[X86] Add schedule module for Gracemont

[HaohaiWen]

Summary

The X86ScheduleGRT.td file is automatically generated by schedtool
(D130897). Some of instruction's scheduling information is based on
measured ADL-P data in uops.info.

[goldstein.w.n]

llvm/lib/Target/X86/X86.td

1082

Imo GMT is more sensible than GRT.

llvm/lib/Target/X86/X86ScheduleGRT.td

73

Is this correct?

537

According to uops.info its 9c.

[RKSimon]

Would this be a good time to add alderlake-p and alderlake-e cpu name aliases as well?

llvm/lib/Target/X86/X86.td

1082

+1 GMT is more commonly used for Gracemont already

1576

This might be better to put next to the other atom cores?

[HaohaiWen]

llvm/lib/Target/X86/X86.td

1082

As I know, GRT is the common abbreviation for Gracemont in Intel.
TRT is Tremont. not TNT in llvm.

llvm/lib/Target/X86/X86ScheduleGRT.td

73

Max lat for ADD (R32 M32) is 5 in uops.info. The extra load latency is 4.

537

Instructions using this schedule write may be overwrite by InstRW.
This 4 cycles is the most common value for all instructions using this SchedWrite.

[HaohaiWen]

In D144393#4142944, @RKSimon wrote:

Would this be a good time to add alderlake-p and alderlake-e cpu name aliases as well?

This model is not yet complete, we still miss lots of port/lat. (see // FIXME: Incompleted schedwrite. and GRTPortInvalid)

Should we rename alderlake-p to other name like alderlake-pc. Alder Lake P is also product series name (https://www.intel.com/content/www/us/en/products/platforms/details/alder-lake-p.html).

[RKSimon]

In D144393#4143219, @HaohaiWen wrote:

In D144393#4142944, @RKSimon wrote:

Would this be a good time to add alderlake-p and alderlake-e cpu name aliases as well?

This model is not yet complete, we still miss lots of port/lat. (see // FIXME: Incompleted schedwrite. and GRTPortInvalid)

Should we rename alderlake-p to other name like alderlake-pc. Alder Lake P is also product series name (https://www.intel.com/content/www/us/en/products/platforms/details/alder-lake-p.html).

Adding extra aliases is cheap (e.g. sandybridge vs corei7-avx etc.), but we can keep the alderlake-p as the default

llvm/lib/Target/X86/X86.td

 include "X86ScheduleZnver2.td"
 include "X86ScheduleZnver3.td"
 include "X86ScheduleBdVer2.td"
 include "X86ScheduleBtVer2.td"
 include "X86SchedSkylakeClient.td"
 include "X86SchedSkylakeServer.td"
 include "X86SchedIceLake.td"
 include "X86SchedAlderlakeP.td"
+include "X86ScheduleGRT.td"
 
 //===----------------------------------------------------------------------===//
 // X86 Processor Feature Lists
 //===----------------------------------------------------------------------===//
 
 def ProcessorFeatures {
   // x86-64 and x86-64-v[234]
   list<SubtargetFeature> X86_64V1Features = [
def ProcessorFeatures {
   list<SubtargetFeature> SRFFeatures =
     !listconcat(ADLFeatures, SRFAdditionalFeatures);
 
   // Grandridge
   list<SubtargetFeature> GRRAdditionalFeatures = [FeatureRAOINT];
   list<SubtargetFeature> GRRFeatures =
     !listconcat(SRFFeatures, GRRAdditionalFeatures);
 
+  // Gracemont
+  list<SubtargetFeature> GRTTuning = [TuningMacroFusion,
+                                      TuningSlow3OpsLEA,
+                                      TuningSlowDivide32,
+                                      TuningSlowDivide64,
+                                      TuningFastScalarFSQRT,
+                                      TuningFastVectorFSQRT,
+                                      TuningFast15ByteNOP,
+                                      TuningFastVariablePerLaneShuffle,
+                                      TuningPOPCNTFalseDeps,
+                                      TuningInsertVZEROUPPER];
+
   // Knights Landing
   list<SubtargetFeature> KNLFeatures = [FeatureX87,
                                         FeatureCX8,
                                         FeatureCMOV,
                                         FeatureMMX,
                                         FeatureFXSR,
                                         FeatureNOPL,
                                         FeatureX86_64,

 def : ProcModel<"raptorlake", AlderlakePModel,
                 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
 def : ProcModel<"meteorlake", AlderlakePModel,
                 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
 def : ProcModel<"graniterapids", SkylakeServerModel,
                 ProcessorFeatures.GNRFeatures, ProcessorFeatures.SPRTuning>;
 def : ProcModel<"emeraldrapids", SkylakeServerModel,
                 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
+def : ProcModel<"gracemont", GRTModel,
+                ProcessorFeatures.ADLFeatures, ProcessorFeatures.GRTTuning>;
 
 // AMD CPUs.
 
 def : Proc<"k6",   [FeatureX87, FeatureCX8, FeatureMMX],
                    [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
 def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow],
                    [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
 def : Proc<"k6-3", [FeatureX87, FeatureCX8, Feature3DNow],

llvm/lib/Target/X86/X86ScheduleGRT.td

+//=------ X86ScheduleGRT.td - X86 Gracemont Scheduling -------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for Gracemont to support instruction
+// scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+
+def GRTModel : SchedMachineModel {
+  // Gracemont can allocate 5 uops per cycle.
+  let IssueWidth = 5; // Based on allocator width.
+  let MicroOpBufferSize = 256; // Based on the reorder buffer.
+  let LoadLatency = 5;
+  let MispredictPenalty = 15;
+
+  // Latency for instructions without latency info.
+  int MaxLatency = 50;
+
+  // This flag is set to allow the scheduler to assign a default model to
+  // unrecognized opcodes.
+  let CompleteModel = 0;
+}
+
+let SchedModel = GRTModel in {
+
+// Gracemont can issue micro-ops to 17 different ports in one cycle.
+def GRTPort00 : ProcResource<1> { let BufferSize = 16; }
+def GRTPort01 : ProcResource<1> { let BufferSize = 16; }
+def GRTPort02 : ProcResource<1> { let BufferSize = 16; }
+def GRTPort03 : ProcResource<1> { let BufferSize = 16; }
+def GRTPort08 : ProcResource<1>;
+def GRTPort09 : ProcResource<1>;
+def GRTPort10 : ProcResource<1>;
+def GRTPort11 : ProcResource<1>;
+def GRTPort12 : ProcResource<1>;
+def GRTPort13 : ProcResource<1>;
+def GRTPort20 : ProcResource<1>;
+def GRTPort21 : ProcResource<1>;
+def GRTPort22 : ProcResource<1>;
+def GRTPort28 : ProcResource<1>;
+def GRTPort29 : ProcResource<1>;
+def GRTPort30 : ProcResource<1>;
+def GRTPort31 : ProcResource<1>;
+
+// Workaround to represent invalid ports. WriteRes shouldn't use this resource.
+def GRTPortInvalid : ProcResource<1>;
+
+// Many micro-ops are capable of issuing on multiple ports.
+def GRTPort00_01_02_03  : ProcResGroup<[GRTPort00, GRTPort01, GRTPort02, GRTPort03]>;
+def GRTPort01_02        : ProcResGroup<[GRTPort01, GRTPort02]>;
+def GRTPort08_09        : ProcResGroup<[GRTPort08, GRTPort09]>;
+def GRTPort10_11        : ProcResGroup<[GRTPort10, GRTPort11]>;
+def GRTPort12_13        : ProcResGroup<[GRTPort12, GRTPort13]>;
+def GRTPort20_21        : ProcResGroup<[GRTPort20, GRTPort21]>;
+def GRTPort20_21_22     : ProcResGroup<[GRTPort20, GRTPort21, GRTPort22]>;
+def GRTPort28_29        : ProcResGroup<[GRTPort28, GRTPort29]>;
+def GRTPort30_31        : ProcResGroup<[GRTPort30, GRTPort31]>;
+
+def GRTPort10_11_12_13 : ProcResGroup<[GRTPort10, GRTPort11, GRTPort12, GRTPort13]> {
+  let BufferSize = 24;
+}
+def GRTPort08_09_30_31 : ProcResGroup<[GRTPort08, GRTPort09, GRTPort30, GRTPort31]> {
+  let BufferSize = 44;
+}
+
+// Integer loads are 4 cycles, so ReadAfterLd registers needn't be available
+// until 4 cycles after the memory operand.
+def : ReadAdvance<ReadAfterLd, 4>;
+
+// Vector loads are 5 cycles, so ReadAfterVec*Ld registers needn't be available
+// until 5 cycles after the memory operand.
+def : ReadAdvance<ReadAfterVecLd, 5>;
+def : ReadAdvance<ReadAfterVecXLd, 5>;
+def : ReadAdvance<ReadAfterVecYLd, 5>;
+
+def : ReadAdvance<ReadInt2Fpu, 0>;
+
+// Many SchedWrites are defined in pairs with and without a folded load.
+// Instructions with folded loads are usually micro-fused, so they only appear
+// as two micro-ops when queued in the reservation station.
+// This multiclass defines the resource usage for variants with and without
+// folded loads.
+multiclass GRTWriteResPair<X86FoldableSchedWrite SchedRW,
+                          list<ProcResourceKind> ExePorts,
+                          int Lat, list<int> Res = [1], int UOps = 1,
+                          int LoadLat = 4, int LoadUOps = 1> {
+  // Register variant is using a single cycle on ExePort.
+  def : WriteRes<SchedRW, ExePorts> {
+    let Latency = Lat;
+    let ResourceCycles = Res;
+    let NumMicroOps = UOps;
+  }
+
+  // Memory variant also uses a cycle on port 10/11 and adds LoadLat cycles to
+  // the latency (default = 4).
+  def : WriteRes<SchedRW.Folded, !listconcat([GRTPort10_11], ExePorts)> {
+    let Latency = !add(Lat, LoadLat);
+    let ResourceCycles = !listconcat([LoadUOps], Res);
+    let NumMicroOps = !add(UOps, LoadUOps);
+  }
+}
+
+//===----------------------------------------------------------------------===//
+// The following definitons are infered by smg.
+//===----------------------------------------------------------------------===//
+
+// Infered SchedWrite definition.
+def : WriteRes<WriteADC, [GRTPort00_01_02_03]> {
+  let Latency = 2;
+}
+def : WriteRes<WriteADCLd, [GRTPort00_01_02_03]> {
+  let Latency = 5;
+}
+defm : GRTWriteResPair<WriteAESDecEnc, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteAESIMC, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteAESKeyGen, [GRTPort20_21], 3, [1], 1, 5>;
+def : WriteRes<WriteALU, [GRTPort00_01_02_03]>;
+def : WriteRes<WriteALULd, [GRTPort00_01_02_03]> {
+  let Latency = 4;
+}
+defm : GRTWriteResPair<WriteBEXTR, [GRTPort01], 4, [1]>;
+defm : GRTWriteResPair<WriteBLS, [GRTPort01], 3, [1]>;
+defm : GRTWriteResPair<WriteBSF, [GRTPort01], 3, [1]>;
+defm : GRTWriteResPair<WriteBSR, [GRTPort01], 3, [1]>;
+def : WriteRes<WriteBSWAP32, [GRTPort00_01_02_03]>;
+def : WriteRes<WriteBSWAP64, [GRTPort00_01_02_03]>;
+defm : GRTWriteResPair<WriteBZHI, [GRTPort01], 3, [1]>;
+def : WriteRes<WriteBitTest, [GRTPort00_01_02_03]>;
+defm : X86WriteRes<WriteBitTestImmLd, [GRTPort00_01_02_03, GRTPort10_11], 6, [1, 1], 2>;
+def : WriteRes<WriteBitTestRegLd, [GRTPort00_01_02_03]> {
+  let Latency = 9;
+}
+def : WriteRes<WriteBitTestSet, [GRTPort00_01_02_03]> {
+  let Latency = 2;
+}
+def : WriteRes<WriteBitTestSetImmLd, [GRTPort00_01_02_03]> {
+  let Latency = 5;
+}
+// FIXME: Incompleted schedwrite.
+defm : X86WriteResUnsupported<WriteBitTestSetRegLd>;
+defm : GRTWriteResPair<WriteBlend, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteBlendY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : GRTWriteResPair<WriteCLMul, [GRTPort20], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCMOV, [GRTPort00_01_02_03], 1, [1]>;
+defm : X86WriteRes<WriteCMPXCHG, [GRTPort00_01_02_03], 5, [5], 5>;
+defm : X86WriteRes<WriteCMPXCHGRMW, [GRTPortInvalid], 8, [1], 7>;
+defm : GRTWriteResPair<WriteCRC32, [GRTPort01], 3, [1]>;
+defm : GRTWriteResPair<WriteCvtI2PD, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtI2PDY, [GRTPort20], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
+defm : GRTWriteResPair<WriteCvtI2PS, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtI2PSY, [GRTPort20], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
+defm : GRTWriteResPair<WriteCvtI2SD, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtI2SS, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtPD2I, [GRTPort20], 3, [1], 1, 5>;
+defm : X86WriteRes<WriteCvtPD2IY, [GRTPort20], 3, [2], 2>;
+defm : X86WriteRes<WriteCvtPD2IYLd, [GRTPort10_11, GRTPort20], 8, [1, 1], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
+defm : GRTWriteResPair<WriteCvtPD2PS, [GRTPort20], 3, [1], 1, 5>;
+defm : X86WriteRes<WriteCvtPD2PSY, [GRTPort20], 3, [2], 2>;
+defm : X86WriteRes<WriteCvtPD2PSYLd, [GRTPort10_11, GRTPort20], 8, [1, 1], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
+defm : GRTWriteResPair<WriteCvtPH2PS, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtPH2PSY, [GRTPort20], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
+defm : GRTWriteResPair<WriteCvtPS2I, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtPS2IY, [GRTPort20], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
+defm : GRTWriteResPair<WriteCvtPS2PD, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtPS2PDY, [GRTPort20], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
+def : WriteRes<WriteCvtPS2PH, [GRTPort20]> {
+  let Latency = 3;
+}
+defm : X86WriteRes<WriteCvtPS2PHSt, [GRTPort12_13, GRTPort20, GRTPort28_29], 3, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteCvtPS2PHY, [GRTPort20], 3, [2], 2>;
+defm : X86WriteRes<WriteCvtPS2PHYSt, [GRTPort12_13, GRTPort20, GRTPort28_29], 3, [2, 2, 2], 6>;
+defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
+defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
+defm : GRTWriteResPair<WriteCvtSD2I, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtSD2SS, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteCvtSS2I, [GRTPort20], 4, [1], 1, 0>;
+defm : GRTWriteResPair<WriteCvtSS2SD, [GRTPort20], 3, [1], 1, 5>;
+defm : X86WriteRes<WriteDPPD, [GRTPortInvalid], 9, [1], 4>;
+defm : X86WriteRes<WriteDPPDLd, [GRTPortInvalid], 13, [1], 5>;
+defm : X86WriteRes<WriteDPPS, [GRTPortInvalid], 16, [1], 8>;
+defm : X86WriteRes<WriteDPPSLd, [GRTPortInvalid], 27, [1], 9>;
+defm : X86WriteRes<WriteDPPSY, [GRTPortInvalid], 16, [1], 15>;
+defm : X86WriteRes<WriteDPPSYLd, [GRTPortInvalid], 30, [1], 17>;
+defm : X86WriteRes<WriteDiv16, [GRTPort00_01_02_03, GRTPort01_02], 11, [2, 1], 3>;
+defm : X86WriteRes<WriteDiv16Ld, [GRTPort00_01_02_03, GRTPort01_02, GRTPort10_11, GRTPort30_31], 15, [1, 1, 1, 1], 4>;
+defm : X86WriteRes<WriteDiv32, [GRTPort00_01_02_03, GRTPort01_02], 11, [2, 1], 3>;
+defm : X86WriteRes<WriteDiv32Ld, [GRTPort00_01_02_03, GRTPort01_02, GRTPort10_11, GRTPort30_31], 15, [1, 1, 1, 1], 4>;
+defm : X86WriteRes<WriteDiv64, [GRTPort00_01_02_03, GRTPort01_02], 11, [2, 1], 3>;
+defm : X86WriteRes<WriteDiv64Ld, [GRTPort00_01_02_03, GRTPort01_02, GRTPort10_11, GRTPort30_31], 15, [1, 1, 1, 1], 4>;
+defm : GRTWriteResPair<WriteDiv8, [GRTPort01_02], 1, [1]>;
+def : WriteRes<WriteEMMS, [GRTPort00_01_02_03]>;
+defm : GRTWriteResPair<WriteFAdd, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFAdd64, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFAdd64X, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFAdd64Y, [GRTPort20_21], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
+defm : GRTWriteResPair<WriteFAddX, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFAddY, [GRTPort20_21], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFAddZ>;
+defm : GRTWriteResPair<WriteFBlend, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFBlendY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+def : WriteRes<WriteFCMOV, [GRTPortInvalid]> {
+  let Latency = 8;
+}
+defm : GRTWriteResPair<WriteFCmp, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFCmp64, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFCmp64X, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFCmp64Y, [GRTPort20_21], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
+defm : GRTWriteResPair<WriteFCmpX, [GRTPort20_21], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFCmpY, [GRTPort20_21], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFCmpZ>;
+defm : GRTWriteResPair<WriteFCom, [GRTPort21], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFComX, [GRTPort21], 4, [1], 1, 5>;
+def : WriteRes<WriteFDiv, [GRTPort20]> {
+  let Latency = 10;
+}
+def : WriteRes<WriteFDivLd, [GRTPortInvalid]> {
+  let Latency = 12;
+}
+defm : GRTWriteResPair<WriteFDiv64, [GRTPort20], 13, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFDiv64X, [GRTPort20], 21, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFDiv64Y, [GRTPort20], 21, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
+defm : GRTWriteResPair<WriteFDivX, [GRTPort20], 15, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFDivY, [GRTPort20], 15, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFDivZ>;
+defm : GRTWriteResPair<WriteFHAdd, [GRTPort20_21, GRTPort20_21_22, GRTPort30_31], 7, [1, 2, 1], 4>;
+defm : GRTWriteResPair<WriteFHAddY, [GRTPort20_21, GRTPort20_21_22, GRTPort30_31], 7, [2, 4, 2], 8, 4, 2>;
+def : WriteRes<WriteFLD0, [GRTPort20_21]>;
+def : WriteRes<WriteFLD1, [GRTPort20]> {
+  let Latency = 4;
+}
+def : WriteRes<WriteFLDC, [GRTPort20]> {
+  let Latency = 4;
+}
+def : WriteRes<WriteFLoad, [GRTPort10_11]> {
+  let Latency = 4;
+}
+def : WriteRes<WriteFLoadX, [GRTPort10_11]> {
+  let Latency = 4;
+}
+defm : X86WriteRes<WriteFLoadY, [GRTPort10_11], 4, [2], 2>;
+defm : GRTWriteResPair<WriteFLogic, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFLogicY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFLogicZ>;
+defm : GRTWriteResPair<WriteFMA, [GRTPort20_21], 6, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFMAX, [GRTPort20_21], 6, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFMAY, [GRTPort20_21], 6, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFMAZ>;
+def : WriteRes<WriteFMOVMSK, [GRTPort20]> {
+  let Latency = 4;
+}
+defm : X86WriteRes<WriteFMaskedLoad, [GRTPort10_11, GRTPort20], 6, [1, 1], 2>;
+defm : X86WriteRes<WriteFMaskedLoadY, [GRTPort10_11, GRTPort20], 6, [2, 2], 4>;
+defm : X86WriteRes<WriteFMaskedStore32, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore32Y, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [2, 2, 2], 6>;
+defm : X86WriteRes<WriteFMaskedStore64, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64Y, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [2, 2, 2], 6>;
+def : WriteRes<WriteFMoveX, [GRTPort20_21_22]>;
+defm : X86WriteRes<WriteFMoveY, [GRTPort20_21_22], 1, [2], 2>;
+defm : X86WriteResUnsupported<WriteFMoveZ>;
+defm : GRTWriteResPair<WriteFMul, [GRTPort20_21], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFMul64, [GRTPort20_21], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFMul64X, [GRTPort20_21], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFMul64Y, [GRTPort20_21], 4, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFMul64Z>;
+defm : GRTWriteResPair<WriteFMulX, [GRTPort20_21], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFMulY, [GRTPort20_21], 4, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFMulZ>;
+defm : GRTWriteResPair<WriteFRcp, [GRTPort20], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFRcpX, [GRTPort20], 5, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFRcpY, [GRTPort20], 5, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFRcpZ>;
+defm : GRTWriteResPair<WriteFRnd, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFRndY, [GRTPort20], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFRndZ>;
+defm : GRTWriteResPair<WriteFRsqrt, [GRTPort20], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFRsqrtX, [GRTPort20], 5, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFRsqrtY, [GRTPort20], 5, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
+defm : GRTWriteResPair<WriteFShuffle, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFShuffle256, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : GRTWriteResPair<WriteFShuffleY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
+def : WriteRes<WriteFSign, [GRTPort20_21]>;
+defm : GRTWriteResPair<WriteFSqrt, [GRTPort20], 11, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFSqrt64, [GRTPort20], 17, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFSqrt64X, [GRTPort20], 29, [1], 1, 5>;
+// Warning: negtive load latency.
+defm : GRTWriteResPair<WriteFSqrt64Y, [GRTPort20], 48, [2], 2, -14, 2>;
+defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
+def : WriteRes<WriteFSqrt80, [GRTPort20]> {
+  let Latency = 13;
+}
+defm : GRTWriteResPair<WriteFSqrtX, [GRTPort20], 17, [1], 1, 2>;
+// Warning: negtive load latency.
+defm : GRTWriteResPair<WriteFSqrtY, [GRTPort20], 24, [2], 2, -5, 2>;
+defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
+defm : X86WriteRes<WriteFStore, [GRTPort08_09, GRTPort12_13], 0, [1, 1], 2>;
+defm : X86WriteResUnsupported<WriteFStoreNT>;
+defm : X86WriteRes<WriteFStoreNTX, [GRTPort08_09, GRTPort12_13], 0, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreNTY, [GRTPort08_09, GRTPort12_13], 0, [2, 2], 4>;
+defm : X86WriteRes<WriteFStoreX, [GRTPort08_09, GRTPort12_13], 0, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreY, [GRTPort08_09, GRTPort12_13], 0, [2, 2], 4>;
+defm : GRTWriteResPair<WriteFTest, [GRTPort21], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFTestY, [GRTPort21], 4, [2], 2, 5, 2>;
+defm : GRTWriteResPair<WriteFVarBlend, [GRTPort20_21], 3, [1], 1, 5>;
+defm : X86WriteRes<WriteFVarBlendY, [GRTPort20_21, GRTPort20_21_22], 6, [2, 6], 8>;
+defm : X86WriteRes<WriteFVarBlendYLd, [GRTPort10_11, GRTPort20_21, GRTPort20_21_22], 9, [2, 2, 4], 8>;
+defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
+defm : GRTWriteResPair<WriteFVarShuffle, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteFVarShuffle256, [GRTPort20], 8, [2], 2, 10, 2>;
+defm : GRTWriteResPair<WriteFVarShuffleY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
+def : WriteRes<WriteFence, [GRTPort00_01_02_03]> {
+  let Latency = GRTModel.MaxLatency;
+}
+defm : X86WriteRes<WriteIDiv16, [GRTPort00_01_02_03, GRTPort01_02], 11, [2, 1], 3>;
+defm : X86WriteRes<WriteIDiv16Ld, [GRTPort00_01_02_03, GRTPort01_02, GRTPort10_11, GRTPort30_31], 15, [1, 1, 1, 1], 4>;
+defm : X86WriteRes<WriteIDiv32, [GRTPort00_01_02_03, GRTPort01_02], 11, [2, 1], 3>;
+defm : X86WriteRes<WriteIDiv32Ld, [GRTPort00_01_02_03, GRTPort01_02, GRTPort10_11, GRTPort30_31], 15, [1, 1, 1, 1], 4>;
+defm : X86WriteRes<WriteIDiv64, [GRTPort00_01_02_03, GRTPort01_02], 11, [2, 1], 3>;
+defm : X86WriteRes<WriteIDiv64Ld, [GRTPort00_01_02_03, GRTPort01_02, GRTPort10_11, GRTPort30_31], 15, [1, 1, 1, 1], 4>;
+defm : GRTWriteResPair<WriteIDiv8, [GRTPort01_02], 9, [1]>;
+defm : GRTWriteResPair<WriteIMul16, [GRTPort00_01_02_03, GRTPort01_02], 8, [4, 1], 5>;
+defm : X86WriteRes<WriteIMul16Imm, [GRTPort00_01_02_03, GRTPort01_02], 5, [2, 1], 3>;
+defm : X86WriteRes<WriteIMul16ImmLd, [GRTPort00_01_02_03, GRTPort01_02], 5, [2, 1], 3>;
+defm : GRTWriteResPair<WriteIMul16Reg, [GRTPort00_01_02_03, GRTPort01_02], 8, [4, 1], 5>;
+defm : GRTWriteResPair<WriteIMul32, [GRTPort01_02], 3, [1]>;
+def : WriteRes<WriteIMul32Imm, [GRTPort01_02]> {
+  let Latency = 3;
+}
+def : WriteRes<WriteIMul32ImmLd, [GRTPort01_02]> {
+  let Latency = 3;
+}
+defm : GRTWriteResPair<WriteIMul32Reg, [GRTPort01_02], 3, [1]>;
+defm : GRTWriteResPair<WriteIMul64, [GRTPort01_02], 5, [1]>;
+def : WriteRes<WriteIMul64Imm, [GRTPort01_02]> {
+  let Latency = 5;
+}
+def : WriteRes<WriteIMul64ImmLd, [GRTPort01_02]> {
+  let Latency = 5;
+}
+defm : GRTWriteResPair<WriteIMul64Reg, [GRTPort01_02], 5, [1]>;
+defm : GRTWriteResPair<WriteIMul8, [GRTPort01_02], 3, [1]>;
+def : WriteRes<WriteIMulH, []> {
+  let Latency = 3;
+}
+// FIXME: Incompleted schedwrite.
+defm : X86WriteResUnsupported<WriteIMulHLd>;
+defm : X86WriteRes<WriteJump, [GRTPort08_09, GRTPort12_13, GRTPort30_31], 1, [1, 1, 1], 3>;
+def : WriteRes<WriteJumpLd, [GRTPort00_01_02_03]> {
+  let Latency = GRTModel.MaxLatency;
+}
+def : WriteRes<WriteLAHFSAHF, [GRTPort00_01_02_03]>;
+def : WriteRes<WriteLDMXCSR, [GRTPort00_01_02_03]> {
+  let Latency = GRTModel.MaxLatency;
+}
+def : WriteRes<WriteLEA, [GRTPort00_01_02_03]>;
+defm : GRTWriteResPair<WriteLZCNT, [GRTPort01], 3, [1]>;
+def : WriteRes<WriteLoad, [GRTPort10_11]> {
+  let Latency = 4;
+}
+def : WriteRes<WriteMMXMOVMSK, [GRTPort20]> {
+  let Latency = 5;
+}
+defm : GRTWriteResPair<WriteMPSAD, [GRTPort20, GRTPort20_21_22], 4, [1, 2], 3, 6>;
+defm : GRTWriteResPair<WriteMPSADY, [GRTPort20, GRTPort20_21_22], 6, [2, 4], 6, 4, 2>;
+defm : X86WriteRes<WriteMULX32, [GRTPort01_02], 3, [1], 0>;
+// FIXME: Incompleted schedwrite.
+defm : X86WriteResUnsupported<WriteMULX32Ld>;
+defm : X86WriteRes<WriteMULX64, [GRTPort01_02], 5, [1], 0>;
+// FIXME: Incompleted schedwrite.
+defm : X86WriteResUnsupported<WriteMULX64Ld>;
+def : WriteRes<WriteMicrocoded, [GRTPort30_31]> {
+  let Latency = GRTModel.MaxLatency;
+}
+def : WriteRes<WriteMove, [GRTPort00_01_02_03]>;
+def : WriteRes<WriteNop, [GRTPort20_21]>;
+def : WriteRes<WritePCmpEStrI, [GRTPort20_21_22]> {
+  let Latency = 20;
+}
+def : WriteRes<WritePCmpEStrILd, [GRTPort00_01_02_03]> {
+  let Latency = 25;
+}
+def : WriteRes<WritePCmpEStrM, [GRTPort20_21_22]> {
+  let Latency = 20;
+}
+def : WriteRes<WritePCmpEStrMLd, [GRTPort00_01_02_03]> {
+  let Latency = 20;
+}
+def : WriteRes<WritePCmpIStrI, [GRTPort20_21_22]> {
+  let Latency = 18;
+}
+def : WriteRes<WritePCmpIStrILd, [GRTPort00_01_02_03]> {
+  let Latency = 24;
+}
+def : WriteRes<WritePCmpIStrM, [GRTPort20_21_22]> {
+  let Latency = 18;
+}
+def : WriteRes<WritePCmpIStrMLd, [GRTPort00_01_02_03]> {
+  let Latency = 19;
+}
+defm : GRTWriteResPair<WritePHAdd, [GRTPort00_01_02_03, GRTPort20_21_22], 6, [1, 5], 6>;
+defm : GRTWriteResPair<WritePHAddX, [GRTPort20_21_22], 7, [7], 7>;
+defm : GRTWriteResPair<WritePHAddY, [GRTPort20_21_22], 7, [14], 14, 4, 2>;
+defm : GRTWriteResPair<WritePHMINPOS, [GRTPort20], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WritePMULLD, [GRTPort20], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WritePMULLDY, [GRTPort20], 4, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WritePMULLDZ>;
+defm : GRTWriteResPair<WritePOPCNT, [GRTPort01], 3, [1]>;
+// FIXME: Incompleted schedwrite.
+defm : X86WriteResUnsupported<WritePSADBW>;
+// FIXME: Incompleted schedwrite.
+defm : X86WriteResUnsupported<WritePSADBWLd>;
+defm : GRTWriteResPair<WritePSADBWX, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WritePSADBWY, [GRTPort20], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WritePSADBWZ>;
+defm : X86WriteRes<WriteRMW, [GRTPort08_09, GRTPort10_11], 1, [1, 1], 2>;
+def : WriteRes<WriteRotate, [GRTPort01]> {
+  let Latency = 2;
+}
+def : WriteRes<WriteRotateLd, [GRTPort00_01_02_03]> {
+  let Latency = 6;
+}
+def : WriteRes<WriteRotateCL, [GRTPort01]> {
+  let Latency = 9;
+}
+def : WriteRes<WriteRotateCLLd, [GRTPort00_01_02_03]> {
+  let Latency = 6;
+}
+def : WriteRes<WriteSETCC, [GRTPort00_01_02_03]>;
+defm : X86WriteRes<WriteSETCCStore, [GRTPort00_01_02_03, GRTPort08_09, GRTPort12_13], 1, [1, 1, 1], 3>;
+def : WriteRes<WriteSHDmrcl, [GRTPort00_01_02_03]> {
+  let Latency = 16;
+}
+defm : X86WriteRes<WriteSHDmri, [GRTPort08_09, GRTPort10_11], 4, [1, 1], 2>;
+def : WriteRes<WriteSHDrrcl, [GRTPort00_01_02_03]> {
+  let Latency = 6;
+}
+def : WriteRes<WriteSHDrri, [GRTPortInvalid]> {
+  let Latency = 0;
+}
+defm : X86WriteRes<WriteSTMXCSR, [GRTPortInvalid], 4, [1], 3>;
+def : WriteRes<WriteShift, [GRTPort00_01_02_03]>;
+def : WriteRes<WriteShiftLd, [GRTPort00_01_02_03]> {
+  let Latency = 6;
+}
+def : WriteRes<WriteShiftCL, [GRTPort00_01_02_03]>;
+def : WriteRes<WriteShiftCLLd, [GRTPort00_01_02_03]> {
+  let Latency = 6;
+}
+defm : GRTWriteResPair<WriteShuffle, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteShuffle256, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : GRTWriteResPair<WriteShuffleX, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteShuffleY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteShuffleZ>;
+defm : X86WriteRes<WriteStore, [GRTPort08_09, GRTPort12_13], 0, [1, 1], 2>;
+defm : X86WriteRes<WriteStoreNT, [GRTPort08_09, GRTPort12_13], 0, [1, 1], 2>;
+def : WriteRes<WriteSystem, [GRTPort00_01_02_03]> {
+  let Latency = GRTModel.MaxLatency;
+}
+defm : GRTWriteResPair<WriteTZCNT, [GRTPort01], 3, [1]>;
+defm : GRTWriteResPair<WriteVPMOV256, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteRes<WriteVarBlend, [GRTPort20_21, GRTPort20_21_22], 7, [1, 3], 4>;
+defm : X86WriteRes<WriteVarBlendLd, [GRTPort10_11, GRTPort20_21], 9, [1, 1], 2>;
+defm : X86WriteRes<WriteVarBlendY, [GRTPort20_21, GRTPort20_21_22], 7, [2, 6], 8>;
+defm : X86WriteRes<WriteVarBlendYLd, [GRTPort10_11, GRTPort20_21, GRTPort20_21_22], 10, [2, 2, 4], 8>;
+defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
+defm : GRTWriteResPair<WriteVarShuffle, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVarShuffle256, [GRTPort20], 6, [2], 2, 0, 2>;
+defm : GRTWriteResPair<WriteVarShuffleX, [GRTPort21], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVarShuffleY, [GRTPort21], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
+defm : GRTWriteResPair<WriteVarVecShift, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVarVecShiftY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
+defm : GRTWriteResPair<WriteVecALU, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVecALUX, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVecALUY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteVecALUZ>;
+def : WriteRes<WriteVecExtract, [GRTPort20]> {
+  let Latency = 4;
+}
+defm : X86WriteRes<WriteVecExtractSt, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [1, 1, 1], 3>;
+defm : GRTWriteResPair<WriteVecIMul, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVecIMulX, [GRTPort20], 3, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVecIMulY, [GRTPort20], 3, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
+def : WriteRes<WriteVecInsert, [GRTPort20]>;
+defm : X86WriteRes<WriteVecInsertLd, [GRTPort10_11, GRTPort20_21_22], 6, [1, 1], 2>;
+def : WriteRes<WriteVecLoad, [GRTPort10_11]> {
+  let Latency = 4;
+}
+def : WriteRes<WriteVecLoadNT, [GRTPort10_11]> {
+  let Latency = 4;
+}
+defm : X86WriteRes<WriteVecLoadNTY, [GRTPort10_11], 4, [2], 2>;
+def : WriteRes<WriteVecLoadX, [GRTPort10_11]> {
+  let Latency = 4;
+}
+defm : X86WriteRes<WriteVecLoadY, [GRTPort10_11], 4, [2], 2>;
+// FIXME: Incompleted schedwrite.
+defm : X86WriteResUnsupported<WriteVecLogic>;
+// FIXME: Incompleted schedwrite.
+defm : X86WriteResUnsupported<WriteVecLogicLd>;
+defm : GRTWriteResPair<WriteVecLogicX, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVecLogicY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
+def : WriteRes<WriteVecMOVMSK, [GRTPort20]> {
+  let Latency = 4;
+}
+defm : X86WriteRes<WriteVecMOVMSKY, [GRTPort20], 4, [2], 2>;
+defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
+defm : X86WriteRes<WriteVecMaskedLoad, [GRTPort10_11, GRTPort20], 6, [1, 1], 2>;
+defm : X86WriteRes<WriteVecMaskedLoadY, [GRTPort10_11, GRTPort20], 6, [2, 2], 4>;
+defm : X86WriteRes<WriteVecMaskedStore32, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore32Y, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [2, 2, 2], 6>;
+defm : X86WriteRes<WriteVecMaskedStore64, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64Y, [GRTPort12_13, GRTPort20, GRTPort28_29], 1, [2, 2, 2], 6>;
+def : WriteRes<WriteVecMove, [GRTPort20_21_22]>;
+def : WriteRes<WriteVecMoveFromGpr, [GRTPort20]>;
+def : WriteRes<WriteVecMoveToGpr, [GRTPort20]> {
+  let Latency = 4;
+}
+def : WriteRes<WriteVecMoveX, [GRTPort20_21_22]>;
+defm : X86WriteRes<WriteVecMoveY, [GRTPort20_21_22], 1, [2], 2>;
+defm : X86WriteResUnsupported<WriteVecMoveZ>;
+defm : GRTWriteResPair<WriteVecShift, [GRTPort20_21_22], 1, [1], 1, 5>;
+def : WriteRes<WriteVecShiftImm, [GRTPort20_21_22]>;
+def : WriteRes<WriteVecShiftImmX, [GRTPort20_21_22]>;
+defm : X86WriteResUnsupported<WriteVecShiftImmXLd>;
+defm : X86WriteRes<WriteVecShiftImmY, [GRTPort20_21_22], 1, [2], 2>;
+defm : X86WriteResUnsupported<WriteVecShiftImmYLd>;
+defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
+defm : GRTWriteResPair<WriteVecShiftX, [GRTPort20_21_22], 1, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVecShiftY, [GRTPort20_21_22], 1, [2], 2, 5, 2>;
+defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
+defm : X86WriteRes<WriteVecStore, [GRTPort08_09, GRTPort12_13], 0, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreNT, [GRTPort08_09, GRTPort12_13], 0, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreNTY, [GRTPort08_09, GRTPort12_13], 0, [2, 2], 4>;
+defm : X86WriteRes<WriteVecStoreX, [GRTPort08_09, GRTPort12_13], 0, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreY, [GRTPort08_09, GRTPort12_13], 0, [2, 2], 4>;
+defm : GRTWriteResPair<WriteVecTest, [GRTPort21], 4, [1], 1, 5>;
+defm : GRTWriteResPair<WriteVecTestY, [GRTPort21], 4, [2], 2, 5, 2>;
+defm : X86WriteRes<WriteXCHG, [GRTPort00_01_02_03], 4, [4], 4>;
+def : WriteRes<WriteZero, []>;
+
+// Infered SchedWriteRes and InstRW definition.
+
+def GRTWriteResGroup0 : SchedWriteRes<[GRTPort00_01_02_03]>;
+def : InstRW<[GRTWriteResGroup0], (instregex "^ADC(8|16|32)ri$",
+                                             "^ADC(16|32|64)ri8$",
+                                             "^ADC(32|64)i32$",
+                                             "^BTS(16|32|64)r(r|i8)$",
+                                             "^ENDBR(32|64)$",
+                                             "^MOV64(cr|rc|rd)$",
+                                             "^RDSSP(D|Q)$",
+                                             "^RO(L|R)(8|16|32|64)r(1|i|CL)$",
+                                             "^XADD(16|32|64)rr$")>;
+def : InstRW<[GRTWriteResGroup0], (instrs ADC16i16,
+                                          ADC64ri32,
+                                          ADC8i8,
+                                          ARPL16rr,
+                                          MOV64dr,
+                                          NOOP,
+                                          VZEROALL,
+                                          VZEROUPPER)>;
+
+def GRTWriteResGroup1 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort08_09, GRTPort10_11]> {
+  let Latency = 5;
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup1], (instregex "^ADC(8|16|32)mi$",
+                                             "^ADC(16|32|64)mi8$")>;
+def : InstRW<[GRTWriteResGroup1], (instrs ADC64mi32)>;
+
+def GRTWriteResGroup2 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort10_11]> {
+  let Latency = 6;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup2, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^SARX(32|64)rm$")>;
+def : InstRW<[GRTWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
+                                                                                                                                        "^AD(C|O)X(32|64)rm$")>;
+
+def GRTWriteResGroup3 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort10_11]> {
+  let Latency = 5;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup3], (instregex "^MOV(8|16)ao(16|32|64)$",
+                                             "^MOV(8|16)rm$",
+                                             "^MOVBE(16|32|64)rm$",
+                                             "^MOVSX(16|32|64)rm(8|16|32)$",
+                                             "^MOVZX16rm(8|16)$",
+                                             "^RORX(32|64)mi$",
+                                             "^TEST(8|16|32)mi$")>;
+def : InstRW<[GRTWriteResGroup3], (instrs ARPL16mr,
+                                          MOV8rm_NOREX,
+                                          MOVSX32rm8_NOREX,
+                                          TEST64mi32)>;
+def : InstRW<[GRTWriteResGroup3, ReadAfterLd], (instregex "^A(D|N)D(8|16|32|64)rm$",
+                                                          "^ANDN(32|64)rm$",
+                                                          "^(CMP|SUB)(8|16|32|64)rm$",
+                                                          "^(X?)OR(8|16|32|64)rm$")>;
+def : InstRW<[GRTWriteResGroup3, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^SH(L|R)X(32|64)rm$",
+                                                                                                                           "^TEST(8|16|32|64)mr$")>;
+
+def GRTWriteResGroup4 : SchedWriteRes<[GRTPort10_11, GRTPort21]> {
+  let Latency = 9;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup4], (instregex "^ADD_F(32|64)m$",
+                                             "^SUB(R?)_F(32|64)m$")>;
+def : InstRW<[GRTWriteResGroup4, ReadAfterVecXLd], (instregex "^SHA(1|256)MSG(1|2)rm$")>;
+def : InstRW<[GRTWriteResGroup4, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
+
+def GRTWriteResGroup5 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 12;
+}
+def : InstRW<[GRTWriteResGroup5], (instregex "^ADD_FI(16|32)m$",
+                                             "^FICOM(P?)(16|32)m$",
+                                             "^SUB(R?)_FI(16|32)m$")>;
+
+def GRTWriteResGroup6 : SchedWriteRes<[GRTPort21]> {
+  let Latency = 4;
+}
+def : InstRW<[GRTWriteResGroup6], (instregex "^SHA(1|256)MSG(1|2)rr$",
+                                             "^SUB(R?)_FrST0$")>;
+def : InstRW<[GRTWriteResGroup6], (instrs ADD_FrST0,
+                                          FCOMPP,
+                                          SHA1NEXTErr)>;
+
+def GRTWriteResGroup7 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = GRTModel.MaxLatency;
+}
+def : InstRW<[GRTWriteResGroup7], (instregex "^AES(DE|EN)C((WIDE)?)(128|256)KL$",
+                                             "^INCSSP(D|Q)$",
+                                             "^IST(T?)_FP(16|32|64)m$",
+                                             "^IST_F(16|32)m$",
+                                             "^LTR(m|r)$",
+                                             "^S(G|I)DT(16|32)m$",
+                                             "^VMPTR(LD|ST)m$",
+                                             "^XRSTORS((64)?)$")>;
+def : InstRW<[GRTWriteResGroup7], (instrs HLT,
+                                          LCMPXCHG16B,
+                                          SAVEPREVSSP,
+                                          SETSSBSY,
+                                          VMCLEARm,
+                                          VMXON)>;
+
+def GRTWriteResGroup8 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 37;
+}
+def : InstRW<[GRTWriteResGroup8], (instregex "^BT(C|R|S)16mr$")>;
+
+def GRTWriteResGroup9 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 35;
+}
+def : InstRW<[GRTWriteResGroup9], (instregex "^BT(C|R|S)32mr$",
+                                             "^BT(R|S)64mr$")>;
+
+def GRTWriteResGroup10 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 36;
+}
+def : InstRW<[GRTWriteResGroup10], (instrs BTC64mr)>;
+
+def GRTWriteResGroup11 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 5;
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup11], (instrs CALL64m)>;
+
+def GRTWriteResGroup12 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 2;
+}
+def : InstRW<[GRTWriteResGroup12], (instregex "^C(DQ|QO)$",
+                                              "^SAR(8|16|32|64)rCL$",
+                                              "^SARX(32|64)rr$")>;
+
+def GRTWriteResGroup13 : SchedWriteRes<[GRTPort08_09, GRTPort12_13]> {
+  let Latency = 0;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup13], (instregex "^CLFLUSH((OPT)?)$",
+                                              "^MOV(8|16|32)o16a$",
+                                              "^MOV(8|16|32|64)o(32|64)a$")>;
+def : InstRW<[GRTWriteResGroup13], (instrs CLDEMOTE,
+                                           CLWB,
+                                           SFENCE)>;
+
+def GRTWriteResGroup14 : SchedWriteRes<[GRTPort30_31]> {
+  let Latency = GRTModel.MaxLatency;
+}
+def : InstRW<[GRTWriteResGroup14], (instregex "^IRET(16|32|64)$",
+                                              "^L(F|G|S)S(32|64)rm$",
+                                              "^POP(F|G)S(16|64)$",
+                                              "^(RD|WR)MSR$",
+                                              "^SYSE(XIT|NTER)$",
+                                              "^VM(CALL|XOFF)$",
+                                              "^VMREAD64(m|r)r$",
+                                              "^VMWRITE64r(m|r)$")>;
+def : InstRW<[GRTWriteResGroup14], (instrs CLTS,
+                                           GETSEC,
+                                           LMSW16r,
+                                           MOV16sm,
+                                           PCONFIG)>;
+
+def GRTWriteResGroup15 : SchedWriteRes<[GRTPort01, GRTPort10_11]> {
+  let Latency = 5;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup15], (instregex "^CMP(8|16|32)mi$",
+                                              "^CMP(16|32|64)mi8$")>;
+def : InstRW<[GRTWriteResGroup15], (instrs CMP64mi32)>;
+def : InstRW<[GRTWriteResGroup15, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;
+
+def GRTWriteResGroup16 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 30;
+  let NumMicroOps = 16;
+}
+def : InstRW<[GRTWriteResGroup16], (instrs CMPXCHG16B)>;
+
+def GRTWriteResGroup17 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 15;
+  let NumMicroOps = 12;
+}
+def : InstRW<[GRTWriteResGroup17], (instrs CMPXCHG8B)>;
+
+def GRTWriteResGroup18 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 9;
+  let NumMicroOps = 7;
+}
+def : InstRW<[GRTWriteResGroup18], (instrs CMPXCHG8rm)>;
+
+def GRTWriteResGroup19 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let Latency = 8;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup19], (instregex "^CVT(T?)SS2SI((64)?)rm((_Int)?)$")>;
+
+def GRTWriteResGroup20 : SchedWriteRes<[GRTPort20]> {
+  let Latency = 3;
+}
+def : InstRW<[GRTWriteResGroup20], (instregex "^CVT(T?)SS2SI((64)?)rr_Int$")>;
+def : InstRW<[GRTWriteResGroup20, ReadDefault], (instregex "^CVT(T?)SS2SI((64)?)rr$")>;
+
+def GRTWriteResGroup21 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let ResourceCycles = [3];
+  let Latency = 4;
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup21], (instrs CWD)>;
+
+def GRTWriteResGroup22 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let Latency = 18;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup22], (instregex "^DIV(R?)_F32m$")>;
+def : InstRW<[GRTWriteResGroup22], (instrs DIV_F64m)>;
+
+def GRTWriteResGroup23 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let Latency = 9;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup23], (instregex "^ILD_F(16|32|64)m$",
+                                              "^VPDP(BU|WS)SD(S?)rm$")>;
+def : InstRW<[GRTWriteResGroup23], (instrs DIVR_F64m)>;
+def : InstRW<[GRTWriteResGroup23, ReadAfterVecXLd], (instregex "^(V?)GF2P8MULBrm$",
+                                                               "^(V?)PCMPGTQrm$")>;
+def : InstRW<[GRTWriteResGroup23, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,
+                                                            SHA256RNDS2rm)>;
+
+def GRTWriteResGroup24 : SchedWriteRes<[GRTPort20]> {
+  let Latency = 13;
+}
+def : InstRW<[GRTWriteResGroup24], (instregex "^DIV(R?)_FrST0$")>;
+
+def GRTWriteResGroup25 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let Latency = 15;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup25, ReadAfterVecLd], (instregex "^(V?)DIVSSrm((_Int)?)$")>;
+
+def GRTWriteResGroup26 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = GRTModel.MaxLatency;
+}
+def : InstRW<[GRTWriteResGroup26], (instregex "^FAR(JMP|CALL)64m$",
+                                              "^FN(CLEX|INIT)$",
+                                              "^POPF(16|64)$")>;
+def : InstRW<[GRTWriteResGroup26], (instrs PAUSE)>;
+
+def GRTWriteResGroup27 : SchedWriteRes<[GRTPort20_21]>;
+def : InstRW<[GRTWriteResGroup27], (instregex "^F(DE|IN)CSTP$",
+                                              "^(LD|ST)_Frr$")>;
+def : InstRW<[GRTWriteResGroup27], (instrs FFREE,
+                                           ST_FPrr)>;
+
+def GRTWriteResGroup28 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort20_21]> {
+  let ResourceCycles = [1, 2];
+  let Latency = 3;
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup28], (instrs FFREEP)>;
+
+def GRTWriteResGroup29 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort20]> {
+  let ResourceCycles = [2, 1];
+  let Latency = 6;
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup29], (instrs FNSTSW16r)>;
+
+def GRTWriteResGroup30 : SchedWriteRes<[GRTPort10_11, GRTPort20_21]> {
+  let Latency = 9;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup30, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$")>;
+
+def GRTWriteResGroup31 : SchedWriteRes<[GRTPort20_21]> {
+  let Latency = 4;
+}
+def : InstRW<[GRTWriteResGroup31], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrri$")>;
+
+def GRTWriteResGroup32 : SchedWriteRes<[GRTPort20]> {
+  let Latency = 4;
+}
+def : InstRW<[GRTWriteResGroup32], (instregex "^(V?)GF2P8MULBrr$",
+                                              "^(V?)PCMPGTQrr$",
+                                              "^VCVTSD2S(S|I64)rr_Int$",
+                                              "^VCVTS(D2SS|S2SD)rr$",
+                                              "^VPDP(BU|WS)SD(S?)rr$")>;
+def : InstRW<[GRTWriteResGroup32], (instrs SHA1RNDS4rri,
+                                           SHA256RNDS2rr,
+                                           VCVTSS2SDrr_Int)>;
+def : InstRW<[GRTWriteResGroup32, ReadDefault], (instregex "^VCVT(T?)SD2SI64rr$")>;
+def : InstRW<[GRTWriteResGroup32, ReadDefault], (instrs VCVTTSD2SIrr)>;
+def : InstRW<[GRTWriteResGroup32, ReadDefault, ReadInt2Fpu], (instregex "^VCVTSI((64)?)2S(D|S)rr((_Int)?)$")>;
+def : InstRW<[GRTWriteResGroup32, ReadDefault, ReadInt2Fpu], (instrs VPINSRWrr)>;
+
+def GRTWriteResGroup33 : SchedWriteRes<[GRTPort10_11, GRTPort30_31]> {
+  let Latency = 5;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup33], (instregex "^PTWRITE((64)?)m$")>;
+def : InstRW<[GRTWriteResGroup33], (instrs JMP64m)>;
+
+def GRTWriteResGroup34 : SchedWriteRes<[GRTPort30_31]>;
+def : InstRW<[GRTWriteResGroup34], (instregex "^PTWRITE((64)?)r$")>;
+def : InstRW<[GRTWriteResGroup34], (instrs JMP64r)>;
+
+def GRTWriteResGroup35 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 79;
+  let NumMicroOps = 27;
+}
+def : InstRW<[GRTWriteResGroup35], (instregex "^LAR(16|32|64)rm$")>;
+
+def GRTWriteResGroup36 : SchedWriteRes<[GRTPort30_31]> {
+  let Latency = 72;
+}
+def : InstRW<[GRTWriteResGroup36], (instrs LAR16rr)>;
+
+def GRTWriteResGroup37 : SchedWriteRes<[GRTPort30_31]> {
+  let Latency = 73;
+}
+def : InstRW<[GRTWriteResGroup37], (instregex "^LAR(32|64)rr$")>;
+
+def GRTWriteResGroup38 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 8;
+}
+def : InstRW<[GRTWriteResGroup38], (instregex "^LCMPXCHG(16|32|64)$")>;
+
+def GRTWriteResGroup39 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 9;
+}
+def : InstRW<[GRTWriteResGroup39], (instrs LCMPXCHG8)>;
+
+def GRTWriteResGroup40 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort10_11]> {
+  let ResourceCycles = [3, 1];
+  let Latency = 7;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup40], (instrs LEAVE64,
+                                           POP16r)>;
+
+def GRTWriteResGroup41 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = GRTModel.MaxLatency;
+  let NumMicroOps = 21;
+}
+def : InstRW<[GRTWriteResGroup41], (instrs LLDT16m)>;
+
+def GRTWriteResGroup42 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = GRTModel.MaxLatency;
+  let NumMicroOps = 19;
+}
+def : InstRW<[GRTWriteResGroup42], (instrs LLDT16r)>;
+
+def GRTWriteResGroup43 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = GRTModel.MaxLatency;
+  let NumMicroOps = 16;
+}
+def : InstRW<[GRTWriteResGroup43], (instrs LMSW16m)>;
+
+def GRTWriteResGroup44 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 78;
+  let NumMicroOps = 16;
+}
+def : InstRW<[GRTWriteResGroup44], (instrs LSL16rm)>;
+
+def GRTWriteResGroup45 : SchedWriteRes<[GRTPort30_31]> {
+  let Latency = 70;
+}
+def : InstRW<[GRTWriteResGroup45], (instregex "^LSL(16|32|64)rr$")>;
+
+def GRTWriteResGroup46 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 77;
+  let NumMicroOps = 16;
+}
+def : InstRW<[GRTWriteResGroup46], (instregex "^LSL(32|64)rm$")>;
+
+def GRTWriteResGroup47 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 6;
+}
+def : InstRW<[GRTWriteResGroup47], (instregex "^LXADD(8|16|32|64)$")>;
+
+def GRTWriteResGroup48 : SchedWriteRes<[GRTPort08_09, GRTPort12_13]> {
+  let Latency = 602;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup48], (instrs MMX_MASKMOVQ64)>;
+
+def GRTWriteResGroup49 : SchedWriteRes<[GRTPort20]> {
+  let Latency = 5;
+}
+def : InstRW<[GRTWriteResGroup49], (instregex "^VMOVMSKP(D|S)rr$")>;
+def : InstRW<[GRTWriteResGroup49], (instrs MMX_MOVD64to64rr,
+                                           MUL_FrST0,
+                                           VCVTSD2SIrr_Int,
+                                           VEXTRACTPSrr)>;
+def : InstRW<[GRTWriteResGroup49, ReadDefault], (instrs VCVTSD2SIrr)>;
+
+def GRTWriteResGroup50 : SchedWriteRes<[GRTPort20_21_22]> {
+  let Latency = 5;
+}
+def : InstRW<[GRTWriteResGroup50], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
+
+def GRTWriteResGroup51 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort10_11, GRTPort20_21_22]> {
+  let ResourceCycles = [1, 1, 3];
+  let Latency = 8;
+  let NumMicroOps = 5;
+}
+def : InstRW<[GRTWriteResGroup51, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)Drm$")>;
+def : InstRW<[GRTWriteResGroup51, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)Drm$")>;
+
+def GRTWriteResGroup52 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort20_21_22]> {
+  let ResourceCycles = [1, 3];
+  let Latency = 4;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup52], (instregex "^MMX_PH(ADD|SUB)Drr$",
+                                              "^(V?)PH(ADD|SUB)Drr$")>;
+
+def GRTWriteResGroup53 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 3;
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup53], (instrs MOV16ms)>;
+
+def GRTWriteResGroup54 : SchedWriteRes<[GRTPort10_11]> {
+  let Latency = 4;
+}
+def : InstRW<[GRTWriteResGroup54], (instregex "^MOV32ao(16|32|64)$",
+                                              "^MOV64ao(32|64)$")>;
+
+def GRTWriteResGroup55 : SchedWriteRes<[GRTPort01]> {
+  let Latency = 3;
+}
+def : InstRW<[GRTWriteResGroup55], (instregex "^P(DEP|EXT)(32|64)rr$")>;
+def : InstRW<[GRTWriteResGroup55], (instrs MOV64rs)>;
+
+def GRTWriteResGroup56 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort08_09, GRTPort12_13]> {
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup56], (instregex "^MOVBE(16|32|64)mr$")>;
+
+def GRTWriteResGroup57 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let Latency = 10;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup57], (instregex "^MUL_F(32|64)m$")>;
+
+def GRTWriteResGroup58 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 13;
+}
+def : InstRW<[GRTWriteResGroup58], (instregex "^MUL_FI(16|32)m$")>;
+
+def GRTWriteResGroup59 : SchedWriteRes<[GRTPort01, GRTPort10_11]> {
+  let Latency = 7;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup59, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
+
+def GRTWriteResGroup60 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 7;
+  let NumMicroOps = 6;
+}
+def : InstRW<[GRTWriteResGroup60], (instregex "^SH(L|R)D32mrCL$")>;
+def : InstRW<[GRTWriteResGroup60], (instrs POP16rmm)>;
+
+def GRTWriteResGroup61 : SchedWriteRes<[GRTPort08_09, GRTPort10_11]> {
+  let Latency = 4;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup61], (instregex "^PUSH(16|64)rmm$")>;
+def : InstRW<[GRTWriteResGroup61], (instrs PREFETCHT0)>;
+
+def GRTWriteResGroup62 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 9;
+}
+def : InstRW<[GRTWriteResGroup62], (instregex "^PUSHF(16|64)$")>;
+
+def GRTWriteResGroup63 : SchedWriteRes<[GRTPort01, GRTPort08_09, GRTPort12_13, GRTPort30_31]> {
+  let Latency = 4;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup63], (instregex "^PUSH(F|G)S(16|64)$")>;
+
+def GRTWriteResGroup64 : SchedWriteRes<[GRTPort01]> {
+  let Latency = 7;
+}
+def : InstRW<[GRTWriteResGroup64], (instregex "^RC(L|R)(8|16)m(1|i)$")>;
+
+def GRTWriteResGroup65 : SchedWriteRes<[GRTPort01]> {
+  let Latency = 19;
+}
+def : InstRW<[GRTWriteResGroup65], (instregex "^RC(L|R)(8|16)mCL$")>;
+
+def GRTWriteResGroup66 : SchedWriteRes<[GRTPort01]> {
+  let Latency = 6;
+}
+def : InstRW<[GRTWriteResGroup66], (instregex "^RC(L|R)(32|64)m(1|i)$")>;
+
+def GRTWriteResGroup67 : SchedWriteRes<[GRTPort01]> {
+  let Latency = 18;
+}
+def : InstRW<[GRTWriteResGroup67], (instregex "^RC(L|R)(32|64)mCL$")>;
+
+def GRTWriteResGroup68 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 1131;
+}
+def : InstRW<[GRTWriteResGroup68], (instrs RDRAND16r)>;
+
+def GRTWriteResGroup69 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 1129;
+}
+def : InstRW<[GRTWriteResGroup69], (instrs RDSEED16r)>;
+
+def GRTWriteResGroup70 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 38;
+  let NumMicroOps = 14;
+}
+def : InstRW<[GRTWriteResGroup70], (instrs SGDT64m)>;
+
+def GRTWriteResGroup71 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 16;
+}
+def : InstRW<[GRTWriteResGroup71], (instrs SHLD16mri8)>;
+
+def GRTWriteResGroup72 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 6;
+}
+def : InstRW<[GRTWriteResGroup72], (instrs SHLD16rri8)>;
+
+def GRTWriteResGroup73 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let ResourceCycles = [3];
+  let Latency = 3;
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup73], (instregex "^SH(L|R)D32rrCL$")>;
+
+def GRTWriteResGroup74 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 14;
+}
+def : InstRW<[GRTWriteResGroup74], (instregex "^SHLD64mr(CL|i8)$")>;
+def : InstRW<[GRTWriteResGroup74], (instrs SHRD16mrCL)>;
+
+def GRTWriteResGroup75 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 7;
+}
+def : InstRW<[GRTWriteResGroup75], (instregex "^SH(L|R)D64rrCL$")>;
+
+def GRTWriteResGroup76 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 4;
+}
+def : InstRW<[GRTWriteResGroup76], (instregex "^SH(L|R)D64rri8$")>;
+
+def GRTWriteResGroup77 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 15;
+}
+def : InstRW<[GRTWriteResGroup77], (instregex "^SHRD(16|64)mri8$")>;
+
+def GRTWriteResGroup78 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 5;
+}
+def : InstRW<[GRTWriteResGroup78], (instrs SHRD16rri8)>;
+
+def GRTWriteResGroup79 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 38;
+  let NumMicroOps = 13;
+}
+def : InstRW<[GRTWriteResGroup79], (instrs SIDT64m)>;
+
+def GRTWriteResGroup80 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 37;
+  let NumMicroOps = 11;
+}
+def : InstRW<[GRTWriteResGroup80], (instrs SLDT16m)>;
+
+def GRTWriteResGroup81 : SchedWriteRes<[GRTPortInvalid]> {
+  let NumMicroOps = 11;
+}
+def : InstRW<[GRTWriteResGroup81], (instrs SLDT16r)>;
+
+def GRTWriteResGroup82 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 12;
+  let NumMicroOps = 8;
+}
+def : InstRW<[GRTWriteResGroup82], (instrs SMSW16m)>;
+
+def GRTWriteResGroup83 : SchedWriteRes<[GRTPortInvalid]> {
+  let NumMicroOps = 8;
+}
+def : InstRW<[GRTWriteResGroup83], (instrs SMSW16r)>;
+
+def GRTWriteResGroup84 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 3;
+  let NumMicroOps = 10;
+}
+def : InstRW<[GRTWriteResGroup84], (instrs STR16r)>;
+
+def GRTWriteResGroup85 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 36;
+  let NumMicroOps = 10;
+}
+def : InstRW<[GRTWriteResGroup85], (instrs STRm)>;
+
+def GRTWriteResGroup86 : SchedWriteRes<[GRTPort12_13, GRTPort20, GRTPort28_29]> {
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup86], (instregex "^ST_F(P?)(32|64)m$")>;
+
+def GRTWriteResGroup87 : SchedWriteRes<[GRTPort01]> {
+  let Latency = GRTModel.MaxLatency;
+}
+def : InstRW<[GRTWriteResGroup87], (instrs SWAPGS)>;
+
+def GRTWriteResGroup88 : SchedWriteRes<[GRTPort10_11, GRTPort20_21]> {
+  let ResourceCycles = [2, 2];
+  let Latency = 8;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup88, ReadAfterVecXLd], (instregex "^VAES(DE|EN)C((LAST)?)Yrm$")>;
+
+def GRTWriteResGroup89 : SchedWriteRes<[GRTPort20_21]> {
+  let ResourceCycles = [2];
+  let Latency = 3;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup89], (instregex "^VAES(DE|EN)C((LAST)?)Yrr$")>;
+
+def GRTWriteResGroup90 : SchedWriteRes<[GRTPort10_11, GRTPort20_21, GRTPort20_21_22]> {
+  let ResourceCycles = [1, 1, 2];
+  let Latency = 9;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup90, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
+
+def GRTWriteResGroup91 : SchedWriteRes<[GRTPort20_21, GRTPort20_21_22]> {
+  let ResourceCycles = [1, 3];
+  let Latency = 6;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup91], (instregex "^VBLENDVP(D|S)rr$")>;
+
+def GRTWriteResGroup92 : SchedWriteRes<[GRTPort10_11, GRTPort20_21_22]> {
+  let ResourceCycles = [2, 2];
+  let Latency = 6;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup92], (instregex "^VBROADCAST(F|I)128$",
+                                              "^VBROADCASTS(D|S)Yrm$",
+                                              "^VPBROADCAST(B|D|Q|W)Yrm$")>;
+
+def GRTWriteResGroup93 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let Latency = 4;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup93], (instregex "^VCVT(T?)SD2SI((64)?)rm$",
+                                              "^VCVTSD2SI((64)?)rm_Int$")>;
+def : InstRW<[GRTWriteResGroup93, ReadAfterVecLd], (instregex "^VCVTS(D|I)2SSrm((_Int)?)$",
+                                                              "^VCVTS(I|S)2SDrm((_Int)?)$",
+                                                              "^VCVTSI642S(D|S)rm((_Int)?)$")>;
+
+def GRTWriteResGroup94 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 58;
+  let NumMicroOps = 12;
+}
+def : InstRW<[GRTWriteResGroup94], (instregex "^VER(R|W)m$")>;
+
+def GRTWriteResGroup95 : SchedWriteRes<[GRTPort30_31]> {
+  let Latency = 51;
+}
+def : InstRW<[GRTWriteResGroup95], (instregex "^VER(R|W)r$")>;
+
+def GRTWriteResGroup96 : SchedWriteRes<[GRTPort12_13, GRTPort20, GRTPort28_29]> {
+  let ResourceCycles = [2, 2, 2];
+  let NumMicroOps = 6;
+}
+def : InstRW<[GRTWriteResGroup96], (instregex "^VEXTRACT(F|I)128mr$")>;
+
+def GRTWriteResGroup97 : SchedWriteRes<[GRTPort20]> {
+  let ResourceCycles = [2];
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup97], (instregex "^VEXTRACT(F|I)128rr$")>;
+
+def GRTWriteResGroup98 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let ResourceCycles = [2];
+  let Latency = 28;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup98, WriteVecMaskedGatherWriteback], (instrs VGATHERDPDYrm)>;
+
+def GRTWriteResGroup99 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 22;
+}
+def : InstRW<[GRTWriteResGroup99, WriteVecMaskedGatherWriteback], (instregex "^VGATHERDP(D|S)rm$",
+                                                                             "^VPGATHERD(D|Q)rm$")>;
+
+def GRTWriteResGroup100 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let ResourceCycles = [2];
+  let Latency = 33;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup100, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm)>;
+
+def GRTWriteResGroup101 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let ResourceCycles = [2];
+  let Latency = 23;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup101, WriteVecMaskedGatherWriteback], (instrs VGATHERQPDYrm,
+                                                                           VPGATHERQQYrm)>;
+
+def GRTWriteResGroup102 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 17;
+}
+def : InstRW<[GRTWriteResGroup102, WriteVecMaskedGatherWriteback], (instrs VGATHERQPDrm,
+                                                                           VPGATHERQQrm)>;
+
+def GRTWriteResGroup103 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 24;
+}
+def : InstRW<[GRTWriteResGroup103, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
+                                                                           VPGATHERQDYrm)>;
+
+def GRTWriteResGroup104 : SchedWriteRes<[GRTPort10_11, GRTPort20_21]> {
+  let ResourceCycles = [2, 2];
+  let Latency = 9;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup104, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBYrmi$")>;
+
+def GRTWriteResGroup105 : SchedWriteRes<[GRTPort20_21]> {
+  let ResourceCycles = [2];
+  let Latency = 4;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup105], (instregex "^VGF2P8AFFINE((INV)?)QBYrri$")>;
+
+def GRTWriteResGroup106 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let ResourceCycles = [2, 2];
+  let Latency = 9;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup106], (instregex "^VPDP(BU|WS)SD(S?)Yrm$")>;
+def : InstRW<[GRTWriteResGroup106, ReadAfterVecYLd], (instrs VGF2P8MULBYrm,
+                                                             VPCMPGTQYrm)>;
+def : InstRW<[GRTWriteResGroup106, ReadAfterVecXLd], (instrs VPCLMULQDQYrm)>;
+
+def GRTWriteResGroup107 : SchedWriteRes<[GRTPort20]> {
+  let ResourceCycles = [2];
+  let Latency = 4;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup107], (instregex "^VPDP(BU|WS)SD(S?)Yrr$")>;
+def : InstRW<[GRTWriteResGroup107], (instrs VGF2P8MULBYrr,
+                                            VPCLMULQDQYrr,
+                                            VPCMPGTQYrr)>;
+
+def GRTWriteResGroup108 : SchedWriteRes<[GRTPort12_13, GRTPort20, GRTPort28_29, GRTPort30_31]> {
+  let ResourceCycles = [2, 2, 2, 1];
+  let Latency = 3;
+  let NumMicroOps = 7;
+}
+def : InstRW<[GRTWriteResGroup108], (instrs VMASKMOVDQU64)>;
+
+def GRTWriteResGroup109 : SchedWriteRes<[GRTPort20]> {
+  let ResourceCycles = [2];
+  let Latency = 5;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup109], (instregex "^VMOVMSKP(D|S)Yrr$")>;
+
+def GRTWriteResGroup110 : SchedWriteRes<[GRTPort20, GRTPort20_21_22]> {
+  let ResourceCycles = [1, 2];
+  let Latency = 6;
+  let NumMicroOps = 3;
+}
+def : InstRW<[GRTWriteResGroup110], (instrs VMPSADBWrri)>;
+
+def GRTWriteResGroup111 : SchedWriteRes<[GRTPort10_11, GRTPort20_21, GRTPort20_21_22]> {
+  let ResourceCycles = [1, 1, 2];
+  let Latency = 10;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup111, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
+
+def GRTWriteResGroup112 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let ResourceCycles = [2, 2];
+  let Latency = 6;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup112, ReadAfterVecYLd], (instregex "^VPERM2(F|I)128rm$")>;
+
+def GRTWriteResGroup113 : SchedWriteRes<[GRTPort20]> {
+  let ResourceCycles = [2];
+  let Latency = 6;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup113], (instregex "^VPERM2(F|I)128rr$")>;
+
+def GRTWriteResGroup114 : SchedWriteRes<[GRTPort10_11, GRTPort20]> {
+  let ResourceCycles = [2, 2];
+  let Latency = 18;
+  let NumMicroOps = 4;
+}
+def : InstRW<[GRTWriteResGroup114, ReadAfterVecYLd], (instregex "^VPERM(Q|PD)Ymi$")>;
+
+def GRTWriteResGroup115 : SchedWriteRes<[GRTPort20]> {
+  let ResourceCycles = [2];
+  let Latency = 8;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup115], (instregex "^VPERM(Q|PD)Yri$")>;
+
+def GRTWriteResGroup116 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let ResourceCycles = [2];
+  let Latency = 32;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup116, WriteVecMaskedGatherWriteback], (instrs VPGATHERDDYrm)>;
+
+def GRTWriteResGroup117 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let ResourceCycles = [2];
+  let Latency = 27;
+  let NumMicroOps = 2;
+}
+def : InstRW<[GRTWriteResGroup117, WriteVecMaskedGatherWriteback], (instrs VPGATHERDQYrm)>;
+
+def GRTWriteResGroup118 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort10_11, GRTPort20_21_22]> {
+  let ResourceCycles = [2, 2, 6];
+  let Latency = 8;
+  let NumMicroOps = 10;
+}
+def : InstRW<[GRTWriteResGroup118, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)DYrm$")>;
+
+def GRTWriteResGroup119 : SchedWriteRes<[GRTPort00_01_02_03, GRTPort20_21_22]> {
+  let ResourceCycles = [2, 6];
+  let Latency = 4;
+  let NumMicroOps = 8;
+}
+def : InstRW<[GRTWriteResGroup119], (instregex "^VPH(ADD|SUB)DYrr$")>;
+
+def GRTWriteResGroup120 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = 6;
+  let NumMicroOps = 5;
+}
+def : InstRW<[GRTWriteResGroup120], (instregex "^X(ADD|CHG)(8|16|32|64)rm$")>;
+
+def GRTWriteResGroup121 : SchedWriteRes<[GRTPort00_01_02_03]> {
+  let Latency = 40;
+}
+def : InstRW<[GRTWriteResGroup121], (instrs XGETBV)>;
+
+def GRTWriteResGroup122 : SchedWriteRes<[GRTPortInvalid]> {
+  let Latency = GRTModel.MaxLatency;
+  let NumMicroOps = 277;
+}
+def : InstRW<[GRTWriteResGroup122], (instregex "^XSAVES((64)?)$")>;
+
+}