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HaohaiWen (Haohai, Wen)
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User Since
Jul 21 2021, 11:13 PM (80 w, 5 d)

Recent Activity

Mon, Jan 16

HaohaiWen added inline comments to D141485: [X86] Add schedule module for SapphireRapids.
Mon, Jan 16, 11:20 PM · Restricted Project, Restricted Project

Fri, Jan 13

HaohaiWen updated the diff for D141485: [X86] Add schedule module for SapphireRapids.

Use SapphireRapidsModel for graniterapids and emeraldrapids

Fri, Jan 13, 12:22 AM · Restricted Project, Restricted Project

Wed, Jan 11

HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Support sapphirerapids target

Wed, Jan 11, 5:17 PM · Restricted Project, Restricted Project
HaohaiWen added a comment to D141485: [X86] Add schedule module for SapphireRapids.

Instruction's scheduling info in this model comes from many sources.
Priority of source is (dsc order)

  1. 4th Generation Intel® Xeon® Scalable Processor Family (based on Sapphire Rapids Architecture) Instruction Throughput and Latency in https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
  2. Alderlake-P data from uops.info
  3. Current SkylakeServerModel.
Wed, Jan 11, 5:46 AM · Restricted Project, Restricted Project
HaohaiWen added reviewers for D141485: [X86] Add schedule module for SapphireRapids: pengfei, wxiao3, LuoYuanke, gpei, RKSimon, e-kud.
Wed, Jan 11, 5:42 AM · Restricted Project, Restricted Project
HaohaiWen requested review of D141485: [X86] Add schedule module for SapphireRapids.
Wed, Jan 11, 5:36 AM · Restricted Project, Restricted Project
HaohaiWen committed rG8ce5579d7f18: [X86] Add scheduling info of CodeGenOnly but encodable instructions for… (authored by HaohaiWen).
[X86] Add scheduling info of CodeGenOnly but encodable instructions for…
Wed, Jan 11, 2:45 AM · Restricted Project, Restricted Project
HaohaiWen closed D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model.
Wed, Jan 11, 2:44 AM · Restricted Project, Restricted Project

Jan 4 2023

HaohaiWen planned changes to D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
Jan 4 2023, 10:00 PM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Don't match CodeGenOnly instructions with lock prefix. Add default LoadUOps argument.

Jan 4 2023, 9:57 PM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model.

Ignore CodeGenOnly instructions with lock prefix

Jan 4 2023, 9:51 PM · Restricted Project, Restricted Project

Dec 27 2022

HaohaiWen added a comment to D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model.

Any comments?

Dec 27 2022, 6:42 PM · Restricted Project, Restricted Project

Dec 8 2022

HaohaiWen added a comment to D139685: [DAGCombine]Expand usage of CreateBuildVecShuffle to make full use of vector ops.

Now, when llc encounters the case that contains a lot of extract_vector_elt and a BUILD_VECTOR, it will replace these to vector_shuffle to decrease the size of code, the actions are done in createBuildVecShuffle in DAGCombiner.cpp, but now the code cannot handle the case that the size of source vector reg is more than twice the dest size.

Dec 8 2022, 5:52 PM · Restricted Project, Restricted Project

Dec 5 2022

HaohaiWen added inline comments to D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model.
Dec 5 2022, 5:09 AM · Restricted Project, Restricted Project
HaohaiWen updated subscribers of D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model.
Dec 5 2022, 3:39 AM · Restricted Project, Restricted Project
HaohaiWen added inline comments to D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model.
Dec 5 2022, 2:02 AM · Restricted Project, Restricted Project
HaohaiWen added reviewers for D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model: pengfei, RKSimon, LuoYuanke.
Dec 5 2022, 1:56 AM · Restricted Project, Restricted Project
HaohaiWen requested review of D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model.
Dec 5 2022, 1:52 AM · Restricted Project, Restricted Project
HaohaiWen planned changes to D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
Dec 5 2022, 12:59 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Don't match CodeGenOnly opcodes by default

Dec 5 2022, 12:59 AM · Restricted Project, Restricted Project

Dec 2 2022

HaohaiWen planned changes to D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
Dec 2 2022, 12:24 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Generate asm string for CodeGenOnly but encodable instructions

Dec 2 2022, 12:24 AM · Restricted Project, Restricted Project

Nov 25 2022

HaohaiWen planned changes to D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
Nov 25 2022, 12:58 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Fix typo

Nov 25 2022, 12:57 AM · Restricted Project, Restricted Project

Nov 24 2022

HaohaiWen abandoned D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions.
Nov 24 2022, 11:19 PM · Restricted Project, Restricted Project
HaohaiWen added a comment to D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions.

I don’t know anything about xed. What does it require?

AFAIK, Input to it is normally encoding or asm string. That's why I need to enumerate asm string and encode it for each llvm opcodes.

Nov 24 2022, 8:53 PM · Restricted Project, Restricted Project
HaohaiWen added a comment to D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions.

Is it not possible to use the encoding information in TSFlags rather than going through the assembly parser? Your patches for schedtool seem very coupled to the names of operand classes and other things. It looks like it will require updates often.

The asm enumeration code and asm matcher patch as well as xed patch are used to build map between llvm opcode <-> Xed info <-> uops.info data / other scheduling info data source. Do you have any suggestion to build this map?
IsaSet in Xed info can also be used to identify whether a llvm opcode is supported by specific target. LLVM predicates can't determine that precisely.

Nov 24 2022, 8:34 PM · Restricted Project, Restricted Project
HaohaiWen added a comment to D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions.

Can we ignore those with isCodeGenOnly. I think they are just duplications of the non codegen only ones from the perspective of encoding.

Of course we can ignore it in almost all cases because they'll never be generated to asm printer.
However we should describe them correctly in schedule model. In fact, current schedtool D130897 only emit scheduling info for not CodeGenOnly instruction. That means scheduling info for CodeGenOnly instructions like CVTSD2SI64rm may be not correct, although it should be same with CVTSD2SI64rm_Int.
I'm working on fixing that, this requires correct mode predicates for CodeGenOnly and encodable instructions.

Nov 24 2022, 7:58 PM · Restricted Project, Restricted Project
HaohaiWen added a comment to D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions.

How does adding In64BitMode avoid this error? This error occurs when AH/BH/CH/DH are passed to an instruction that uses a REX prefix. Are you using In64BitMode to avoid passing AH/BH/CH/DH registers?

In fact, the issue is, I relied on predicates to auto gen asm. Let's take CVTSD2SI64rm as an example.
Since it have no predicates, I made assumption its encodable in all modes and then try to gen 16,32,64 bit asm string (by adding {.code16 .code32 . code64) enumeration and encode it with llvm-mc. Then fed the encoding into llvm-mc to decode in order to find all matchable llvm opcodes.
That's how I found this predicates error.

Nov 24 2022, 5:30 PM · Restricted Project, Restricted Project
HaohaiWen added a comment to D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions.

Isn't X86::CVTSD2SI64rm the CodeGenOnly instruction?

Nov 24 2022, 4:52 PM · Restricted Project, Restricted Project
HaohaiWen planned changes to D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
Nov 24 2022, 5:05 AM · Restricted Project, Restricted Project
HaohaiWen added a comment to D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions.

Are you seeing a functional issue that this fixes?

Nov 24 2022, 12:46 AM · Restricted Project, Restricted Project
HaohaiWen added a reviewer for D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions: skan.
Nov 24 2022, 12:03 AM · Restricted Project, Restricted Project
HaohaiWen requested review of D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions.
Nov 24 2022, 12:02 AM · Restricted Project, Restricted Project

Nov 23 2022

HaohaiWen committed rG1215e86a0e47: [CostModel][X86] Fix permute latency cost (authored by HaohaiWen).
[CostModel][X86] Fix permute latency cost
Nov 23 2022, 3:18 AM · Restricted Project, Restricted Project
HaohaiWen closed D138427: [CostModel][X86] Fix permute latency cost.
Nov 23 2022, 3:17 AM · Restricted Project, Restricted Project
HaohaiWen added a comment to D138427: [CostModel][X86] Fix permute latency cost.

Have you confirmed that this passes the whole of check-llvm? Sometime these cost changes have effects in transforms/codegen you don't expect

Yes, all passed.

Nov 23 2022, 2:28 AM · Restricted Project, Restricted Project
HaohaiWen added inline comments to D138359: [TableGen] CheckSchedClassTables - check for unnecessary scheduler overrides.
Nov 23 2022, 1:38 AM · Restricted Project, Restricted Project
HaohaiWen added inline comments to D138359: [TableGen] CheckSchedClassTables - check for unnecessary scheduler overrides.
Nov 23 2022, 1:12 AM · Restricted Project, Restricted Project

Nov 22 2022

HaohaiWen updated the diff for D138427: [CostModel][X86] Fix permute latency cost.

Rebase upon D38485

Nov 22 2022, 7:28 PM · Restricted Project, Restricted Project
HaohaiWen committed rG2dfe76e98987: [CostModel][X86] Add CostKinds test coverage for shufflevector instruction (authored by HaohaiWen).
[CostModel][X86] Add CostKinds test coverage for shufflevector instruction
Nov 22 2022, 6:31 PM · Restricted Project, Restricted Project
HaohaiWen closed D138485: [CostModel][X86] Add CostKinds test coverage for shufflevector instruction.
Nov 22 2022, 6:31 PM · Restricted Project, Restricted Project
HaohaiWen added reviewers for D138485: [CostModel][X86] Add CostKinds test coverage for shufflevector instruction: RKSimon, pengfei, LuoYuanke.
Nov 22 2022, 6:27 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D138485: [CostModel][X86] Add CostKinds test coverage for shufflevector instruction.

Add cost-kind and update costs for slm/goldencove/btver2

Nov 22 2022, 6:11 AM · Restricted Project, Restricted Project
HaohaiWen added a comment to D138485: [CostModel][X86] Add CostKinds test coverage for shufflevector instruction.

Please see diffs between those versions to see what changed.
Patch1: Just copy throughput cost files.
Patch2: Add cost-kind options (some cost-kinds are added in patch4)
Patch3: Update cost value. (some costs are added in patch4)

Nov 22 2022, 4:04 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D138485: [CostModel][X86] Add CostKinds test coverage for shufflevector instruction.

Update cost value

Nov 22 2022, 4:01 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D138485: [CostModel][X86] Add CostKinds test coverage for shufflevector instruction.

Add cost-kind options

Nov 22 2022, 3:30 AM · Restricted Project, Restricted Project
HaohaiWen requested review of D138485: [CostModel][X86] Add CostKinds test coverage for shufflevector instruction.
Nov 22 2022, 3:28 AM · Restricted Project, Restricted Project

Nov 21 2022

HaohaiWen added a comment to D138427: [CostModel][X86] Fix permute latency cost.

No test affected, or lacking test for them?

Looks like no permute latency test.

Nov 21 2022, 5:46 PM · Restricted Project, Restricted Project
HaohaiWen updated the summary of D138427: [CostModel][X86] Fix permute latency cost.
Nov 21 2022, 5:19 PM · Restricted Project, Restricted Project
HaohaiWen requested review of D138427: [CostModel][X86] Fix permute latency cost.
Nov 21 2022, 6:14 AM · Restricted Project, Restricted Project

Nov 11 2022

HaohaiWen added a comment to D137841: [X86] Reduce unnecessary instregex for AlderlakeP schedule model.

Do you have any suggestions for scheduler classes that we could add/change to help reduce the number of overrides?

Nov 11 2022, 9:05 PM · Restricted Project, Restricted Project
HaohaiWen committed rG8b3f7833e0d2: [X86] Reduce unnecessary instregex for AlderlakeP schedule model (authored by HaohaiWen).
[X86] Reduce unnecessary instregex for AlderlakeP schedule model
Nov 11 2022, 8:32 PM · Restricted Project, Restricted Project
HaohaiWen closed D137841: [X86] Reduce unnecessary instregex for AlderlakeP schedule model.
Nov 11 2022, 8:32 PM · Restricted Project, Restricted Project
HaohaiWen added a comment to D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
  let ResourceCycles = [2, 2, 1, 2];
  let Latency = 6;
  let NumMicroOps = 7;
}
def : InstRW<[ADLPWriteResGroup222], (instregex "^SHA1MSG2rr$")>;

That could just as well be (instrs SHA1MSG2rr)

Nov 11 2022, 7:57 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Delete misadded files

Nov 11 2022, 7:55 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Replace simple instregex with instrs to boost tblgen match speed

Nov 11 2022, 7:52 AM · Restricted Project, Restricted Project
HaohaiWen added a comment to D137841: [X86] Reduce unnecessary instregex for AlderlakeP schedule model.

All I'm actually requiring is that the instregex that end in "_Int$" are replaced with (_Int)?$

Nov 11 2022, 7:46 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D137841: [X86] Reduce unnecessary instregex for AlderlakeP schedule model.

Replace simple instregex with instrs

Nov 11 2022, 7:32 AM · Restricted Project, Restricted Project
HaohaiWen added a comment to D137841: [X86] Reduce unnecessary instregex for AlderlakeP schedule model.

@RKSimon , you can compare diff of patch1 and patch2 to see what changed for instregex.

Nov 11 2022, 7:14 AM · Restricted Project, Restricted Project
HaohaiWen added reviewers for D137841: [X86] Reduce unnecessary instregex for AlderlakeP schedule model: LuoYuanke, RKSimon.
Nov 11 2022, 7:13 AM · Restricted Project, Restricted Project
HaohaiWen requested review of D137841: [X86] Reduce unnecessary instregex for AlderlakeP schedule model.
Nov 11 2022, 7:09 AM · Restricted Project, Restricted Project

Nov 8 2022

HaohaiWen committed rGb17b25dde069: [X86] Add In64BitMode requirement for MMXRI (authored by HaohaiWen).
[X86] Add In64BitMode requirement for MMXRI
Nov 8 2022, 10:09 PM · Restricted Project, Restricted Project
HaohaiWen closed D137686: [X86] Add In64BitMode requirement for MMXRI.
Nov 8 2022, 10:08 PM · Restricted Project, Restricted Project
HaohaiWen added a reviewer for D137686: [X86] Add In64BitMode requirement for MMXRI: skan.
Nov 8 2022, 6:37 PM · Restricted Project, Restricted Project
HaohaiWen requested review of D137686: [X86] Add In64BitMode requirement for MMXRI.
Nov 8 2022, 6:36 PM · Restricted Project, Restricted Project

Nov 7 2022

HaohaiWen committed rG1c355352c730: [X86] Add In64BitMode predicates for LOCK_INC64m, LOCK_DEC64m (authored by HaohaiWen).
[X86] Add In64BitMode predicates for LOCK_INC64m, LOCK_DEC64m
Nov 7 2022, 11:17 PM · Restricted Project, Restricted Project
HaohaiWen closed D137608: [X86] Add In64BitMode predicates for LOCK_INC64m, LOCK_DEC64m.
Nov 7 2022, 11:17 PM · Restricted Project, Restricted Project
HaohaiWen added reviewers for D137608: [X86] Add In64BitMode predicates for LOCK_INC64m, LOCK_DEC64m: pengfei, LuoYuanke.
Nov 7 2022, 9:49 PM · Restricted Project, Restricted Project
HaohaiWen requested review of D137608: [X86] Add In64BitMode predicates for LOCK_INC64m, LOCK_DEC64m.
Nov 7 2022, 9:48 PM · Restricted Project, Restricted Project

Nov 3 2022

HaohaiWen committed rGe419620fc2f5: [CodeGenPrep] Change ValueToSExts from DeseMap to MapVector (authored by HaohaiWen).
[CodeGenPrep] Change ValueToSExts from DeseMap to MapVector
Nov 3 2022, 8:16 PM · Restricted Project, Restricted Project
HaohaiWen closed D137234: [CodeGenPrep] Change ValueToSExts from DeseMap to MapVector.
Nov 3 2022, 8:15 PM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Remove old alderlake.td template file

Nov 3 2022, 12:41 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Rebase patch

Nov 3 2022, 12:39 AM · Restricted Project, Restricted Project

Nov 2 2022

HaohaiWen added reviewers for D137234: [CodeGenPrep] Change ValueToSExts from DeseMap to MapVector: pengfei, LuoYuanke, wxiao3.
Nov 2 2022, 1:44 AM · Restricted Project, Restricted Project
HaohaiWen requested review of D137234: [CodeGenPrep] Change ValueToSExts from DeseMap to MapVector.
Nov 2 2022, 1:43 AM · Restricted Project, Restricted Project

Oct 26 2022

HaohaiWen committed rG21f23a37c6f1: [SelectionDAG] Clamp stack alignment for memset, memmove (authored by HaohaiWen).
[SelectionDAG] Clamp stack alignment for memset, memmove
Oct 26 2022, 1:46 AM · Restricted Project, Restricted Project
HaohaiWen closed D136456: [SelectionDAG] Clamp stack alignment for memset, memmove.
Oct 26 2022, 1:45 AM · Restricted Project, Restricted Project

Oct 24 2022

HaohaiWen added inline comments to D136456: [SelectionDAG] Clamp stack alignment for memset, memmove.
Oct 24 2022, 12:00 AM · Restricted Project, Restricted Project

Oct 23 2022

HaohaiWen updated the diff for D136456: [SelectionDAG] Clamp stack alignment for memset, memmove.

Delete mistakenly added files

Oct 23 2022, 7:02 PM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D136456: [SelectionDAG] Clamp stack alignment for memset, memmove.

Update comments

Oct 23 2022, 6:59 PM · Restricted Project, Restricted Project

Oct 21 2022

HaohaiWen added inline comments to D136456: [SelectionDAG] Clamp stack alignment for memset, memmove.
Oct 21 2022, 11:38 PM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D136456: [SelectionDAG] Clamp stack alignment for memset, memmove.

Fix amdgpu test

Oct 21 2022, 11:32 PM · Restricted Project, Restricted Project
HaohaiWen added reviewers for D136456: [SelectionDAG] Clamp stack alignment for memset, memmove: pengfei, wxiao3, LuoYuanke, RKSimon.
Oct 21 2022, 8:26 AM · Restricted Project, Restricted Project
HaohaiWen requested review of D136456: [SelectionDAG] Clamp stack alignment for memset, memmove.
Oct 21 2022, 8:24 AM · Restricted Project, Restricted Project

Sep 13 2022

HaohaiWen added inline comments to rGa931dbfbd307: [CostModel][X86] Merge AVX512BW vXi8/vXi16 shifts into default AVX512BW cost….
Sep 13 2022, 11:19 PM · Restricted Project, Restricted Project

Sep 4 2022

HaohaiWen planned changes to D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
Sep 4 2022, 5:55 PM · Restricted Project, Restricted Project

Aug 18 2022

HaohaiWen added a comment to D130959: [X86] Add schedule module for Alderlake-P.

Thank you @RKSimon

Aug 18 2022, 1:41 AM · Restricted Project, Restricted Project
HaohaiWen committed rGf4410d471f1f: [X86] Add schedule module for Alderlake-P (authored by HaohaiWen).
[X86] Add schedule module for Alderlake-P
Aug 18 2022, 1:40 AM · Restricted Project, Restricted Project
HaohaiWen closed D130959: [X86] Add schedule module for Alderlake-P.
Aug 18 2022, 1:40 AM · Restricted Project, Restricted Project

Aug 3 2022

HaohaiWen updated the summary of D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
Aug 3 2022, 3:08 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.

Rename alderlake to alderlake-p

Aug 3 2022, 3:07 AM · Restricted Project, Restricted Project
HaohaiWen retitled D130959: [X86] Add schedule module for Alderlake-P from [X86] Add schedule module for Alderlake target to [X86] Add schedule module for Alderlake-P.
Aug 3 2022, 2:50 AM · Restricted Project, Restricted Project
HaohaiWen updated the diff for D130959: [X86] Add schedule module for Alderlake-P.

Rename alderlake model to alderlake-p model

Aug 3 2022, 2:48 AM · Restricted Project, Restricted Project

Aug 2 2022

HaohaiWen added a comment to D130959: [X86] Add schedule module for Alderlake-P.

do you have enough public info to write the model manually and then exegesis can confirm it at least matches total uops, throughput and latency counts.

For total uops, latency, we can get them from uops.info. We can set them in schedule model automatically.
For throughput, llvm calculate (see MCSchedModel::getReciprocalThroughput) them based on port description (resource, resource_cycles) instead of defining them directly like latency. We need to infer possible ports based on given throughput.

Aug 2 2022, 6:13 AM · Restricted Project, Restricted Project
HaohaiWen added a comment to D130959: [X86] Add schedule module for Alderlake-P.

llvm-exegesis can give some reasonably latency / throughput numbers based off uops counters alone and the latest AoM shows the Gracemont microarch for actual ports - we had to do something similar for the Atom and SLM models

Aug 2 2022, 3:58 AM · Restricted Project, Restricted Project
HaohaiWen added a comment to D130959: [X86] Add schedule module for Alderlake-P.

Do you intend to add a alderlake-e model as well?

I'd like to add adl-e model. The problem is we have no instruction port information for gracemont since it has no events like uops.dispatch.port0. See https://uops.info/table.html

Aug 2 2022, 3:38 AM · Restricted Project, Restricted Project
HaohaiWen added inline comments to D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically.
Aug 2 2022, 3:27 AM · Restricted Project, Restricted Project

Aug 1 2022

HaohaiWen retitled D130959: [X86] Add schedule module for Alderlake-P from Add schedule module for Alderlake target to [X86] Add schedule module for Alderlake target.
Aug 1 2022, 8:34 PM · Restricted Project, Restricted Project
HaohaiWen requested review of D130959: [X86] Add schedule module for Alderlake-P.
Aug 1 2022, 8:23 PM · Restricted Project, Restricted Project