[AArch64][SelectionDAG] Perfer CMN for (0 - Y) == Y

[Allen]

Summary

cmn a, b means a - (-b) - which under two's complement arithmetic
is exactly equivalent to a + b. so Y == -Y is just match the cmn Y, Y

Fix https://github.com/llvm/llvm-project/issues/60818

[Allen]

update comment

[spatel]

We should probably view this as a missed canonicalization in IR first:
https://alive2.llvm.org/ce/z/D2Aph4 (that should also work with eq predicates)

The IR with and removes a use of the input variable, so it's better for analysis.
If the codegen here is still considered better, then add a transform from the new canonical form to the cmn form.

[Allen]

Yes, Agree your idea, thanks @spatel. I also realize that the cmn directive may not exist on all backends? so this is not appropriate.

I try to add a patten match in performSETCCCombine , but then it go Into an infinite, so I'm trying to add a codegen pattern for this issue.

+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20436,6 +20436,20 @@ static SDValue performSETCCCombine(SDNode *N,
     }
   }
 
+  // setcc (shl x, 1), 0, ne ==> setcc (sub 0, x), x, ne for CMN
+  if (Cond == ISD::SETNE && isNullConstant(RHS) &&
+      LHS->getOpcode() == ISD::SHL && isa<ConstantSDNode>(LHS->getOperand(1)) &&
+      LHS->getConstantOperandVal(1) == 1 && LHS->hasOneUse()) {
+    EVT TstVT = LHS->getValueType(0);
+    if (TstVT.isScalarInteger() && TstVT.getFixedSizeInBits() <= 64) {
+      // this pattern will get better opt in emitComparison
+      SDValue ValX = LHS->getOperand(0);
+      SDValue TST = DAG.getNode(ISD::SUB, DL, TstVT, DAG.getConstant(0, DL, TstVT),
+                                ValX);
+      return DAG.getNode(ISD::SETCC, DL, VT, TST, ValX, N->getOperand(2));
+    }
+  }

[Allen]

Agree with @spatel , should be redesign in IR level

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

   // (X ^ Y) == Y --> X == 0
   if (BOpcode == ISD::ADD || BOpcode == ISD::XOR)
     return DAG.getSetCC(DL, VT, X, DAG.getConstant(0, DL, OpVT), Cond);
 
   // The shift would not be valid if the operands are boolean (i1).
   if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1)
     return SDValue();
 
+  // The shift would be disable as we prefer CMN for (0 - Y) == Y
+  if (ConstantSDNode *CTVal = isConstOrConstSplat(X))
+    if (CTVal->isZero())
+      return SDValue();
+
   // (X - Y) == Y --> X == Y << 1
   EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(),
                                  !DCI.isBeforeLegalize());
   SDValue One = DAG.getConstant(1, DL, ShiftVT);
   SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
   if (!DCI.isCalledByLegalizer())
     DCI.AddToWorklist(YShl1.getNode());
   return DAG.getSetCC(DL, VT, X, YShl1, Cond);

llvm/test/CodeGen/AArch64/cmp-to-cmn.ll

 ; CHECK-NEXT: ret
 entry:
   %conv = zext i8 %a to i32
   %conv1 = zext i8 %b to i32
   %add = sub nsw i32 0, %conv1
   %cmp = icmp ne i32 %conv, %add
   ret i1 %cmp
 }
+
+define i1 @PR60818(i32 %a) {
+; CHECK-LABEL: PR60818:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmn  w0, w0
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i32 0, %a
+  %cmp = icmp ne i32 %sub, %a
+  ret i1 %cmp
+}