[AMDGPU][MC] Enable modifiers on V_MOV_B32

[danilomilosevic]

https://github.com/llvm/llvm-project/issues/49692

[Joe_Nash]

Thanks for taking a look at this issue.

First, I am surprised there are not many more crashes without further modifications to codegen passes to account for the changed number of operands. For example
SIFoldOperand.cpp:693
The number of operands has changed, so I would expect removing the operands to break quite badly.

Actually, I think due to the way the operand lists for _e32 instructions are constructed, the modifiers are not taking effect.
If you dump the tablegen records, if the change was effective there should be a src0_modifiers operand on the V_MOV_B32_e32 instruction.

That said, I'm not convinced doing this properly would be worth the effort. Perhaps I should just close the issue.
@arsenm
@foad

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt

435

It's curious that this results in sext(v2). It should print -v2. sext is not supported on v_mov_b32. Perhaps this is caused by the wrong operand class being set, or due to a bug in the inst printer.

[arsenm]

In D144271#4139979, @Joe_Nash wrote:

Actually, I think due to the way the operand lists for _e32 instructions are constructed, the modifiers are not taking effect.
If you dump the tablegen records, if the change was effective there should be a src0_modifiers operand on the V_MOV_B32_e32 instruction.

I'd expect it to only be on v_mov_b32_e64?

[Joe_Nash]

In D144271#4139981, @arsenm wrote:

In D144271#4139979, @Joe_Nash wrote:

Actually, I think due to the way the operand lists for _e32 instructions are constructed, the modifiers are not taking effect.
If you dump the tablegen records, if the change was effective there should be a src0_modifiers operand on the V_MOV_B32_e32 instruction.

I'd expect it to only be on v_mov_b32_e64?

I guess the spec was changed between gfx9 and gfx10. On gfx10 and newer the docs say modifiers are supported on VOP1 as well as VOP3. But in terms of what our backend would make with just the above patch, it seems the modifiers would be on v_mov_b32_e64 but not v_mov_b32_e32. Hence my ask to check the tablegen records.

[foad]

In D144271#4139988, @Joe_Nash wrote:

In D144271#4139981, @arsenm wrote:

In D144271#4139979, @Joe_Nash wrote:

Actually, I think due to the way the operand lists for _e32 instructions are constructed, the modifiers are not taking effect.
If you dump the tablegen records, if the change was effective there should be a src0_modifiers operand on the V_MOV_B32_e32 instruction.

I'd expect it to only be on v_mov_b32_e64?

I guess the spec was changed between gfx9 and gfx10. On gfx10 and newer the docs say modifiers are supported on VOP1 as well as VOP3. But in terms of what our backend would make with just the above patch, it seems the modifiers would be on v_mov_b32_e64 but not v_mov_b32_e32. Hence my ask to check the tablegen records.

There are no modifiers in VOP1 - there are no bits in the encoding for them.

[danilomilosevic]

• Fixed sext appearing in v_mod_b32_e64_dpp
• Fixed disassembler tests

[Joe_Nash]

In D144271#4140757, @foad wrote:

In D144271#4139988, @Joe_Nash wrote:

In D144271#4139981, @arsenm wrote:

In D144271#4139979, @Joe_Nash wrote:

Actually, I think due to the way the operand lists for _e32 instructions are constructed, the modifiers are not taking effect.
If you dump the tablegen records, if the change was effective there should be a src0_modifiers operand on the V_MOV_B32_e32 instruction.

I'd expect it to only be on v_mov_b32_e64?

I guess the spec was changed between gfx9 and gfx10. On gfx10 and newer the docs say modifiers are supported on VOP1 as well as VOP3. But in terms of what our backend would make with just the above patch, it seems the modifiers would be on v_mov_b32_e64 but not v_mov_b32_e32. Hence my ask to check the tablegen records.

There are no modifiers in VOP1 - there are no bits in the encoding for them.

Ah yes, that makes a lot more sense. Sorry, I was not thinking clearly there.
The intention of this patch seems ok then to allow the modifiers on v_mov_b32_e64. Since modifiers are not supported on gfx9 and earlier, it would likely need the introduction of a new pseudo instruction for v_mov_b32, one for gfx10Plus that allows modifiers on VOP3.

But we make limited use of v_mov_b32_e64. So should more work be done to make use of it?
The potential utility is to do something like v_mov_b32 v0, -v1. But in a lot of cases this could be folded into the use of v0 by setting the neg modifier there.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
 
   unsigned I = 1;
   const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
   for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
   }
 
   int Fi = 0;
+  int Clamp = 0;
   for (unsigned E = Operands.size(); I != E; ++I) {
     auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),
                                             MCOI::TIED_TO);
     if (TiedTo != -1) {
       assert((unsigned)TiedTo < Inst.getNumOperands());
       // handle tied old or src2 for MAC instructions
       Inst.addOperand(Inst.getOperand(TiedTo));
     }
     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
     // Add the register arguments
     if (Op.isReg() && validateVccOperand(Op.getReg())) {
       // VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.
       // Skip it.
       continue;
     }
 
+    if (Op.isClampSI()) {
+      Clamp = Op.getImm();
+      continue;
+    }
     if (IsDPP8) {
       if (Op.isDPP8()) {
         Op.addImmOperands(Inst, 1);
       } else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
         Op.addRegWithFPInputModsOperands(Inst, 2);
       } else if (Op.isFI()) {
         Fi = Op.getImm();
       } else if (Op.isReg()) {
if (IsDPP8) {
       } else {
         llvm_unreachable("Invalid operand type");
       }
     }
   }
 
   if (IsDPP8) {
     using namespace llvm::AMDGPU::DPP;
+    if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp)) {
+      Inst.addOperand(MCOperand::createImm(Clamp));
+    }
     Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));
   } else {
+    if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp)) {
+      addOptionalImmOperand(Inst, Operands, OptionalIdx,
+                            AMDGPUOperand::ImmTyClampSI, Clamp);
+    }
     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
     if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) {
       addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi);
     }
   }
 }

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) {
     if (Dst.isPhysical()) {
       MovDPP.addDef(RI.getSubReg(Dst, Sub));
     } else {
       assert(MRI.isSSA());
       auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
       MovDPP.addDef(Tmp);
     }
 
+    MachineOperand *Src0Mods =
+        getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
     for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
       const MachineOperand &SrcOp = MI.getOperand(I);
+      if (I == 2)
+        MovDPP.addImm(Src0Mods ? Src0Mods->getImm() : 0);
       assert(!SrcOp.isFPImm());
       if (SrcOp.isImm()) {
         APInt Imm(64, SrcOp.getImm());
         Imm.ashrInPlace(Part * 32);
         MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
       } else {
         assert(SrcOp.isReg());
         Register Src = SrcOp.getReg();

llvm/lib/Target/AMDGPU/VOP1Instructions.td

 //===----------------------------------------------------------------------===//
 // VOP1 Instructions
 //===----------------------------------------------------------------------===//
 
 let VOPAsmPrefer32Bit = 1 in {
 defm V_NOP : VOP1Inst <"v_nop", VOP_NOP_PROFILE>;
 }
 
-def VOPProfile_MOV : VOPProfile <[i32, i32, untyped, untyped]> {
+def VOPProfile_MOV : VOPProfile <[i32, i32, untyped, untyped], 1> {
   let InsVOPDX = (ins Src0RC32:$src0X);
   let InsVOPDXDeferred = (ins VSrc_f32_Deferred:$src0X);
   let InsVOPDY = (ins Src0RC32:$src0Y);
   let InsVOPDYDeferred = (ins VSrc_f32_Deferred:$src0Y);
+  let HasModifiers = 1;
+  let Src0Mod = FP32InputMods;
+  let Src0ModVOP3DPP = FPVRegInputMods;
 }
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 defm V_MOV_B32 : VOP1Inst <"v_mov_b32", VOPProfile_MOV, null_frag, 0x8>;
 
 let SubtargetPredicate = isGFX940Plus in
 defm V_MOV_B64 : VOP1Inst <"v_mov_b64", VOP_I64_I64>;
 } // End isMoveImm = 1

 
 } // End VOP1 = 1, SubtargetPredicate = isGFX8GFX9, Uses = [M0]
 
 let OtherPredicates = [isGFX8Plus] in {
 
 def : GCNPat <
   (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask,
                            timm:$bank_mask, timm:$bound_ctrl)),
-  (V_MOV_B32_dpp VGPR_32:$src, VGPR_32:$src, (as_i32timm $dpp_ctrl),
+  (V_MOV_B32_dpp VGPR_32:$src, SRCMODS.NONE, VGPR_32:$src, (as_i32timm $dpp_ctrl),
                        (as_i32timm $row_mask), (as_i32timm $bank_mask),
                        (as_i1timm $bound_ctrl))
 >;
 
 def : GCNPat <
   (i32 (int_amdgcn_update_dpp i32:$old, i32:$src, timm:$dpp_ctrl,
                               timm:$row_mask, timm:$bank_mask,
                               timm:$bound_ctrl)),
-  (V_MOV_B32_dpp VGPR_32:$old, VGPR_32:$src, (as_i32timm $dpp_ctrl),
+  (V_MOV_B32_dpp VGPR_32:$old, SRCMODS.NONE, VGPR_32:$src, (as_i32timm $dpp_ctrl),
                  (as_i32timm $row_mask), (as_i32timm $bank_mask),
                  (as_i1timm $bound_ctrl))
 >;
 
 } // End OtherPredicates = [isGFX8Plus]
 
 let OtherPredicates = [isGFX8Plus] in {
 def : GCNPat<

 
 //===----------------------------------------------------------------------===//
 // GFX10
 //===----------------------------------------------------------------------===//
 
 let OtherPredicates = [isGFX10Only] in {
 def : GCNPat <
   (i32 (int_amdgcn_mov_dpp8 i32:$src, timm:$dpp8)),
-  (V_MOV_B32_dpp8_gfx10 VGPR_32:$src, VGPR_32:$src,
+  (V_MOV_B32_dpp8_gfx10 VGPR_32:$src, SRCMODS.NONE, VGPR_32:$src,
                         (as_i32timm $dpp8), (i32 DPP8Mode.FI_0))
 >;
 } // End OtherPredicates = [isGFX10Only]
 
 //===----------------------------------------------------------------------===//
 // GFX11
 //===----------------------------------------------------------------------===//
 
 let OtherPredicates = [isGFX11Only] in {
 def : GCNPat <
   (i32 (int_amdgcn_mov_dpp8 i32:$src, timm:$dpp8)),
-  (V_MOV_B32_dpp8_gfx11 VGPR_32:$src, VGPR_32:$src,
+  (V_MOV_B32_dpp8_gfx11 VGPR_32:$src, SRCMODS.NONE, VGPR_32:$src,
                         (as_i32timm $dpp8), (i32 DPP8Mode.FI_0))
 >;
 } // End OtherPredicates = [isGFX11Only]

llvm/test/CodeGen/AMDGPU/dpp64_combine.mir

body: |
   bb.0:
     %1:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
     %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec
     %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
 ...
 
 # DPP64 does not support all control values and must be split to become legal
 # GCN-LABEL: name: dpp64_illegal_ctrl
-# GCN: %4:vgpr_32 = V_MOV_B32_dpp undef %1.sub0:vreg_64_align2, undef %2.sub0:vreg_64_align2, 1, 15, 15, 1, implicit $exec
-# GCN: %5:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64_align2, undef %2.sub1:vreg_64_align2, 1, 15, 15, 1, implicit $exec
+# GCN: %4:vgpr_32 = V_MOV_B32_dpp undef %1.sub0:vreg_64_align2, 0, undef %2.sub0:vreg_64_align2, 1, 15, 15, 1, implicit $exec
+# GCN: %5:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64_align2, 0, undef %2.sub1:vreg_64_align2, 1, 15, 15, 1, implicit $exec
 # GCN: %0:vreg_64_align2 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1
 # GCN: %3:vreg_64_align2 = V_CEIL_F64_e32 %0, implicit $mode, implicit $exec
 name: dpp64_illegal_ctrl
 tracksRegLiveness: true
 body: |
   bb.0:
     %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 1, 15, 15, 1, implicit $exec
     %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec
 ...

llvm/test/CodeGen/AMDGPU/dpp_combine.mir

 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
     ; VOP2
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
 
-    %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 0, implicit $exec
     %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
 
-    %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
+    %7:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 1, implicit $exec
     %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
 
-    %9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
 
     ; VOP1
-    %11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %11:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %12:vgpr_32 = V_NOT_B32_e32 %11, implicit $exec
 
-    %13:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
+    %13:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 0, implicit $exec
     %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec
 
-    %15:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
+    %15:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 1, implicit $exec
     %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
 
-    %17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %17:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
 ...
 
 # old is zero cases:
 
 # GCN-LABEL: name: old_is_0
 
 # VOP2:

 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
     ; VOP2
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
 
-    %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 0, implicit $exec
     %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
 
-    %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
+    %7:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 1, implicit $exec
     %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
 
-    %9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
 
     ; VOP1
-    %11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %11:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %12:vgpr_32 = V_NOT_B32_e32 %11, implicit $exec
 
-    %13:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
+    %13:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 0, implicit $exec
     %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec
 
-    %15:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
+    %15:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 1, implicit $exec
     %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
 
-    %17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %17:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
 ...
 
 # old is nonzero identity cases:
 
 # old is nonzero identity, masks are fully enabled, bound_ctrl:1 is off:
 # the DPP mov result would be either identity ({src lane disabled}|{out of
 # range}) or src lane result - can combine with old = src1 of the VALU op

 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
 
     %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 0, implicit $exec
     %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
 
     %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
-    %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 15, 0, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %5, 0, %0, 1, 15, 15, 0, implicit $exec
     %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
 
     %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
-    %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 15, 15, 0, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %8, 0, %0, 1, 15, 15, 0, implicit $exec
     %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
 
     %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
-    %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 15, 0, implicit $exec
+    %12:vgpr_32 = V_MOV_B32_dpp %11, 0, %0, 1, 15, 15, 0, implicit $exec
     %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
 ...
 
 # old is nonzero identity, masks are partially enabled, bound_ctrl:1 is off:
 # the DPP mov result would be either identity ({src lane disabled}|{src lane is
 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
 # active src lane result - can combine with old = src1 of the VALU op.
 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they

 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
 
     %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
 
     %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
-    %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %5, 0, %0, 1, 15, 14, 0, implicit $exec
     %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
 
     %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
-    %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %8, 0, %0, 1, 14, 15, 0, implicit $exec
     %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
 
     %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
-    %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec
+    %12:vgpr_32 = V_MOV_B32_dpp %11, 0, %0, 1, 15, 14, 0, implicit $exec
     %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
 ...
 
 # old is nonzero identity, masks are partially enabled, bound_ctrl:1 is on:
 # the DPP mov result may have 3 different values:
 #   1. the active src lane result
 #   2. 0 if the src lane is disabled|out of range
 #   3. DPP mov's old value if the mov's dest VGPR write is disabled by masks

 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
 
     %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 1, implicit $exec
     %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
 
     %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
-    %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 1, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %5, 0, %0, 1, 15, 14, 1, implicit $exec
     %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
 
     %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
-    %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 1, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %8, 0, %0, 1, 14, 15, 1, implicit $exec
     %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
 
     %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
-    %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 1, implicit $exec
+    %12:vgpr_32 = V_MOV_B32_dpp %11, 0, %0, 1, 15, 14, 1, implicit $exec
     %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
 ...
 
 # when the DPP source isn't a src0 operand the operation should be commuted if possible
 # GCN-LABEL: name: dpp_commute
 # GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 # GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
 # GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 # GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
 # GCN: %16:vgpr_32 = V_SUBREV_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
 # GCN: %19:vgpr_32 = V_ADD_CO_U32_e32 5, %18, implicit-def $vcc, implicit $exec
 name: dpp_commute
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
 
     %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %4:vgpr_32 = V_MUL_U32_U24_e32 %1, %3, implicit $exec
 
     %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
-    %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %5, 0, %0, 1, 15, 14, 0, implicit $exec
     %7:vgpr_32 = V_AND_B32_e32 %1, %6, implicit $exec
 
     %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
-    %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %8, 0, %0, 1, 14, 15, 0, implicit $exec
     %10:vgpr_32 = V_MAX_I32_e32 %1, %9, implicit $exec
 
     %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
-    %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec
+    %12:vgpr_32 = V_MOV_B32_dpp %11, 0, %0, 1, 15, 14, 0, implicit $exec
     %13:vgpr_32 = V_MIN_I32_e32 %1, %12, implicit $exec
 
     %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %15:vgpr_32 = V_MOV_B32_dpp %14, %0, 1, 14, 15, 0, implicit $exec
+    %15:vgpr_32 = V_MOV_B32_dpp %14, 0, %0, 1, 14, 15, 0, implicit $exec
     %16:vgpr_32 = V_SUB_CO_U32_e32 %1, %15, implicit-def $vcc, implicit $exec
 
     ; this cannot be combined because immediate as src0 isn't commutable
     %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %18:vgpr_32 = V_MOV_B32_dpp %17, %0, 1, 14, 15, 0, implicit $exec
+    %18:vgpr_32 = V_MOV_B32_dpp %17, 0, %0, 1, 14, 15, 0, implicit $exec
     %19:vgpr_32 = V_ADD_CO_U32_e32 5, %18, implicit-def $vcc, implicit $exec
 ...
 
 ---
 
 # check for floating point modifiers
 # GCN-LABEL: name: add_f32_e64
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
 # GCN: %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $mode, implicit $exec
 # GCN: %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec
 # GCN: %8:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 15, 15, 1, implicit $mode, implicit $exec
 # GCN: %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $mode, implicit $exec
 
 name: add_f32_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
     ; this shouldn't be combined as omod is set
-    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $mode, implicit $exec
 
     ; this should be combined as all modifiers are default
-    %5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $mode, implicit $exec
 
     ; this should be combined as modifiers other than abs|neg are default
-    %7:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %7:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %8:vgpr_32 = V_ADD_F32_e64 1, %7, 2, %0, 0, 0, implicit $mode, implicit $exec
 
     ; this shouldn't be combined as modifiers aren't abs|neg
-    %9:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $mode, implicit $exec
 ...
 
 # check for e64 modifiers
 # GCN-LABEL: name: add_u32_e64
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec
 # GCN: %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec
 
 name: add_u32_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
     ; this should be combined as all modifiers are default
-    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e64 %3, %1, 0, implicit $exec
 
     ; this shouldn't be combined as clamp is set
-    %5:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec
 ...
 
 # GCN-LABEL: name: add_co_u32_e64
 # GCN: %4:vgpr_32, %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, %1, 0, implicit $exec
 
 name: add_co_u32_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
     ; this shouldn't be combined as the carry-out is used
-    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32, %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, %1, 0, implicit $exec
 
     S_NOP 0, implicit %5
 ...
 
 # tests on sequences of dpp consumers
 # GCN-LABEL: name: dpp_seq
 # GCN: %4:vgpr_32 = V_ADD_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
 # GCN: %5:vgpr_32 = V_SUBREV_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
 # GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 # broken sequence:
-# GCN: %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+# GCN: %7:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
 
 name: dpp_seq
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %4:vgpr_32 = V_ADD_CO_U32_e32 %3, %1, implicit-def $vcc, implicit $exec
     %5:vgpr_32 = V_SUB_CO_U32_e32 %1, %3, implicit-def $vcc, implicit $exec
     %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec
 
-    %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %7:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %8:vgpr_32 = V_ADD_CO_U32_e32 %7, %1, implicit-def $vcc, implicit $exec
     ; this breaks the sequence
     %9:vgpr_32 = V_SUB_CO_U32_e32 5, %7, implicit-def $vcc, implicit $exec
 ...
 
 # tests on sequences of dpp consumers followed by control flow
 # GCN-LABEL: name: dpp_seq_cf
 # GCN: %4:vgpr_32 = V_ADD_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
 # GCN: %5:vgpr_32 = V_SUBREV_CO_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
 # GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 
 name: dpp_seq_cf
 tracksRegLiveness: true
 body: |
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %4:vgpr_32 = V_ADD_CO_U32_e32 %3, %1, implicit-def $vcc, implicit $exec
     %5:vgpr_32 = V_SUB_CO_U32_e32 %1, %3, implicit-def $vcc, implicit $exec
     %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec
 
     %7:sreg_64 = V_CMP_EQ_U32_e64 %5, %6, implicit $exec
     %8:sreg_64 = SI_IF %7, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
     S_BRANCH %bb.1
 
bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %1, 1, 1, 1, 0, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %0, implicit $exec
 ...
 
 # old reg def is in diff BB but bound_ctrl:1 - can combine
 # GCN-LABEL: name: old_in_diff_bb_bctrl_zero
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp {{%[0-9]}}, %0, %1, 1, 15, 15, 1, implicit $exec
 
 name: old_in_diff_bb_bctrl_zero
 tracksRegLiveness: true
 body: |
   bb.0:
     successors: %bb.1
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
 ...
 
 # EXEC mask changed between def and use - cannot combine
 # GCN-LABEL: name: exec_changed
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
 
 name: exec_changed
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
     %5:sreg_64 = COPY $exec, implicit-def $exec
     %6:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
 ...
 
 # test if $old definition is correctly tracked through subreg manipulation pseudos
 
 # GCN-LABEL: name: mul_old_subreg
 # GCN: %7:vgpr_32 = V_MUL_I32_I24_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
 
 name:            mul_old_subreg
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vreg_64 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
     %3:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vreg_64 = INSERT_SUBREG %4, %1, %subreg.sub1 ; %5.sub0 is taken from %4
-    %6:vgpr_32 = V_MOV_B32_dpp %5.sub0, %1, 1, 1, 1, 0, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %5.sub0, 0, %1, 1, 1, 1, 0, implicit $exec
     %7:vgpr_32 = V_MUL_I32_I24_e32 %6, %0.sub1, implicit $exec
 ...
 
 # GCN-LABEL: name: add_old_subreg
 # GCN: %5:vgpr_32 = V_ADD_U32_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
 
 name:            add_old_subreg
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vreg_64 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted
-    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, 0, %1, 1, 1, 1, 0, implicit $exec
     %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
 ...
 
 # GCN-LABEL: name: add_old_subreg_undef
 # GCN: %5:vgpr_32 = V_ADD_U32_dpp undef %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec
 
 name:            add_old_subreg_undef
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vreg_64 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef
-    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, 0, %1, 1, 15, 15, 1, implicit $exec
     %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
 ...
 
 # Test instruction which does not have modifiers in VOP1 form but does in DPP form.
 # GCN-LABEL: name: dpp_vop1
 # GCN: %3:vgpr_32 = V_CEIL_F32_dpp %0, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: dpp_vop1
 tracksRegLiveness: true
 body: |
   bb.0:
     %1:vgpr_32 = IMPLICIT_DEF
-    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec
 ...
 
 # Test instruction which does not have modifiers in VOP2 form but does in DPP form.
 # GCN-LABEL: name: dpp_min
 # GCN: %3:vgpr_32 = V_MIN_F32_dpp %0, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: dpp_min
 tracksRegLiveness: true
 body: |
   bb.0:
     %1:vgpr_32 = IMPLICIT_DEF
-    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $mode, implicit $exec
 ...
 
 # Test an undef old operand
 # GCN-LABEL: name: dpp_undef_old
 # GCN: %3:vgpr_32 = V_CEIL_F32_dpp undef %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: dpp_undef_old
 tracksRegLiveness: true
 body: |
   bb.0:
-    %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec
 ...
 
 # Do not combine a dpp mov which writes a physreg.
 # GCN-LABEL: name: phys_dpp_mov_dst
-# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
+# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, 0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec
 name: phys_dpp_mov_dst
 tracksRegLiveness: true
 body: |
   bb.0:
-    $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec
 ...
 
 # Do not combine a dpp mov which reads a physreg.
 # GCN-LABEL: name: phys_dpp_mov_old_src
-# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
+# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, 0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec
 name: phys_dpp_mov_old_src
 tracksRegLiveness: true
 body: |
   bb.0:
-    %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec
 ...
 
 # Do not combine a dpp mov which reads a physreg.
 # GCN-LABEL: name: phys_dpp_mov_src
-# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec
+# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, 0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec
 name: phys_dpp_mov_src
 tracksRegLiveness: true
 body: |
   bb.0:
-    %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, 0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
     %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_both_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 # GCN: %9:vgpr_32 = IMPLICIT_DEF
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
 # GCN: %6:vgpr_32 = V_ADD_CO_U32_dpp %9, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_both_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_first_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
-# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
+# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 1, 1, 1, implicit $exec
 # GCN: %5:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, %4, %subreg.sub1
 # GCN: %6:vgpr_32 = V_ADD_CO_U32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_first_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 1, 1, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_second_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 1, 1, 1, implicit $exec
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, undef %4:vgpr_32, %subreg.sub1
 # GCN: %6:vgpr_32 = V_ADD_CO_U32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_second_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 1, 1, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_none_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
-# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 1, 1, 1, implicit $exec
+# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 1, 1, 1, implicit $exec
 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
 # GCN: %6:vgpr_32 = V_ADD_CO_U32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_none_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 1, 1, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 1, 1, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_exec_changed
 # GCN:   %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN:   %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN:   %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-# GCN:   %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-# GCN:   %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+# GCN:   %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+# GCN:   %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
 # GCN:   %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
 # GCN:   S_BRANCH %bb.1
 # GCN: bb.1:
 # GCN:   %6:vgpr_32 = V_ADD_CO_U32_e32 %5.sub0, %2, implicit-def $vcc, implicit $exec
 # GCN:   %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_exec_changed
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     S_BRANCH %bb.1
 
   bb.1:
     %6:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %5, implicit-def $vcc, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_subreg
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
 # GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1
 # GCN: %7:vgpr_32 = V_ADD_CO_U32_e32 %6.sub0, %2, implicit-def $vcc, implicit $exec
 # GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_subreg
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %8:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vreg_64 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub1, %subreg.sub1
     %6:vgpr_32 = V_ADD_CO_U32_e32 %5.sub0, %8, implicit-def $vcc, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %8, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp64_add64_impdef
 # GCN: %3:vgpr_32 = V_ADD_CO_U32_dpp %1.sub0, %0.sub0, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec

 body: |
   bb.0:
     %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
     %5:vgpr_32 = V_ADD_CO_U32_e32 %2.sub0, undef %4:vgpr_32, implicit-def $vcc, implicit $exec
     %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp64_add64_first_combined
-# GCN: %8:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64, undef %2.sub1:vreg_64, 1, 15, 15, 1, implicit $exec
+# GCN: %8:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64, 0, undef %2.sub1:vreg_64, 1, 15, 15, 1, implicit $exec
 # GCN: %0:vreg_64 = REG_SEQUENCE undef %7:vgpr_32, %subreg.sub0, %8, %subreg.sub1
 # GCN: %3:vgpr_32 = V_ADD_CO_U32_dpp undef %1.sub0:vreg_64, undef %2.sub0:vreg_64, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $exec
 # GCN: %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %0.sub1, undef $vcc, 0, implicit $exec
 name: dpp64_add64_first_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_CO_U32_e32 %2.sub0, undef %3:vgpr_32, implicit-def $vcc, implicit $exec
     %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %2.sub1, undef $vcc, 0, implicit $exec
 ...
 
 # GCN-LABEL: name: dont_combine_cndmask_with_src2
 # GCN: %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec
 name: dont_combine_cndmask_with_src2
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:sreg_64_xexec = IMPLICIT_DEF
     %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec
 ...
 
 ---
 
 # Make sure flags aren't dropped
 # GCN-LABEL: name: flags_add_f32_e64
 # GCN: %4:vgpr_32 = nnan nofpexcept V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: flags_add_f32_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
-    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = nofpexcept nnan V_ADD_F32_e64 0, %3, 0, %0, 0, 0, implicit $mode, implicit $exec
     S_ENDPGM 0, implicit %4
 
 ...
 
 # GCN-LABEL: name: dont_combine_more_than_one_operand
 # GCN: %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
 name: dont_combine_more_than_one_operand
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
-    %2:vgpr_32 = V_MOV_B32_dpp %0, %1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0, 0, %1, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
 ...
 
 # GCN-LABEL: name: dont_combine_more_than_one_operand_dpp_reg_sequence
 # GCN: %5:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec
 # GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dont_combine_more_than_one_operand_dpp_reg_sequence
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec
     %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # execMayBeModifiedBeforeAnyUse used to assert if the queried
 # V_MOV_B32_dpp was the last instruction in the block.
 ---
body:             |
   ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
   ; GCN-NEXT:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT: bb.1:
   ; GCN-NEXT:   successors: %bb.2(0x80000000)
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %5, %bb.2
-  ; GCN-NEXT:   [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[PHI]], 323, 15, 15, 0, implicit $exec
+  ; GCN-NEXT:   [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], 0, [[PHI]], 323, 15, 15, 0, implicit $exec
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT: bb.2:
   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF2]], implicit $exec
   ; GCN-NEXT:   V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
   ; GCN-NEXT:   S_BRANCH %bb.3
   ; GCN-NEXT: {{  $}}
   ; GCN-NEXT: bb.3:
   ; GCN-NEXT:   S_ENDPGM 0
   bb.0:
     liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8
 
     %0:sgpr_32 = COPY $sgpr8
     %1:vgpr_32 = IMPLICIT_DEF
     %2:sreg_32 = IMPLICIT_DEF
     %3:sreg_64_xexec = IMPLICIT_DEF
 
   bb.1:
     %4:vgpr_32 = PHI %1, %bb.0, %5, %bb.2
-    %5:vgpr_32 = V_MOV_B32_dpp %1, %4, 323, 15, 15, 0, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp %1, 0, %4, 323, 15, 15, 0, implicit $exec
 
   bb.2:
     %6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %3, implicit $exec
     V_CMP_NE_U32_e32 1, %6, implicit-def $vcc, implicit $exec
     S_CBRANCH_VCCNZ %bb.1, implicit $vcc
     S_BRANCH %bb.3
 
   bb.3:
     S_ENDPGM 0
 
 ...

llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir

 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = COPY $vgpr2
     %3:vgpr_32 = IMPLICIT_DEF
-    %4:vgpr_32 = V_MOV_B32_dpp %3, %0, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3, 0, %0, 1, 15, 15, 1, implicit $exec
 
     %5:sreg_32_xm0_xexec = IMPLICIT_DEF
     %6:vgpr_32, %7:sreg_32_xm0_xexec = V_SUBBREV_U32_e64 %4, %1, %5, 1, implicit $exec
 
     %8:vgpr_32 = V_CVT_PK_U8_F32_e64 4, %4, 2, %2, 2, %1, 1, implicit $mode, implicit $exec
 
     ; should not be combined because src2 literal is illegal
-    %9:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %10:vgpr_32 = V_MED3_F32_e64 0, %9, 0, %0, 0, 12345678, 0, 0, implicit $mode, implicit $exec
 
     ; should not be combined because src1 imm is illegal
-    %11:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %11:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %12:vgpr_32 = V_MED3_F32_e64 0, %11, 0, 2, 0, %7, 0, 0, implicit $mode, implicit $exec
 ...
 
 # Regression test for src_modifiers on base u16 opcode
 # GCN-label: name: vop3_u16
 # GCN: %5:vgpr_32 = V_ADD_NC_U16_e64_dpp %3, 0, %1, 0, %3, 0, 0, 1, 15, 15, 1, implicit $exec
 # GCN: %7:vgpr_32 = V_ADD_NC_U16_e64_dpp %3, 4, %5, 8, %5, 0, 0, 1, 15, 15, 1, implicit $exec
 name: vop3_u16
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = COPY $vgpr2
     %3:vgpr_32 = IMPLICIT_DEF
-    %4:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %5:vgpr_32 = V_ADD_NC_U16_e64 0, %4, 0, %3, 0, 0, implicit $exec
-    %6:vgpr_32 = V_MOV_B32_dpp %3, %5, 1, 15, 15, 1, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %3, 0, %5, 1, 15, 15, 1, implicit $exec
     %7:vgpr_32 = V_ADD_NC_U16_e64 4, %6, 8, %5, 0, 0, implicit $exec
 ...
 
 name: vop3p
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GCN-LABEL: name: vop3p
     ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GCN: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], 0, [[COPY1]], 1, 15, 15, 1, implicit $exec
     ; GCN: [[V_DOT2_F32_F16_:%[0-9]+]]:vgpr_32 = V_DOT2_F32_F16 0, [[V_MOV_B32_dpp]], 0, [[COPY]], 0, [[COPY2]], 0, 5, 0, 0, 0, implicit $mode, implicit $exec
-    ; GCN: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], 0, [[COPY1]], 1, 15, 15, 1, implicit $exec
     ; GCN: [[V_DOT2_F32_F16_1:%[0-9]+]]:vgpr_32 = V_DOT2_F32_F16 0, [[V_MOV_B32_dpp1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, 4, 0, 0, implicit $mode, implicit $exec
     ; GCN: [[V_DOT2_F32_F16_dpp:%[0-9]+]]:vgpr_32 = V_DOT2_F32_F16_dpp [[DEF]], 10, [[COPY1]], 8, [[COPY]], 13, [[COPY2]], 1, 0, 7, 4, 5, 1, 15, 15, 1, implicit $mode, implicit $exec
     ; GCN: [[V_FMA_MIX_F32_dpp:%[0-9]+]]:vgpr_32 = V_FMA_MIX_F32_dpp [[DEF]], 8, [[COPY1]], 8, [[COPY]], 8, [[COPY2]], 1, 0, 7, 1, 15, 15, 1, implicit $mode, implicit $exec
     ; GCN: [[V_FMA_MIXLO_F16_dpp:%[0-9]+]]:vgpr_32 = V_FMA_MIXLO_F16_dpp [[DEF]], 8, [[COPY1]], 8, [[COPY]], 8, [[COPY2]], 0, [[COPY2]], 0, 7, 1, 15, 15, 1, implicit $mode, implicit $exec
     ; GCN: [[V_FMA_MIXHI_F16_dpp:%[0-9]+]]:vgpr_32 = V_FMA_MIXHI_F16_dpp [[DEF]], 8, [[COPY1]], 8, [[COPY]], 8, [[COPY2]], 1, [[COPY]], 0, 7, 1, 15, 15, 1, implicit $mode, implicit $exec
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = COPY $vgpr2
     %3:vgpr_32 = IMPLICIT_DEF
 
     ; this should not be combined because op_sel is not zero
-    %4:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %5:vgpr_32 = V_DOT2_F32_F16 0, %4, 0, %0, 0, %2, 0, 5, 0, 0, 0, implicit $mode, implicit $exec
 
     ; this should not be combined because op_sel_hi is not all set
-    %6:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %7:vgpr_32 = V_DOT2_F32_F16 0, %6, 0, %0, 0, %2, 0, 0, 4, 0, 0, implicit $mode, implicit $exec
 
-    %8:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %8:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %9:vgpr_32 = V_DOT2_F32_F16 10, %8, 8, %0, 13, %2, 1, 0, 7, 4, 5, implicit $mode, implicit $exec
 
-    %10:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %10:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %11:vgpr_32 = V_FMA_MIX_F32 8, %10, 8, %0, 8, %2, 1, 0, 7, implicit $mode, implicit $exec
 
-    %12:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %12:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %13:vgpr_32 = V_FMA_MIXLO_F16 8, %12, 8, %0, 8, %2, 0, %2, 0, 7, implicit $mode, implicit $exec
 
-    %14:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %14:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %15:vgpr_32 = V_FMA_MIXHI_F16 8, %14, 8, %0, 8, %2, 1, %0, 0, 7, implicit $mode, implicit $exec
 
 ...
 
 # GCN-LABEL: name: fmac_e64
 # GCN: %5:vgpr_32 = V_FMAC_F32_e64_dpp %3, 2, %0, 2, %1, 2, %2, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: fmac_e64
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = COPY $vgpr2
     %3:vgpr_32 = IMPLICIT_DEF
-    %4:vgpr_32 = V_MOV_B32_dpp %3, %0, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3, 0, %0, 1, 15, 15, 1, implicit $exec
     %6:vgpr_32 = V_FMAC_F32_e64 2, %4, 2, %1, 2, %2, 1, 2, implicit $mode, implicit $exec
 ...
 
 # when the DPP source isn't a src0 operand the operation should be commuted if possible
 # GCN-LABEL: name: dpp_commute_shrink
 # GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 # GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
 # GCN: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 # GCN: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
 # GCN: %16:vgpr_32 = V_SUBREV_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 name: dpp_commute_shrink
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
 
     %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %4:vgpr_32 = V_MUL_U32_U24_e64 %1, %3, 0, implicit $exec
 
     %5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
-    %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %5, 0, %0, 1, 15, 14, 0, implicit $exec
     %7:vgpr_32 = V_AND_B32_e64 %1, %6, implicit $exec
 
     %8:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
-    %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %8, 0, %0, 1, 14, 15, 0, implicit $exec
     %10:vgpr_32 = V_MAX_I32_e64 %1, %9, implicit $exec
 
     %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
-    %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec
+    %12:vgpr_32 = V_MOV_B32_dpp %11, 0, %0, 1, 15, 14, 0, implicit $exec
     %13:vgpr_32 = V_MIN_I32_e64 %1, %12, implicit $exec
 
     %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %15:vgpr_32 = V_MOV_B32_dpp %14, %0, 1, 14, 15, 0, implicit $exec
+    %15:vgpr_32 = V_MOV_B32_dpp %14, 0, %0, 1, 14, 15, 0, implicit $exec
     %16:vgpr_32 = V_SUB_U32_e64 %1, %15, 0, implicit $exec
 
 ...
 
 # do not combine, dpp arg used twice
 # GCN-label: name: dpp_arg_twice
 # GCN: %4:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %3, 2, %3, 1, 2, implicit $mode, implicit $exec
 # GCN: %6:vgpr_32 = V_FMA_F32_e64 2, %5, 2, %1, 2, %5, 1, 2, implicit $mode, implicit $exec
 # GCN: %8:vgpr_32 = V_FMA_F32_e64 2, %7, 2, %7, 2, %1, 1, 2, implicit $mode, implicit $exec
 name: dpp_arg_twice
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %3, 2, %3, 1, 2, implicit $mode, implicit $exec
 
-    %5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %6:vgpr_32 = V_FMA_F32_e64 2, %5, 2, %1, 2, %5, 1, 2, implicit $mode, implicit $exec
 
-    %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %7:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %8:vgpr_32 = V_FMA_F32_e64 2, %7, 2, %7, 2, %1, 1, 2, implicit $mode, implicit $exec
 
 ...
 
 # when the dpp source isn't a src0 operand the operation should be commuted if possible
 # GCN-label: name: dpp_commute_e64
 # GCN: %4:vgpr_32  = V_MUL_U32_U24_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec
 # GCN: %7:vgpr_32 = V_FMA_F32_e64_dpp %5, 2, %0, 1, %1, 2, %1, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec
 # GCN: %10:vgpr_32 = V_SUBREV_U32_e64_dpp %1, %0, %1, 1, 1, 14, 15, 0, implicit $exec
 # GCN: %13:vgpr_32, %14:sreg_32_xm0_xexec = V_ADD_CO_U32_e64_dpp %1, %0, %1, 0, 1, 14, 15, 0, implicit $exec
 # GCN: %17:vgpr_32, %18:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 5, %16, 0, implicit $exec
 name: dpp_commute_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
 
     %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %4:vgpr_32 = V_MUL_U32_U24_e64 %1, %3, 1, implicit $exec
 
     %5:vgpr_32 = IMPLICIT_DEF
-    %6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 15, 1, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %5, 0, %0, 1, 15, 15, 1, implicit $exec
     %7:vgpr_32 = V_FMA_F32_e64 1, %1, 2, %6, 2, %1, 1, 2, implicit $mode, implicit $exec
 
     %8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp %8, 0, %0, 1, 14, 15, 0, implicit $exec
     %10:vgpr_32 = V_SUB_U32_e64 %1, %9, 1, implicit $exec
 
     %11:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 14, 15, 0, implicit $exec
+    %12:vgpr_32 = V_MOV_B32_dpp %11, 0, %0, 1, 14, 15, 0, implicit $exec
     %13:vgpr_32, %14:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %1, %12, 0, implicit $exec
 
     ; this cannot be combined because immediate as src0 isn't commutable
     %15:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %16:vgpr_32 = V_MOV_B32_dpp %15, %0, 1, 14, 15, 0, implicit $exec
+    %16:vgpr_32 = V_MOV_B32_dpp %15, 0, %0, 1, 14, 15, 0, implicit $exec
     %17:vgpr_32, %18:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 5, %16, 0, implicit $exec
 ...
 
 ---
 
 # check for floating point modifiers
 # GCN-LABEL: name: add_f32_e64
 # GCN:   %4:vgpr_32 = V_ADD_F32_e64_dpp %2, 0, %1, 0, %0, 0, 1, 1, 15, 15, 1, implicit $mode, implicit $exec
 # GCN:   %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec
 # GCN:   %8:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 15, 15, 1, implicit $mode, implicit $exec
 # GCN:   %10:vgpr_32 = V_ADD_F32_e64_dpp %2, 4, %1, 8, %0, 0, 0, 1, 15, 15, 1, implicit $mode, implicit $exec
 
 name: add_f32_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
     ; this should be combined as e64
-    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $mode, implicit $exec
 
     ; this should be combined and shrunk as all modifiers are default
-    %5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $mode, implicit $exec
 
     ; this should be combined and shrunk as modifiers other than abs|neg are default
-    %7:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %7:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %8:vgpr_32 = V_ADD_F32_e64 1, %7, 2, %0, 0, 0, implicit $mode, implicit $exec
 
     ; this should be combined as e64
-    %9:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %9:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $mode, implicit $exec
 ...
 
 # check for e64 modifiers
 # GCN-LABEL: name: add_u32_e64
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec
 # GCN: %6:vgpr_32 = V_ADD_U32_e64_dpp %2, %0, %1, 1, 1, 15, 15, 1, implicit $exec
 
 name: add_u32_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
     ; this should be combined  and shrunk as all modifiers are default
-    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e64 %3, %1, 0, implicit $exec
 
     ; this should be combined as _e64
-    %5:vgpr_32 = V_MOV_B32_dpp undef %2, %0, 1, 15, 15, 1, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec
 ...
 
 # tests on sequences of dpp consumers
 # GCN-LABEL: name: dpp_seq
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0,  implicit $exec
 # GCN: %5:vgpr_32 = V_SUBREV_U32_dpp %1, %0, %1, 1, 14, 15, 0,  implicit $exec
 # GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 # broken sequence:
-# GCN: %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+# GCN: %7:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
 
 name: dpp_seq
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %1,  implicit $exec
     %5:vgpr_32 = V_SUB_U32_e32 %1, %3,  implicit $exec
     %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec
 
-    %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %7:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %8:vgpr_32 = V_ADD_U32_e32 %7, %1,  implicit $exec
     ; this breaks the sequence
     %9:vgpr_32 = V_SUB_U32_e32 5, %7,  implicit $exec
 ...
 
 # tests on sequences of dpp consumers followed by control flow
 # GCN-LABEL: name: dpp_seq_cf
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 # GCN: %5:vgpr_32 = V_SUBREV_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 # GCN: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 
 name: dpp_seq_cf
 tracksRegLiveness: true
 body: |
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 14, 15, 0, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
     %5:vgpr_32 = V_SUB_U32_e32 %1, %3, implicit $exec
     %6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec
 
     %7:sreg_32 = V_CMP_EQ_U32_e64 %5, %6, implicit $exec
     %8:sreg_32 = SI_IF %7, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
     S_BRANCH %bb.1
 
bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %1, 1, 1, 1, 0, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %0, implicit $exec
 ...
 
 # old reg def is in diff BB but bound_ctrl:1 - can combine
 # GCN-LABEL: name: old_in_diff_bb_bctrl_zero
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp {{%[0-9]}}, %0, %1, 1, 15, 15, 1, implicit $exec
 
 name: old_in_diff_bb_bctrl_zero
 tracksRegLiveness: true
 body: |
   bb.0:
     successors: %bb.1
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
 ...
 
 # EXEC mask changed between def and use - cannot combine
 # GCN-LABEL: name: exec_changed
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
 
 name: exec_changed
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
     %5:sreg_64 = COPY $exec, implicit-def $exec
     %6:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
 ...
 
 # test if $old definition is correctly tracked through subreg manipulation pseudos
 
 # GCN-LABEL: name: mul_old_subreg
 # GCN: %7:vgpr_32 = V_MUL_I32_I24_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
 
 name:            mul_old_subreg
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vreg_64 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
     %3:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vreg_64 = INSERT_SUBREG %4, %1, %subreg.sub1 ; %5.sub0 is taken from %4
-    %6:vgpr_32 = V_MOV_B32_dpp %5.sub0, %1, 1, 1, 1, 0, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %5.sub0, 0, %1, 1, 1, 1, 0, implicit $exec
     %7:vgpr_32 = V_MUL_I32_I24_e32 %6, %0.sub1, implicit $exec
 ...
 
 # GCN-LABEL: name: add_old_subreg
 # GCN: %5:vgpr_32 = V_ADD_U32_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
 
 name:            add_old_subreg
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vreg_64 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted
-    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, 0, %1, 1, 1, 1, 0, implicit $exec
     %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
 ...
 
 # GCN-LABEL: name: add_old_subreg_undef
 # GCN: %5:vgpr_32 = V_ADD_U32_dpp undef %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec
 
 name:            add_old_subreg_undef
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vreg_64 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef
-    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, 0, %1, 1, 15, 15, 1, implicit $exec
     %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
 ...
 
 # Test instruction which does not have modifiers in VOP1 form but does in DPP form.
 # GCN-LABEL: name: dpp_vop1
 # GCN: %3:vgpr_32 = V_CEIL_F32_dpp %0, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: dpp_vop1
 tracksRegLiveness: true
 body: |
   bb.0:
     %1:vgpr_32 = IMPLICIT_DEF
-    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec
 ...
 
 # Test instruction which does not have modifiers in VOP2 form but does in DPP form.
 # GCN-LABEL: name: dpp_min
 # GCN: %3:vgpr_32 = V_MIN_F32_dpp %0, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: dpp_min
 tracksRegLiveness: true
 body: |
   bb.0:
     %1:vgpr_32 = IMPLICIT_DEF
-    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $mode, implicit $exec
 ...
 
 # Test an undef old operand
 # GCN-LABEL: name: dpp_undef_old
 # GCN: %3:vgpr_32 = V_CEIL_F32_dpp undef %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: dpp_undef_old
 tracksRegLiveness: true
 body: |
   bb.0:
-    %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec
 ...
 
 # Do not combine a dpp mov which writes a physreg.
 # GCN-LABEL: name: phys_dpp_mov_dst
-# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
+# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, 0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec
 name: phys_dpp_mov_dst
 tracksRegLiveness: true
 body: |
   bb.0:
-    $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec
 ...
 
 # Do not combine a dpp mov which reads a physreg.
 # GCN-LABEL: name: phys_dpp_mov_old_src
-# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
+# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, 0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec
 name: phys_dpp_mov_old_src
 tracksRegLiveness: true
 body: |
   bb.0:
-    %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec
 ...
 
 # Do not combine a dpp mov which reads a physreg.
 # GCN-LABEL: name: phys_dpp_mov_src
-# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec
+# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, 0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
 # GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec
 name: phys_dpp_mov_src
 tracksRegLiveness: true
 body: |
   bb.0:
-    %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, 0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
     %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_both_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 # GCN: %9:vgpr_32 = IMPLICIT_DEF
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
 # GCN: %6:vgpr_32 = V_ADD_U32_dpp %9, %1.sub0, %2, 1, 15, 15, 1, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_both_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_first_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
-# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
+# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 1, 1, 1, implicit $exec
 # GCN: %5:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, %4, %subreg.sub1
 # GCN: %6:vgpr_32 = V_ADD_U32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_first_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 1, 1, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_second_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 1, 1, 1, implicit $exec
 # GCN: %8:vgpr_32 = IMPLICIT_DEF
 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, undef %4:vgpr_32, %subreg.sub1
 # GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_dpp %8, %1.sub1, %2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_second_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 1, 1, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_none_combined
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
-# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 1, 1, 1, implicit $exec
+# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 1, 1, 1, implicit $exec
 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
 # GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec
 # GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_none_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 1, 1, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 1, 1, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 1, 1, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_exec_changed
 # GCN:   %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN:   %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN:   %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-# GCN:   %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-# GCN:   %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+# GCN:   %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+# GCN:   %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
 # GCN:   %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
 # GCN:   S_BRANCH %bb.1
 # GCN: bb.1:
 # GCN:   %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec
 # GCN:   %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_exec_changed
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     S_BRANCH %bb.1
 
   bb.1:
     %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_subreg
 # GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
 # GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
 # GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+# GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
 # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
 # GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1
 # GCN: %7:vgpr_32 = V_ADD_U32_e32 %6.sub0, %2, implicit $exec
 # GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dpp_reg_sequence_subreg
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %8:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vreg_64 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub1, %subreg.sub1
     %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %8, implicit $exec
     %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %8, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_src2_reject
-#GCN: %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-#GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+#GCN: %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+#GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
 #GCN: %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
 #GCN: %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 #GCN: %6:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub0, 1, 2, implicit $mode, implicit $exec
 #GCN: %7:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub1, 1, 2, implicit $mode, implicit $exec
 name: dpp_reg_sequence_src2_reject
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
     ; use of dpp arg as src2, reject
     %6:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub0, 1, 2, implicit $mode, implicit $exec
     ; cannot commute src0 and src2, and %4.sub0 already rejected, reject
     %7:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub1, 1, 2, implicit $mode, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp_reg_sequence_src2
-#GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+#GCN: %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
 #GCN: %4:vreg_64 = REG_SEQUENCE undef %2:vgpr_32, %subreg.sub0, %3, %subreg.sub1
 #GCN: %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
 #GCN: %6:vgpr_32 = V_FMA_F32_e64_dpp %8, 2, %1.sub0, 2, %5, 2, %4.sub1, 1, 2, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: dpp_reg_sequence_src2
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
     %6:vgpr_32 = V_FMA_F32_e64 2, %4.sub0, 2, %5, 2, %4.sub1, 1, 2, implicit $mode, implicit $exec
 ...
 
 # GCN-LABEL: name: dpp64_add64_impdef
 # GCN: %3:vgpr_32 = V_ADD_U32_dpp %1.sub0, %0.sub0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $exec
 # GCN: %5:vgpr_32 = V_ADDC_U32_dpp %1.sub1, %0.sub1, undef %4:vgpr_32, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec

 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
-    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %2, 0, %0, 1, 15, 15, 1, implicit $exec
     %4:sreg_32_xm0_xexec = IMPLICIT_DEF
     %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec
 
     ; src2 is legal for _e64
-    %6:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 15, 15, 1, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %7:sreg_32_xm0_xexec = IMPLICIT_DEF
     %8:vgpr_32 = V_CNDMASK_B32_e64 4, %6, 0, %1, %7, implicit $exec
 ...
 
 ---
 
 # Make sure flags aren't dropped
 # GCN-LABEL: name: flags_add_f32_e64
 # GCN: %4:vgpr_32 = nnan nofpexcept V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec
 name: flags_add_f32_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
 
-    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp undef %2, 0, %1, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = nofpexcept nnan V_ADD_F32_e64 0, %3, 0, %0, 0, 0, implicit $mode, implicit $exec
     S_ENDPGM 0, implicit %4
 
 ...
 
 # GCN-LABEL: name: dont_combine_more_than_one_operand
 # GCN: %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
 name: dont_combine_more_than_one_operand
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
-    %2:vgpr_32 = V_MOV_B32_dpp %0, %1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0, 0, %1, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
 ...
 
 # GCN-LABEL: name: dont_combine_more_than_one_operand_dpp_reg_sequence
 # GCN: %5:vgpr_32 = V_ADD_U32_e32 %4.sub0, %4.sub0, implicit $exec
 # GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
 name: dont_combine_more_than_one_operand_dpp_reg_sequence
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
-    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, 0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, 0, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vgpr_32 = V_ADD_U32_e32 %4.sub0, %4.sub0, implicit $exec
     %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
 ...

llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir

 # VI-NEXT: S_NOP 4
 # VI-NEXT: V_MOV_B32_dpp
 
 name: dpp
 
 body: |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-    $vgpr1 = V_MOV_B32_dpp $vgpr1, $vgpr0, 0, 15, 15, 0, implicit $exec
+    $vgpr1 = V_MOV_B32_dpp $vgpr1, 0, $vgpr0, 0, 15, 15, 0, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
-    $vgpr3 = V_MOV_B32_dpp $vgpr3, $vgpr0, 0, 15, 15, 0, implicit $exec
+    $vgpr3 = V_MOV_B32_dpp $vgpr3, 0, $vgpr0, 0, 15, 15, 0, implicit $exec
     S_ENDPGM 0
 ...

llvm/test/CodeGen/AMDGPU/remat-vop.mir

bb.0:
     S_ENDPGM 0
 ...
 ---
 name:            test_remat_v_mov_b32_e64
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; GCN-LABEL: name: test_remat_v_mov_b32_e64
-    ; GCN: renamable $vgpr0 = V_MOV_B32_e64 1, implicit $exec
-    ; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e64 2, implicit $exec
+    ; GCN: renamable $vgpr0 = V_MOV_B32_e64 0, 1, 0, implicit $exec
+    ; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_e64 0, 2, 0, implicit $exec
     ; GCN-NEXT: S_NOP 0, implicit killed renamable $vgpr0
     ; GCN-NEXT: S_NOP 0, implicit killed renamable $vgpr1
-    ; GCN-NEXT: renamable $vgpr0 = V_MOV_B32_e64 3, implicit $exec
+    ; GCN-NEXT: renamable $vgpr0 = V_MOV_B32_e64 0, 3, 0, implicit $exec
     ; GCN-NEXT: S_NOP 0, implicit killed renamable $vgpr0
     ; GCN-NEXT: S_ENDPGM 0
-    %0:vgpr_32 = V_MOV_B32_e64 1, implicit $exec
-    %1:vgpr_32 = V_MOV_B32_e64 2, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_e64 3, implicit $exec
+    %0:vgpr_32 = V_MOV_B32_e64 0, 1, 0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_e64 0, 2, 0, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_e64 0, 3, 0, implicit $exec
     S_NOP 0, implicit %0
     S_NOP 0, implicit %1
     S_NOP 0, implicit %2
     S_ENDPGM 0
 ...
 ---
 name:            test_no_remat_v_mov_b32_dpp
 tracksRegLiveness: true
 machineFunctionInfo:
   stackPtrOffsetReg:  $sgpr32
 body:             |
   bb.0:
     ; GCN-LABEL: name: test_no_remat_v_mov_b32_dpp
-    ; GCN: renamable $vgpr0 = V_MOV_B32_dpp undef $vgpr0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
+    ; GCN: renamable $vgpr0 = V_MOV_B32_dpp undef $vgpr0, 0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
     ; GCN-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
-    ; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_dpp undef $vgpr1, undef $vgpr0, 1, 15, 15, 1, implicit $exec
-    ; GCN-NEXT: renamable $vgpr0 = V_MOV_B32_dpp undef $vgpr0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
+    ; GCN-NEXT: renamable $vgpr1 = V_MOV_B32_dpp undef $vgpr1, 0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
+    ; GCN-NEXT: renamable $vgpr0 = V_MOV_B32_dpp undef $vgpr0, 0, undef $vgpr0, 1, 15, 15, 1, implicit $exec
     ; GCN-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
     ; GCN-NEXT: renamable $vgpr0 = SI_SPILL_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5)
     ; GCN-NEXT: S_NOP 0, implicit killed renamable $vgpr0
     ; GCN-NEXT: S_NOP 0, implicit killed renamable $vgpr1
     ; GCN-NEXT: renamable $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5)
     ; GCN-NEXT: S_NOP 0, implicit killed renamable $vgpr0
     ; GCN-NEXT: S_ENDPGM 0
-    %1:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
-    %2:vgpr_32 = V_MOV_B32_dpp undef %2:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
-    %3:vgpr_32 = V_MOV_B32_dpp undef %3:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp undef %2:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp undef %3:vgpr_32, 0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     S_NOP 0, implicit %1
     S_NOP 0, implicit %2
     S_NOP 0, implicit %3
     S_ENDPGM 0
 ...
 ---
 name:            test_remat_v_accvgpr_read_b32
 tracksRegLiveness: true

llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir

bb.0:
     %18 = V_LSHLREV_B32_e64 16, %17, implicit $exec
     %19 = V_LSHRREV_B32_e64 16, %18, implicit $exec
     %20 = V_CVT_U32_F32_e32 %19, implicit $mode, implicit $exec
     %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec
     %23 = V_CVT_F32_I32_e32 123, implicit $mode, implicit $exec
     %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec
 
     %25 = V_LSHRREV_B32_e64 16, %3, implicit $exec
-    %26 = V_MOV_B32_e64 %25, implicit $exec
+    %26 = V_MOV_B32_e64 0, %25, 0, implicit $exec
     %26 = V_LSHLREV_B32_e64 16, %26, implicit $exec
     %27 = V_FRACT_F32_e64 0, %6, 0, 0, implicit $mode, implicit $exec
     %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec
     %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec
     %30 = V_SIN_F32_e64 0, %29, 0, 0, implicit $mode, implicit $exec
     %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec
     %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec
     %33 = V_CVT_U32_F32_e64 0, %32, 0, 0, implicit $mode, implicit $exec

llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir

bb.0:
     %18 = V_LSHLREV_B32_e64 16, %17, implicit $exec
     %19 = V_LSHRREV_B32_e64 16, %18, implicit $exec
     %20 = V_CVT_U32_F32_e32 %19, implicit $mode, implicit $exec
     %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec
     %23 = V_CVT_F32_I32_e32 123, implicit $mode, implicit $exec
     %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec
 
     %25 = V_LSHRREV_B32_e64 16, %3, implicit $exec
-    %26 = V_MOV_B32_e64 %25, implicit $exec
+    %26 = V_MOV_B32_e64 0, %25, 0, implicit $exec
     %26 = V_LSHLREV_B32_e64 16, %26, implicit $exec
     %27 = V_FRACT_F32_e64 0, %6, 0, 0, implicit $mode, implicit $exec
     %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec
     %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec
     %30 = V_SIN_F32_e64 0, %29, 0, 0, implicit $mode, implicit $exec
     %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec
     %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec
     %33 = V_CVT_U32_F32_e64 0, %32, 0, 0, implicit $mode, implicit $exec

llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir

bb.0:
     %14 = V_LSHRREV_B32_e64 16, %13, implicit $exec
     %15 = V_BFM_B32_e64 %13, killed %14, implicit-def $vcc, implicit $exec
 
     %16 = V_LSHRREV_B32_e64 16, %15, implicit $exec
     %17 = V_CVT_PKNORM_I16_F32_e64 0, %15, 0, killed %16, 0, implicit-def $vcc, implicit $exec
 
     %18 = V_LSHRREV_B32_e64 16, %17, implicit $exec
     %19 = V_READLANE_B32 killed %18, 0, implicit-def $vcc, implicit $exec
-    %20 = V_MOV_B32_e64 %19, implicit $exec
+    %20 = V_MOV_B32_e64 0, %19, 0, implicit $exec
 
     FLAT_STORE_DWORD %0, %20, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
     $sgpr30_sgpr31 = COPY %2
     S_SETPC_B64_return $sgpr30_sgpr31

llvm/test/CodeGen/AMDGPU/vopc_dpp.mir

bb.0:
     ; GCN-LABEL: name: vopc
     ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
     ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN-NEXT: V_CMP_LT_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], 0, [[COPY1]], 1, 15, 15, 1, implicit $exec
     ; GCN-NEXT: V_CMPX_EQ_I16_t16_nosdst_e64 [[V_MOV_B32_dpp]], [[COPY]], implicit-def $exec, implicit-def $vcc, implicit $mode, implicit $exec
     ; GCN-NEXT: [[V_CMP_CLASS_F16_t16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_t16_e64_dpp 0, [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit $exec
     ; GCN-NEXT: [[V_CMP_GE_F16_t16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_GE_F16_t16_e64_dpp 1, [[COPY1]], 0, [[COPY]], 1, 1, 15, 15, 1, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], 0, [[COPY1]], 1, 15, 15, 1, implicit $exec
     ; GCN-NEXT: V_CMPX_GT_U32_nosdst_e64 [[V_MOV_B32_dpp1]], [[COPY]], implicit-def $exec, implicit $mode, implicit $exec
     ; GCN-NEXT: V_CMP_CLASS_F32_e32_dpp 2, [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $exec
     ; GCN-NEXT: V_CMP_NGE_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], 0, [[COPY1]], 1, 15, 15, 1, implicit $exec
     ; GCN-NEXT: [[V_CMP_NGE_F16_t16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_NGE_F16_t16_e64 0, [[V_CMP_NGE_F16_t16_e64_]], 0, [[COPY]], 0, implicit $mode, implicit $exec
     ; GCN-NEXT: [[V_CMP_NGE_F32_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_NGE_F32_e64_dpp 0, [[COPY1]], 0, [[COPY]], 0, 1, 15, 15, 1, implicit $mode, implicit $exec
     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sgpr_32 = S_AND_B32 [[V_CMP_NGE_F32_e64_dpp]], 10101, implicit-def $scc
     ; GCN-NEXT: V_CMP_GT_I32_e32_dpp [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $exec
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = COPY $vgpr2
     %3:vgpr_32 = IMPLICIT_DEF
 
-    %4:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     V_CMP_LT_F32_e32 %4, %0, implicit-def $vcc, implicit $mode, implicit $exec
 
     ; unsafe to combine cmpx
-    %5:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     V_CMPX_EQ_I16_t16_nosdst_e64 %5, %0, implicit-def $exec, implicit-def $vcc, implicit $mode, implicit $exec
 
-    %6:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %6:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %7:sgpr_32 = V_CMP_CLASS_F16_t16_e64 0, %6, %0, implicit-def $vcc, implicit $mode, implicit $exec
 
-    %8:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %8:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %9:sgpr_32 = V_CMP_GE_F16_t16_e64 1, %8, 0, %0, 1, implicit $mode, implicit $exec
 
     ; unsafe to combine cmpx
-    %10:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %10:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     V_CMPX_GT_U32_nosdst_e64 %10, %0, implicit-def $exec, implicit $mode, implicit $exec
 
-    %11:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %11:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %12:sgpr_32 = V_CMP_CLASS_F32_e64 2, %11, %0, implicit $mode, implicit $exec
 
     ; shrink
-    %13:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %13:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %14:sgpr_32 = V_CMP_NGE_F32_e64 0, %13, 0, %0, 0, implicit $mode, implicit $exec
 
     ; do not shrink True16 instructions
-    %15:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %15:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %16:sgpr_32 = V_CMP_NGE_F16_t16_e64 0, %16, 0, %0, 0, implicit $mode, implicit $exec
 
     ; do not shrink, sdst used
-    %17:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %17:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     %18:sgpr_32 = V_CMP_NGE_F32_e64 0, %17, 0, %0, 0, implicit $mode, implicit $exec
     %19:sgpr_32 = S_AND_B32 %18, 10101, implicit-def $scc
 
     ; commute
-    %20:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 15, 15, 1, implicit $exec
+    %20:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 15, 15, 1, implicit $exec
     V_CMP_LT_I32_e32 %0, %20, implicit-def $vcc, implicit $exec
 
 ...
 ---
 
 name: mask_not_full
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GCN-LABEL: name: mask_not_full
     ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 14, 1, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], 0, [[COPY1]], 1, 15, 14, 1, implicit $exec
     ; GCN-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_t16_e64 0, [[V_MOV_B32_dpp]], [[COPY]], implicit-def $vcc, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[V_MOV_B32_e32_]], [[COPY1]], 1, 13, 15, 1, implicit $exec
+    ; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[V_MOV_B32_e32_]], 0, [[COPY1]], 1, 13, 15, 1, implicit $exec
     ; GCN-NEXT: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sgpr_32 = V_CMP_GE_F32_e64 1, [[V_MOV_B32_dpp1]], 0, [[COPY]], 1, implicit $mode, implicit $exec
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = IMPLICIT_DEF
     %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 
     ; Do not combine VOPC when row_mask or bank_mask is not 0xf
     ; All cases are covered by generic rules for creating DPP instructions
-    %4:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 15, 14, 1, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_dpp %2, 0, %1, 1, 15, 14, 1, implicit $exec
     %99:sgpr_32 = V_CMP_CLASS_F16_t16_e64 0, %4, %0, implicit-def $vcc, implicit $mode, implicit $exec
 
-    %5:vgpr_32 = V_MOV_B32_dpp %3, %1, 1, 13, 15, 1, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_dpp %3, 0, %1, 1, 13, 15, 1, implicit $exec
     %6:sgpr_32 = V_CMP_GE_F32_e64 1, %5, 0, %0, 1, implicit $mode, implicit $exec
 
 ...

llvm/test/CodeGen/AMDGPU/wqm.mir

bb.0:
     %6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
     %5:sgpr_128 = COPY %6
     %7:sreg_32 = S_MOV_B32 0
     %8:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %6, %7, 0, 0, 0, implicit $exec
     %16:vgpr_32 = COPY %8.sub1
     %11:vgpr_32 = COPY %16
     %10:vgpr_32 = V_SET_INACTIVE_B32 %11, undef %12:sreg_32, implicit $exec, implicit-def $scc
     %14:vgpr_32 = COPY %7
-    %13:vgpr_32 = V_MOV_B32_dpp %14, killed %10, 323, 12, 15, 0, implicit $exec
+    %13:vgpr_32 = V_MOV_B32_dpp %14, 0, killed %10, 323, 12, 15, 0, implicit $exec
     early-clobber %15:vgpr_32 = STRICT_WWM killed %13, implicit $exec
     BUFFER_STORE_DWORD_OFFSET_exact killed %15, %6, %7, 4, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...
 
 ---
 # Ensure that strict_wwm is not put around an EXEC copy
bb.0:
     %0:sgpr_32 = COPY $sgpr0
     %4:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
     %5:sreg_32 = S_MOV_B32 0
     %6:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %4, %5, 0, 0, 0, implicit $exec
 
     %8:sreg_64 = COPY $exec
     %9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %10:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %8.sub0:sreg_64, 0, implicit $exec
-    %11:vgpr_32 = V_MOV_B32_dpp %9:vgpr_32, %10:vgpr_32, 312, 15, 15, 0, implicit $exec
+    %11:vgpr_32 = V_MOV_B32_dpp %9:vgpr_32, 0, %10:vgpr_32, 312, 15, 15, 0, implicit $exec
     %12:sreg_32 = V_READLANE_B32 %11:vgpr_32, 63
     early-clobber %13:sreg_32 = STRICT_WWM %9:vgpr_32, implicit $exec
 
     %14:vgpr_32 = COPY %13
     BUFFER_STORE_DWORD_OFFSET_exact killed %14, %4, %5, 4, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...

llvm/test/MC/AMDGPU/gfx10_asm_vop1.s

 // GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x5f,0x01,0x00]
 
 v_mov_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
 // GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x61,0x01,0x00]
 
 v_mov_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
 // GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x6f,0x01,0x00]
 
+v_mov_b32_e64 v5, -v2
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2|
+// GFX10: encoding: [0x05,0x01,0x81,0xd5,0x02,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, -v2 clamp
+// GFX10: encoding: [0x05,0x80,0x81,0xd5,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2| clamp
+// GFX10: encoding: [0x05,0x81,0x81,0xd5,0x02,0x01,0x00,0x00]
+
 v_readfirstlane_b32 s5, v1
 // GFX10: encoding: [0x01,0x05,0x0a,0x7e]
 
 v_readfirstlane_b32 s103, v1
 // GFX10: encoding: [0x01,0x05,0xce,0x7e]
 
 v_readfirstlane_b32 ttmp11, v1
 // GFX10: encoding: [0x01,0x05,0xee,0x7e]

llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s

 // GFX11: [0x05,0x00,0xc4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01]
 
 v_movrelsd_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 // GFX11: [0x05,0x00,0xc4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x09,0x13]
 
 v_movrelsd_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // GFX11: [0xff,0x00,0xc4,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
 
+v_mov_b32_e64_dpp v5, -v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// GFX11: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x20,0x02,0x1b,0x00,0xff]
+
+v_mov_b32_e64_dpp v5, |v2| quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// GFX11: [0x05,0x01,0x81,0xd5,0xfa,0x00,0x00,0x00,0x02,0x1b,0x00,0xff]
+
+v_mov_b32_e64_dpp v5, -v2 clamp quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// GFX11: [0x05,0x80,0x81,0xd5,0xfa,0x00,0x00,0x20,0x02,0x1b,0x00,0xff]
+
+v_mov_b32_e64_dpp v5, |v2| clamp quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf
+// GFX11: [0x05,0x81,0x81,0xd5,0xfa,0x00,0x00,0x00,0x02,0x1b,0x00,0xff]
+
 v_not_b16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
 // GFX11: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
 
 v_not_b16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
 // GFX11: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
 
 v_not_b16_e64_dpp v5, v1 row_mirror
 // GFX11: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]

llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s

 // GFX11: [0x05,0x00,0xc4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 
 v_movrelsd_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
 // GFX11: [0x05,0x00,0xc4,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 
 v_movrelsd_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
 // GFX11: [0xff,0x00,0xc4,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
 
+v_mov_b32_e64_dpp v5, -v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: [0x05,0x00,0x81,0xd5,0xe9,0x00,0x00,0x20,0x02,0x77,0x39,0x05]
+
+v_mov_b32_e64_dpp v5, |v2| dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: [0x05,0x01,0x81,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
+
+v_mov_b32_e64_dpp v5, -v2 clamp dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: [0x05,0x80,0x81,0xd5,0xe9,0x00,0x00,0x20,0x02,0x77,0x39,0x05]
+
+v_mov_b32_e64_dpp v5, |v2| clamp dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: [0x05,0x81,0x81,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
+
 v_not_b16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: [0x05,0x00,0xe9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 
 v_not_b16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
 // GFX11: [0x05,0x00,0xe9,0xd5,0xea,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 
 v_not_b16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
 // GFX11: [0xff,0x00,0xe9,0xd5,0xe9,0x00,0x00,0x00,0xff,0x00,0x00,0x00]

llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s

 // GFX11: encoding: [0xff,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
 
 v_movrelsd_b32_e64 v5, v1
 // GFX11: encoding: [0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
 
 v_movrelsd_b32_e64 v255, v255
 // GFX11: encoding: [0xff,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
 
+v_mov_b32_e64 v5, -v2
+// GFX11: encoding: [0x05,0x00,0x81,0xd5,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2|
+// GFX11: encoding: [0x05,0x01,0x81,0xd5,0x02,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, -v2 clamp
+// GFX11: encoding: [0x05,0x80,0x81,0xd5,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2| clamp
+// GFX11: encoding: [0x05,0x81,0x81,0xd5,0x02,0x01,0x00,0x00]
+
 v_nop_e64
 // GFX11: encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
 
 v_not_b16_e64 v5, v1
 // GFX11: encoding: [0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00]
 
 v_not_b16_e64 v5, v255
 // GFX11: encoding: [0x05,0x00,0xe9,0xd5,0xff,0x01,0x00,0x00]

llvm/test/MC/AMDGPU/gfx7_asm_vop3.s

 // CHECK: [0x05,0x00,0x02,0xd3,0xfc,0x00,0x00,0x00]
 
 v_mov_b32_e64 v5, src_scc
 // CHECK: [0x05,0x00,0x02,0xd3,0xfd,0x00,0x00,0x00]
 
 v_mov_b32_e64 v5, src_lds_direct
 // CHECK: [0x05,0x00,0x02,0xd3,0xfe,0x00,0x00,0x00]
 
+v_mov_b32_e64 v5, -v2
+// CHECK: [0x05,0x00,0x02,0xd3,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2|
+// CHECK: [0x05,0x01,0x02,0xd3,0x02,0x01,0x00,0x00]
+
 v_cvt_i32_f64_e64 v5, v[1:2]
 // CHECK: [0x05,0x00,0x06,0xd3,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f64_e64 v255, v[1:2]
 // CHECK: [0xff,0x00,0x06,0xd3,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f64_e64 v5, v[254:255]
 // CHECK: [0x05,0x00,0x06,0xd3,0xfe,0x01,0x00,0x00]

llvm/test/MC/AMDGPU/gfx8_asm_vop3.s

 // CHECK: [0x05,0x00,0x41,0xd1,0xfc,0x00,0x00,0x00]
 
 v_mov_b32_e64 v5, src_scc
 // CHECK: [0x05,0x00,0x41,0xd1,0xfd,0x00,0x00,0x00]
 
 v_mov_b32_e64 v5, src_lds_direct
 // CHECK: [0x05,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00]
 
+v_mov_b32_e64 v5, -v2
+// CHECK: [0x05,0x00,0x41,0xd1,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2|
+// CHECK: [0x05,0x01,0x41,0xd1,0x02,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, -v2 clamp
+// CHECK: [0x05,0x80,0x41,0xd1,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2| clamp
+// CHECK: [0x05,0x81,0x41,0xd1,0x02,0x01,0x00,0x00]
+
 v_cvt_i32_f64_e64 v5, v[1:2]
 // CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f64_e64 v255, v[1:2]
 // CHECK: [0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f64_e64 v5, v[254:255]
 // CHECK: [0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00]

llvm/test/MC/AMDGPU/gfx9_asm_vop3.s

 // CHECK: [0x05,0x00,0x41,0xd1,0xfc,0x00,0x00,0x00]
 
 v_mov_b32_e64 v5, src_scc
 // CHECK: [0x05,0x00,0x41,0xd1,0xfd,0x00,0x00,0x00]
 
 v_mov_b32_e64 v5, src_lds_direct
 // CHECK: [0x05,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00]
 
+v_mov_b32_e64 v5, -v2
+// CHECK: [0x05,0x00,0x41,0xd1,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2|
+// CHECK: [0x05,0x01,0x41,0xd1,0x02,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, -v2 clamp
+// CHECK: [0x05,0x80,0x41,0xd1,0x02,0x01,0x00,0x20]
+
+v_mov_b32_e64 v5, |v2| clamp
+// CHECK: [0x05,0x81,0x41,0xd1,0x02,0x01,0x00,0x00]
+
 v_cvt_i32_f64_e64 v5, v[1:2]
 // CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f64_e64 v255, v[1:2]
 // CHECK: [0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f64_e64 v5, v[254:255]
 // CHECK: [0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00]

llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt

 0xff,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00
 
 # GFX10: v_movrelsd_b32_e64 v5, v1               ; encoding: [0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
 0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00
 
 # GFX10: v_movrelsd_b32_e64 v5, v255             ; encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
 0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00
 
+# GFX10: v_mov_b32_e64 v5, -v2                   ; encoding: [0x05,0x00,0x81,0xd5,0x02,0x01,0x00,0x20]
+0x05,0x00,0x81,0xd5,0x02,0x01,0x00,0x20
+
+# GFX10: v_mov_b32_e64 v5, |v2|                  ; encoding: [0x05,0x01,0x81,0xd5,0x02,0x01,0x00,0x00]
+0x05,0x01,0x81,0xd5,0x02,0x01,0x00,0x00
+
+# GFX10: v_mov_b32_e64 v5, -v2 clamp             ; encoding: [0x05,0x80,0x81,0xd5,0x02,0x01,0x00,0x20]
+0x05,0x80,0x81,0xd5,0x02,0x01,0x00,0x20
+
+# GFX10: v_mov_b32_e64 v5, |v2| clamp            ; encoding: [0x05,0x81,0x81,0xd5,0x02,0x01,0x00,0x00]
+0x05,0x81,0x81,0xd5,0x02,0x01,0x00,0x00
+
 # GFX10: v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4] ; encoding: [0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04]
 0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04
 
 # GFX10: v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4] ; encoding: [0x05,0x00,0x73,0xd5,0xc1,0x04,0x0e,0x04]
 0x05,0x00,0x73,0xd5,0xc1,0x04,0x0e,0x04
 
 # GFX10: v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4] ; encoding: [0x05,0x00,0x73,0xd5,0x80,0x04,0x0e,0x04]
 0x05,0x00,0x73,0xd5,0x80,0x04,0x0e,0x04

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt

 0x05,0x00,0xc4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x5f,0x01,0x01
 
 # GFX11: v_movrelsd_b32_e64_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0xc4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13]
 0x05,0x00,0xc4,0xd5,0xfa,0x00,0x00,0x00,0x01,0x60,0x01,0x13
 
 # GFX11: v_movrelsd_b32_e64_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0xc4,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30]
 0xff,0x00,0xc4,0xd5,0xfa,0x00,0x00,0x00,0xff,0x6f,0x0d,0x30
 
+# GFX11: v_mov_b32_e64_dpp v5, -v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x20,0x02,0x1b,0x00,0xff]
+0x05,0x00,0x81,0xd5,0xfa,0x00,0x00,0x20,0x02,0x1b,0x00,0xff
+
+# GFX11: v_mov_b32_e64_dpp v5, |v2| quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x81,0xd5,0xfa,0x00,0x00,0x00,0x02,0x1b,0x00,0xff]
+0x05,0x01,0x81,0xd5,0xfa,0x00,0x00,0x00,0x02,0x1b,0x00,0xff
+
+# GFX11: v_mov_b32_e64_dpp v5, -v2 clamp quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x80,0x81,0xd5,0xfa,0x00,0x00,0x20,0x02,0x1b,0x00,0xff]
+0x05,0x80,0x81,0xd5,0xfa,0x00,0x00,0x20,0x02,0x1b,0x00,0xff
+
+# GFX11: v_mov_b32_e64_dpp v5, |v2| clamp quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x81,0x81,0xd5,0xfa,0x00,0x00,0x00,0x02,0x1b,0x00,0xff]
+0x05,0x81,0x81,0xd5,0xfa,0x00,0x00,0x00,0x02,0x1b,0x00,0xff
+
 # GFX11: v_not_b16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
 0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
 
 # GFX11: v_not_b16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
 0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
 
 # GFX11: v_not_b16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
 0x05,0x00,0xe9,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt

 0xff,0x00,0xc8,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
 
 # GFX11: v_movrelsd_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xc4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 0x05,0x00,0xc4,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
 
 # GFX11: v_movrelsd_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xc4,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
 0xff,0x00,0xc4,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
 
+# GFX11: v_mov_b32_e64_dpp v5, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x81,0xd5,0xe9,0x00,0x00,0x20,0x02,0x77,0x39,0x05]
+0x05,0x00,0x81,0xd5,0xe9,0x00,0x00,0x20,0x02,0x77,0x39,0x05
+
+# GFX11: v_mov_b32_e64_dpp v5, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x81,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
+0x05,0x01,0x81,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05
+
+# GFX11: v_mov_b32_e64_dpp v5, -v2 clamp dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x80,0x81,0xd5,0xe9,0x00,0x00,0x20,0x02,0x77,0x39,0x05]
+0x05,0x80,0x81,0xd5,0xe9,0x00,0x00,0x20,0x02,0x77,0x39,0x05
+
+# GFX11: v_mov_b32_e64_dpp v5, |v2| clamp dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x81,0x81,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
+0x05,0x81,0x81,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05
+
 # GFX11: v_not_b16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 0x05,0x00,0xe9,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
 
 # GFX11: v_not_b16_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xe9,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
 0xff,0x00,0xe9,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
 
 # GFX11: v_not_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 0x05,0x00,0xb7,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt

 0xff,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00
 
 # GFX11: v_movrelsd_b32_e64 v5, v1               ; encoding: [0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
 0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00
 
 # GFX11: v_movrelsd_b32_e64 v255, v255           ; encoding: [0xff,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
 0xff,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00
 
+# GFX11: v_mov_b32_e64 v5, -v2                   ; encoding: [0x05,0x00,0x81,0xd5,0x02,0x01,0x00,0x20]
+0x05,0x00,0x81,0xd5,0x02,0x01,0x00,0x20
+
+# GFX11: v_mov_b32_e64 v5, |v2|                  ; encoding: [0x05,0x01,0x81,0xd5,0x02,0x01,0x00,0x00]
+0x05,0x01,0x81,0xd5,0x02,0x01,0x00,0x00
+
+# GFX11: v_mov_b32_e64 v5, -v2 clamp             ; encoding: [0x05,0x80,0x81,0xd5,0x02,0x01,0x00,0x20]
+0x05,0x80,0x81,0xd5,0x02,0x01,0x00,0x20
+
+# GFX11: v_mov_b32_e64 v5, |v2| clamp            ; encoding: [0x05,0x81,0x81,0xd5,0x02,0x01,0x00,0x00]
+0x05,0x81,0x81,0xd5,0x02,0x01,0x00,0x00
+
 # GFX11: v_nop                                   ; encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
 0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00
 
 # GFX11: v_not_b16_e64 v5, v1                    ; encoding: [0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00]
 0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00
 
 # GFX11: v_not_b16_e64 v5, v255                  ; encoding: [0x05,0x00,0xe9,0xd5,0xff,0x01,0x00,0x00]
 0x05,0x00,0xe9,0xd5,0xff,0x01,0x00,0x00

llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt

 0x05,0x00,0x41,0xd1,0xc1,0x00,0x00,0x00
 
 # CHECK: v_mov_b32_e64 v5, 0.5                   ; encoding: [0x05,0x00,0x41,0xd1,0xf0,0x00,0x00,0x00]
 0x05,0x00,0x41,0xd1,0xf0,0x00,0x00,0x00
 
 # CHECK: v_mov_b32_e64 v5, -4.0                  ; encoding: [0x05,0x00,0x41,0xd1,0xf7,0x00,0x00,0x00]
 0x05,0x00,0x41,0xd1,0xf7,0x00,0x00,0x00
 
+# CHECK: v_mov_b32_e64 v5, -v2                   ; encoding: [0x05,0x00,0x41,0xd1,0x02,0x01,0x00,0x20]
+0x05,0x00,0x41,0xd1,0x02,0x01,0x00,0x20
+
+# CHECK: v_mov_b32_e64 v5, |v2|                  ; encoding: [0x05,0x01,0x41,0xd1,0x02,0x01,0x00,0x00]
+0x05,0x01,0x41,0xd1,0x02,0x01,0x00,0x00
+
+# CHECK: v_mov_b32_e64 v5, -v2 clamp             ; encoding: [0x05,0x80,0x41,0xd1,0x02,0x01,0x00,0x20]
+0x05,0x80,0x41,0xd1,0x02,0x01,0x00,0x20
+
+# CHECK: v_mov_b32_e64 v5, |v2| clamp            ; encoding: [0x05,0x81,0x41,0xd1,0x02,0x01,0x00,0x00]
+0x05,0x81,0x41,0xd1,0x02,0x01,0x00,0x00
+
 # CHECK: v_cvt_i32_f64_e64 v5, v[1:2]            ; encoding: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
 0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00
 
 # CHECK: v_cvt_i32_f64_e64 v255, v[1:2]          ; encoding: [0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
 0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00
 
 # CHECK: v_cvt_i32_f64_e64 v5, v[254:255]        ; encoding: [0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00]
 0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00

llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt

 0x05,0x00,0x41,0xd1,0xc1,0x00,0x00,0x00
 
 # CHECK: v_mov_b32_e64 v5, 0.5                   ; encoding: [0x05,0x00,0x41,0xd1,0xf0,0x00,0x00,0x00]
 0x05,0x00,0x41,0xd1,0xf0,0x00,0x00,0x00
 
 # CHECK: v_mov_b32_e64 v5, -4.0                  ; encoding: [0x05,0x00,0x41,0xd1,0xf7,0x00,0x00,0x00]
 0x05,0x00,0x41,0xd1,0xf7,0x00,0x00,0x00
 
+# CHECK: v_mov_b32_e64 v5, -v2                   ; encoding: [0x05,0x00,0x41,0xd1,0x02,0x01,0x00,0x20]
+0x05,0x00,0x41,0xd1,0x02,0x01,0x00,0x20
+
+# CHECK: v_mov_b32_e64 v5, |v2|                  ; encoding: [0x05,0x01,0x41,0xd1,0x02,0x01,0x00,0x00]
+0x05,0x01,0x41,0xd1,0x02,0x01,0x00,0x00
+
+# CHECK: v_mov_b32_e64 v5, -v2 clamp             ; encoding: [0x05,0x80,0x41,0xd1,0x02,0x01,0x00,0x20]
+0x05,0x80,0x41,0xd1,0x02,0x01,0x00,0x20
+
+# CHECK: v_mov_b32_e64 v5, |v2| clamp            ; encoding: [0x05,0x81,0x41,0xd1,0x02,0x01,0x00,0x00]
+0x05,0x81,0x41,0xd1,0x02,0x01,0x00,0x00
+
 # CHECK: v_cvt_i32_f64_e64 v5, v[1:2]            ; encoding: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
 0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00
 
 # CHECK: v_cvt_i32_f64_e64 v255, v[1:2]          ; encoding: [0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
 0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00
 
 # CHECK: v_cvt_i32_f64_e64 v5, v[254:255]        ; encoding: [0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00]
 0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00