AMDGPU: Override getNegatedExpression constant handling

[arsenm]

Summary

Ignore the multiple use heuristics of the default
implementation, and report cost based on inline immediates. This
is mostly interesting for -0 vs. 0. Gets a few small improvements.
fneg_fadd_0_f16 is a small regression. We could probably avoid this
if we handled folding fneg into div_fixup.

[arsenm]

11c3cead23783e65fb30e673d62771352078ff05

[foad]

Heads up, this is causing an infinite loop in the DAG combiner. I'm working on reducing a test case.

[foad]

llc -march=amdgcn -mcpu=gfx1030 hangs on this test case:

define float @f(float %arg) {
bb:
  %i = fmul float %arg, 0.0
  %i1 = fsub float 0.0, %i
  ret float %i1
}

Could you please fix or revert?

[foad]

An excerpt from the infinite debug output:

Combining: t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $vgpr0, t3103

Combining: t3103: f32 = fsub # D:1 ConstantFP:f32<0.000000e+00>, t3102
Creating fp constant: t3104: f32 = ConstantFP<-0.000000e+00>
Creating new node: t3105: f32 = fmul # D:1 t2, ConstantFP:f32<-0.000000e+00>
Creating new node: t3106: f32 = fadd # D:1 t3105, ConstantFP:f32<0.000000e+00>
 ... into: t3106: f32 = fadd # D:1 t3105, ConstantFP:f32<0.000000e+00>

Combining: t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $vgpr0, t3106

Combining: t3106: f32 = fadd # D:1 t3105, ConstantFP:f32<0.000000e+00>
Creating new node: t3107: f32 = fmul # D:1 t2, ConstantFP:f32<0.000000e+00>
Creating new node: t3108: f32 = fsub # D:1 ConstantFP:f32<0.000000e+00>, t3107
 ... into: t3108: f32 = fsub # D:1 ConstantFP:f32<0.000000e+00>, t3107

[foad]

In D143963#4131640, @foad wrote:

llc -march=amdgcn -mcpu=gfx1030 hangs on this test case:

define float @f(float %arg) {
bb:
  %i = fmul float %arg, 0.0
  %i1 = fsub float 0.0, %i
  ret float %i1
}

Could you please fix or revert?

I've reverted the patch and added this test case to test/CodeGen/AMDGPU/fneg-combines.new.ll

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const {
   return false;
 }
 
 SDValue AMDGPUTargetLowering::getNegatedExpression(
     SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize,
     NegatibleCost &Cost, unsigned Depth) const {
 
   switch (Op.getOpcode()) {
+  case ISD::ConstantFP: {
+    auto *C = cast<ConstantFPSDNode>(Op);
+    Cost = getConstantNegateCost(C);
+    APFloat V = C->getValueAPF();
+    V.changeSign();
+    return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
+  }
   case ISD::FMA:
   case ISD::FMAD: {
     // Negating a fma is not free if it has users without source mods.
     if (!allUsesHaveSourceMods(Op.getNode()))
       return SDValue();
     break;
   }
   case AMDGPUISD::RCP: {

llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll

 define amdgpu_kernel void @div_v4_c_by_x_25ulp(ptr addrspace(1) %arg) {
   %load = load <4 x float>, ptr addrspace(1) %arg, align 16
   %div = fdiv <4 x float> <float 2.000000e+00, float 1.000000e+00, float -1.000000e+00, float -2.000000e+00>, %load, !fpmath !0
   store <4 x float> %div, ptr addrspace(1) %arg, align 16
   ret void
 }
 
 ; GCN-LABEL: {{^}}div_v4_c_by_minus_x_25ulp:
-; GCN-DENORM-DAG: v_div_scale_f32 {{.*}}, -2.0{{$}}
-; GCN-DENORM-DAG: v_div_scale_f32 {{.*}}, -2.0{{$}}
-; GCN-DENORM-DAG: v_div_scale_f32 {{.*}}, -2.0{{$}}
-; GCN-DENORM-DAG: v_div_scale_f32 {{.*}}, -2.0{{$}}
+; GCN-DENORM-DAG: v_div_scale_f32 {{.*}}, s{{[0-9]+}}, s{{[0-9]+}}, -2.0{{$}}
+; GCN-DENORM-DAG: v_div_scale_f32 {{.*}}, s{{[0-9]+}}, s{{[0-9]+}}, 2.0{{$}}
+; GCN-DENORM-DAG: v_div_scale_f32 {{.*}}, -2.0, s{{[0-9]+}}, -2.0{{$}}
+; GCN-DENORM-DAG: v_div_scale_f32 {{.*}}, 2.0, s{{[0-9]+}}, 2.0{{$}}
 ; GCN-DENORM-DAG: v_rcp_f32_e32
 ; GCN-DENORM-DAG: v_rcp_f32_e32
 
 ; GCN-DAG:        v_mov_b32_e32 [[L:v[0-9]+]], 0x6f800000
 ; GCN-DAG:        v_mov_b32_e32 [[S:v[0-9]+]], 0x2f800000
 
 ; GCN-DAG:        v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
 ; GCN-DAG:        v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
 ; GCN-DAG:        v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
 ; GCN-DAG:        v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
 
 ; GCN-DENORM-DAG: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; GCN-DENORM-DAG: v_mul_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}, v{{[0-9]+}}
 ; GCN-DENORM-DAG: v_rcp_f32_e32 [[RCP1:v[0-9]+]], v{{[0-9]+}}
 ; GCN-DENORM-DAG: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[RCP1]]
 ; GCN-DENORM-DAG: v_rcp_f32_e32 [[RCP2:v[0-9]+]], v{{[0-9]+}}
 ; GCN-DENORM-DAG: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[RCP2]]
 
 ; GCN-DENORM-DAG: v_div_fmas_f32
 ; GCN-DENORM-DAG: v_div_fmas_f32
 ; GCN-DENORM-DAG: v_div_fixup_f32 {{.*}}, -2.0{{$}}
-; GCN-DENORM-DAG: v_div_fixup_f32 {{.*}}, -2.0{{$}}
+; GCN-DENORM-DAG: v_div_fixup_f32 {{.*}}, 2.0{{$}}
 
 ; GCN-FLUSH-DAG:  v_rcp_f32_e32
 ; GCN-FLUSH-DAG:  v_rcp_f32_e64
 
 ; GCN-NOT:        v_cmp_gt_f32_e64
 ; GCN-NOT:        v_cndmask_b32_e32
 ; GCN-FLUSH-NOT:  v_div
 

llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll

 ;
 ; SI-NSZ-LABEL: fneg_fadd_0_f16:
 ; SI-NSZ:       ; %bb.0: ; %.entry
 ; SI-NSZ-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, s1
 ; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, s0
 ; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; SI-NSZ-NEXT:    v_div_scale_f32 v2, s[0:1], v0, v0, 1.0
+; SI-NSZ-NEXT:    v_div_scale_f32 v2, s[0:1], v0, v0, -1.0
 ; SI-NSZ-NEXT:    v_rcp_f32_e32 v3, v2
-; SI-NSZ-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
+; SI-NSZ-NEXT:    v_div_scale_f32 v4, vcc, -1.0, v0, -1.0
 ; SI-NSZ-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; SI-NSZ-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
 ; SI-NSZ-NEXT:    v_fma_f32 v3, v5, v3, v3
 ; SI-NSZ-NEXT:    v_mul_f32_e32 v5, v4, v3
 ; SI-NSZ-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; SI-NSZ-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; SI-NSZ-NEXT:    v_fma_f32 v2, -v2, v5, v4
 ; SI-NSZ-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; SI-NSZ-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; SI-NSZ-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
-; SI-NSZ-NEXT:    v_mul_f32_e32 v0, 0x80000000, v0
+; SI-NSZ-NEXT:    v_div_fixup_f32 v0, v2, v0, -1.0
+; SI-NSZ-NEXT:    v_mul_f32_e32 v0, 0, v0
 ; SI-NSZ-NEXT:    v_cmp_nlt_f32_e64 vcc, -v0, v1
 ; SI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-NSZ-NEXT:    v_mov_b32_e32 v1, 0x7fc00000
 ; SI-NSZ-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0
 ; SI-NSZ-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; SI-NSZ-NEXT:    ; return to shader part epilog
 ;
 ; VI-SAFE-LABEL: fneg_fadd_0_f16:

 ; VI-SAFE-NEXT:    ; return to shader part epilog
 ;
 ; VI-NSZ-LABEL: fneg_fadd_0_f16:
 ; VI-NSZ:       ; %bb.0: ; %.entry
 ; VI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, s1
 ; VI-NSZ-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NSZ-NEXT:    v_mov_b32_e32 v1, 0x7e00
 ; VI-NSZ-NEXT:    v_rcp_f32_e32 v0, v0
+; VI-NSZ-NEXT:    v_sub_f32_e32 v0, 0x80000000, v0
 ; VI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; VI-NSZ-NEXT:    v_div_fixup_f16 v0, v0, s1, 1.0
-; VI-NSZ-NEXT:    v_mul_f16_e32 v0, 0x8000, v0
+; VI-NSZ-NEXT:    v_div_fixup_f16 v0, v0, s1, -1.0
+; VI-NSZ-NEXT:    v_mul_f16_e32 v0, 0, v0
 ; VI-NSZ-NEXT:    v_cmp_nlt_f16_e64 vcc, -v0, s0
 ; VI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; VI-NSZ-NEXT:    v_cmp_nlt_f16_e32 vcc, 0, v0
 ; VI-NSZ-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; VI-NSZ-NEXT:    ; return to shader part epilog
 ;
 ; GFX11-SAFE-LABEL: fneg_fadd_0_f16:
 ; GFX11-SAFE:       ; %bb.0: ; %.entry

 ; GFX11-SAFE-NEXT:    ; return to shader part epilog
 ;
 ; GFX11-NSZ-LABEL: fneg_fadd_0_f16:
 ; GFX11-NSZ:       ; %bb.0: ; %.entry
 ; GFX11-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, s1
 ; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
 ; GFX11-NSZ-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX11-NSZ-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NSZ-NEXT:    v_sub_f32_e32 v0, 0x80000000, v0
 ; GFX11-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-NSZ-NEXT:    v_div_fixup_f16 v0, v0, s1, 1.0
 ; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NSZ-NEXT:    v_mul_f16_e32 v0, 0x8000, v0
-; GFX11-NSZ-NEXT:    v_cmp_nlt_f16_e64 s1, -v0, s0
+; GFX11-NSZ-NEXT:    v_div_fixup_f16 v0, v0, s1, -1.0
+; GFX11-NSZ-NEXT:    v_mul_f16_e32 v0, 0, v0
 ; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NSZ-NEXT:    v_cmp_nlt_f16_e64 s1, -v0, s0
 ; GFX11-NSZ-NEXT:    v_cndmask_b32_e64 v0, v0, s0, s1
+; GFX11-NSZ-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NSZ-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, 0, v0
 ; GFX11-NSZ-NEXT:    v_cndmask_b32_e64 v0, 0x7e00, 0, vcc_lo
 ; GFX11-NSZ-NEXT:    ; return to shader part epilog
 .entry:
   %tmp7 = fdiv half 1.000000e+00, %tmp6
   %tmp8 = fmul half 0.000000e+00, %tmp7
   %tmp9 = fmul reassoc nnan arcp contract half 0.000000e+00, %tmp8
   %.i188 = fadd half %tmp9, 0.000000e+00

 ; SI-SAFE-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; SI-SAFE-NEXT:    ; return to shader part epilog
 ;
 ; SI-NSZ-LABEL: fneg_fadd_0_nsz_f16:
 ; SI-NSZ:       ; %bb.0: ; %.entry
 ; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v0, s1
 ; SI-NSZ-NEXT:    v_cvt_f16_f32_e32 v1, s0
 ; SI-NSZ-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
-; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-NSZ-NEXT:    v_cvt_f32_f16_e64 v0, -v0
 ; SI-NSZ-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-NSZ-NEXT:    v_rcp_f32_e32 v0, v0
-; SI-NSZ-NEXT:    v_mul_f32_e32 v0, 0x80000000, v0
+; SI-NSZ-NEXT:    v_mul_f32_e32 v0, 0, v0
 ; SI-NSZ-NEXT:    v_cmp_nlt_f32_e64 vcc, -v0, v1
 ; SI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-NSZ-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0
 ; SI-NSZ-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
 ; SI-NSZ-NEXT:    ; return to shader part epilog
 ;
 ; VI-SAFE-LABEL: fneg_fadd_0_nsz_f16:
 ; VI-SAFE:       ; %bb.0: ; %.entry

llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll

 ; SI-SAFE-NEXT:    v_cndmask_b32_e64 v0, -v0, v1, vcc
 ; SI-SAFE-NEXT:    v_mov_b32_e32 v1, 0x7fc00000
 ; SI-SAFE-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0
 ; SI-SAFE-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; SI-SAFE-NEXT:    ; return to shader part epilog
 ;
 ; SI-NSZ-LABEL: fneg_fadd_0_f32:
 ; SI-NSZ:       ; %bb.0: ; %.entry
-; SI-NSZ-NEXT:    v_div_scale_f32 v0, s[2:3], s1, s1, 1.0
+; SI-NSZ-NEXT:    v_div_scale_f32 v0, s[2:3], s1, s1, -1.0
 ; SI-NSZ-NEXT:    v_rcp_f32_e32 v1, v0
-; SI-NSZ-NEXT:    v_div_scale_f32 v2, vcc, 1.0, s1, 1.0
+; SI-NSZ-NEXT:    v_div_scale_f32 v2, vcc, -1.0, s1, -1.0
 ; SI-NSZ-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; SI-NSZ-NEXT:    v_fma_f32 v3, -v0, v1, 1.0
 ; SI-NSZ-NEXT:    v_fma_f32 v1, v3, v1, v1
 ; SI-NSZ-NEXT:    v_mul_f32_e32 v3, v2, v1
 ; SI-NSZ-NEXT:    v_fma_f32 v4, -v0, v3, v2
 ; SI-NSZ-NEXT:    v_fma_f32 v3, v4, v1, v3
 ; SI-NSZ-NEXT:    v_fma_f32 v0, -v0, v3, v2
 ; SI-NSZ-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; SI-NSZ-NEXT:    v_div_fmas_f32 v0, v0, v1, v3
-; SI-NSZ-NEXT:    v_div_fixup_f32 v0, v0, s1, 1.0
-; SI-NSZ-NEXT:    v_mul_f32_e32 v0, 0x80000000, v0
+; SI-NSZ-NEXT:    v_div_fixup_f32 v0, v0, s1, -1.0
+; SI-NSZ-NEXT:    v_mul_f32_e32 v0, 0, v0
 ; SI-NSZ-NEXT:    v_mov_b32_e32 v1, s0
 ; SI-NSZ-NEXT:    v_cmp_nlt_f32_e64 vcc, -v0, s0
 ; SI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-NSZ-NEXT:    v_mov_b32_e32 v1, 0x7fc00000
 ; SI-NSZ-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0
 ; SI-NSZ-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; SI-NSZ-NEXT:    ; return to shader part epilog
 ;

 ; VI-SAFE-NEXT:    v_cmp_ngt_f32_e32 vcc, s0, v0
 ; VI-SAFE-NEXT:    v_cndmask_b32_e64 v0, -v0, v2, vcc
 ; VI-SAFE-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0
 ; VI-SAFE-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; VI-SAFE-NEXT:    ; return to shader part epilog
 ;
 ; VI-NSZ-LABEL: fneg_fadd_0_f32:
 ; VI-NSZ:       ; %bb.0: ; %.entry
-; VI-NSZ-NEXT:    v_div_scale_f32 v0, s[2:3], s1, s1, 1.0
-; VI-NSZ-NEXT:    v_div_scale_f32 v1, vcc, 1.0, s1, 1.0
+; VI-NSZ-NEXT:    v_div_scale_f32 v0, s[2:3], s1, s1, -1.0
+; VI-NSZ-NEXT:    v_div_scale_f32 v1, vcc, -1.0, s1, -1.0
 ; VI-NSZ-NEXT:    v_rcp_f32_e32 v2, v0
 ; VI-NSZ-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; VI-NSZ-NEXT:    v_fma_f32 v3, -v0, v2, 1.0
 ; VI-NSZ-NEXT:    v_fma_f32 v2, v3, v2, v2
 ; VI-NSZ-NEXT:    v_mul_f32_e32 v3, v1, v2
 ; VI-NSZ-NEXT:    v_fma_f32 v4, -v0, v3, v1
 ; VI-NSZ-NEXT:    v_fma_f32 v3, v4, v2, v3
 ; VI-NSZ-NEXT:    v_fma_f32 v0, -v0, v3, v1
 ; VI-NSZ-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; VI-NSZ-NEXT:    v_div_fmas_f32 v0, v0, v2, v3
 ; VI-NSZ-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NSZ-NEXT:    v_mov_b32_e32 v1, 0x7fc00000
-; VI-NSZ-NEXT:    v_div_fixup_f32 v0, v0, s1, 1.0
-; VI-NSZ-NEXT:    v_mul_f32_e32 v0, 0x80000000, v0
+; VI-NSZ-NEXT:    v_div_fixup_f32 v0, v0, s1, -1.0
+; VI-NSZ-NEXT:    v_mul_f32_e32 v0, 0, v0
 ; VI-NSZ-NEXT:    v_cmp_nlt_f32_e64 vcc, -v0, s0
 ; VI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; VI-NSZ-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v0
 ; VI-NSZ-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; VI-NSZ-NEXT:    ; return to shader part epilog
 .entry:
   %tmp7 = fdiv float 1.000000e+00, %tmp6
   %tmp8 = fmul float 0.000000e+00, %tmp7

 ; SI-SAFE-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc
 ; SI-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
 ; SI-SAFE-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
 ; SI-SAFE-NEXT:    s_and_b64 s[0:1], vcc, exec
 ; SI-SAFE-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000
 ; SI-SAFE-NEXT:    s_mov_b32 s0, 0
 ; SI-SAFE-NEXT:    ; return to shader part epilog
 ;
-; SI-NSZ-LABEL: fneg_fadd_0_f64:
-; SI-NSZ:       ; %bb.0: ; %.entry
-; SI-NSZ-NEXT:    v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
-; SI-NSZ-NEXT:    s_mov_b32 s4, 0
-; SI-NSZ-NEXT:    s_brev_b32 s5, 1
-; SI-NSZ-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
-; SI-NSZ-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; SI-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
-; SI-NSZ-NEXT:    v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
-; SI-NSZ-NEXT:    v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
-; SI-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; SI-NSZ-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
-; SI-NSZ-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
-; SI-NSZ-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
-; SI-NSZ-NEXT:    v_mov_b32_e32 v2, s1
-; SI-NSZ-NEXT:    v_mov_b32_e32 v3, s0
-; SI-NSZ-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; SI-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], s[4:5]
-; SI-NSZ-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
-; SI-NSZ-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; SI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; SI-NSZ-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; SI-NSZ-NEXT:    s_and_b64 s[0:1], vcc, exec
-; SI-NSZ-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000
-; SI-NSZ-NEXT:    s_mov_b32 s0, 0
-; SI-NSZ-NEXT:    ; return to shader part epilog
+; GCN-NSZ-LABEL: fneg_fadd_0_f64:
+; GCN-NSZ:       ; %bb.0: ; %.entry
+; GCN-NSZ-NEXT:    v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], -1.0
+; GCN-NSZ-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
+; GCN-NSZ-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
+; GCN-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
+; GCN-NSZ-NEXT:    v_div_scale_f64 v[4:5], vcc, -1.0, s[2:3], -1.0
+; GCN-NSZ-NEXT:    v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
+; GCN-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
+; GCN-NSZ-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
+; GCN-NSZ-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
+; GCN-NSZ-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
+; GCN-NSZ-NEXT:    v_mov_b32_e32 v2, s1
+; GCN-NSZ-NEXT:    v_mov_b32_e32 v3, s0
+; GCN-NSZ-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], -1.0
+; GCN-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], 0
+; GCN-NSZ-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
+; GCN-NSZ-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
+; GCN-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; GCN-NSZ-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
+; GCN-NSZ-NEXT:    s_and_b64 s[0:1], vcc, exec
+; GCN-NSZ-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000
+; GCN-NSZ-NEXT:    s_mov_b32 s0, 0
+; GCN-NSZ-NEXT:    ; return to shader part epilog
 ;
 ; VI-SAFE-LABEL: fneg_fadd_0_f64:
 ; VI-SAFE:       ; %bb.0: ; %.entry
 ; VI-SAFE-NEXT:    v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
 ; VI-SAFE-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
 ; VI-SAFE-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
 ; VI-SAFE-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
 ; VI-SAFE-NEXT:    v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0

 ; VI-SAFE-NEXT:    v_xor_b32_e32 v3, 0x80000000, v1
 ; VI-SAFE-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc
 ; VI-SAFE-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
 ; VI-SAFE-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
 ; VI-SAFE-NEXT:    s_and_b64 s[0:1], vcc, exec
 ; VI-SAFE-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000
 ; VI-SAFE-NEXT:    s_mov_b32 s0, 0
 ; VI-SAFE-NEXT:    ; return to shader part epilog
-;
-; VI-NSZ-LABEL: fneg_fadd_0_f64:
-; VI-NSZ:       ; %bb.0: ; %.entry
-; VI-NSZ-NEXT:    v_div_scale_f64 v[0:1], s[4:5], s[2:3], s[2:3], 1.0
-; VI-NSZ-NEXT:    v_rcp_f64_e32 v[2:3], v[0:1]
-; VI-NSZ-NEXT:    v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
-; VI-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[4:5], v[2:3]
-; VI-NSZ-NEXT:    v_div_scale_f64 v[4:5], vcc, 1.0, s[2:3], 1.0
-; VI-NSZ-NEXT:    v_fma_f64 v[6:7], -v[0:1], v[2:3], 1.0
-; VI-NSZ-NEXT:    v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; VI-NSZ-NEXT:    v_mul_f64 v[6:7], v[4:5], v[2:3]
-; VI-NSZ-NEXT:    v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
-; VI-NSZ-NEXT:    v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[6:7]
-; VI-NSZ-NEXT:    v_mov_b32_e32 v2, s1
-; VI-NSZ-NEXT:    v_mov_b32_e32 v3, s0
-; VI-NSZ-NEXT:    v_div_fixup_f64 v[0:1], v[0:1], s[2:3], 1.0
-; VI-NSZ-NEXT:    s_mov_b32 s2, 0
-; VI-NSZ-NEXT:    s_brev_b32 s3, 1
-; VI-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], s[2:3]
-; VI-NSZ-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
-; VI-NSZ-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; VI-NSZ-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; VI-NSZ-NEXT:    s_and_b64 s[0:1], vcc, exec
-; VI-NSZ-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000
-; VI-NSZ-NEXT:    s_mov_b32 s0, 0
-; VI-NSZ-NEXT:    ; return to shader part epilog
 .entry:
   %tmp7 = fdiv double 1.000000e+00, %tmp6
   %tmp8 = fmul double 0.000000e+00, %tmp7
   %tmp9 = fmul reassoc nnan arcp contract double 0.000000e+00, %tmp8
   %.i188 = fadd double %tmp9, 0.000000e+00
   %tmp10 = fcmp uge double %.i188, %tmp2
   %tmp11 = fneg double %.i188
   %.i092 = select i1 %tmp10, double %tmp2, double %tmp11

 ;
 ; SI-NSZ-LABEL: fneg_fadd_0_nsz_f64:
 ; SI-NSZ:       ; %bb.0: ; %.entry
 ; SI-NSZ-NEXT:    v_rcp_f64_e32 v[0:1], s[2:3]
 ; SI-NSZ-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
 ; SI-NSZ-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
 ; SI-NSZ-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
 ; SI-NSZ-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
-; SI-NSZ-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
-; SI-NSZ-NEXT:    s_mov_b32 s2, 0
-; SI-NSZ-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
-; SI-NSZ-NEXT:    s_brev_b32 s3, 1
-; SI-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], s[2:3]
+; SI-NSZ-NEXT:    v_mul_f64 v[2:3], v[0:1], -1.0
+; SI-NSZ-NEXT:    v_fma_f64 v[4:5], -s[2:3], v[2:3], -1.0
+; SI-NSZ-NEXT:    v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
 ; SI-NSZ-NEXT:    v_mov_b32_e32 v2, s1
-; SI-NSZ-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
+; SI-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], 0
 ; SI-NSZ-NEXT:    v_mov_b32_e32 v3, s0
+; SI-NSZ-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
 ; SI-NSZ-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; SI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
 ; SI-NSZ-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
 ; SI-NSZ-NEXT:    s_and_b64 s[0:1], vcc, exec
 ; SI-NSZ-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000
 ; SI-NSZ-NEXT:    s_mov_b32 s0, 0
 ; SI-NSZ-NEXT:    ; return to shader part epilog
 ;
 ; VI-NSZ-LABEL: fneg_fadd_0_nsz_f64:
 ; VI-NSZ:       ; %bb.0: ; %.entry
 ; VI-NSZ-NEXT:    v_rcp_f64_e32 v[0:1], s[2:3]
 ; VI-NSZ-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
 ; VI-NSZ-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
 ; VI-NSZ-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
 ; VI-NSZ-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
-; VI-NSZ-NEXT:    v_fma_f64 v[2:3], -s[2:3], v[0:1], 1.0
-; VI-NSZ-NEXT:    s_mov_b32 s2, 0
-; VI-NSZ-NEXT:    s_brev_b32 s3, 1
-; VI-NSZ-NEXT:    v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1]
+; VI-NSZ-NEXT:    v_mul_f64 v[2:3], v[0:1], -1.0
+; VI-NSZ-NEXT:    v_fma_f64 v[4:5], -s[2:3], v[2:3], -1.0
+; VI-NSZ-NEXT:    v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]
 ; VI-NSZ-NEXT:    v_mov_b32_e32 v2, s1
 ; VI-NSZ-NEXT:    v_mov_b32_e32 v3, s0
-; VI-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], s[2:3]
+; VI-NSZ-NEXT:    v_mul_f64 v[0:1], v[0:1], 0
 ; VI-NSZ-NEXT:    v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
 ; VI-NSZ-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; VI-NSZ-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
 ; VI-NSZ-NEXT:    v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
 ; VI-NSZ-NEXT:    s_and_b64 s[0:1], vcc, exec
 ; VI-NSZ-NEXT:    s_cselect_b32 s1, 0, 0x7ff80000
 ; VI-NSZ-NEXT:    s_mov_b32 s0, 0
 ; VI-NSZ-NEXT:    ; return to shader part epilog

llvm/test/CodeGen/AMDGPU/v_pack.ll

 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    global_load_ushort v1, v0, s[0:1] glc dlc
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    global_load_ushort v2, v0, s[2:3] glc dlc
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_subrev_f16_e32 v0, 2.0, v1
+; GCN-NEXT:    v_add_f16_e32 v0, -2.0, v1
 ; GCN-NEXT:    v_add_f16_e32 v1, 2.0, v2
 ; GCN-NEXT:    v_pack_b32_f16 v0, v0, v1
 ; GCN-NEXT:    ;;#ASMSTART
 ; GCN-NEXT:    ; use v0
 ; GCN-NEXT:    ;;#ASMEND
 ; GCN-NEXT:    s_endpgm
 ;
 ; GISEL-LABEL: v_pack_b32_v2f16_sub: