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Differential D143790

[RISCV] Make vsetvli intrinsics default to MA.
ClosedPublic

Authored by craig.topper on Feb 10 2023, 3:40 PM.

Details

Reviewers
reames
frasercrmck
eopXD
kito-cheng
rogfer01
Commits
rG7638409d4363: [RISCV] Make vsetvli intrinsics default to MA.
Summary

The vsetvli insertion pass can replace it with MU if needed by
a using instruction. The vsetvli insertion pass will not convert
MU to MA so we need to start at MA.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 10 2023, 3:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 10 2023, 3:40 PM
Herald added subscribers: luke, VincentWu, vkmr and 25 others. · View Herald Transcript
craig.topper requested review of this revision.Feb 10 2023, 3:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 10 2023, 3:40 PM
Herald added subscribers: • pcwang-thead, MaskRay. · View Herald Transcript
eopXD accepted this revision.Feb 11 2023, 6:18 AM

This change looks reasonable to me.

This revision is now accepted and ready to land.Feb 11 2023, 6:18 AM
This revision was landed with ongoing or failed builds.Feb 13 2023, 10:40 AM
Closed by commit rG7638409d4363: [RISCV] Make vsetvli intrinsics default to MA. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG7638409d4363: [RISCV] Make vsetvli intrinsics default to MA..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
test/
CodeGen/
RISCV/
rvv/
10 lines
2 lines
4 lines
6 lines
42 lines
44 lines
22 lines
36 lines
16 lines
36 lines
16 lines
Transforms/
LoopStrengthReduce/
RISCV/
4 lines

Diff 497044

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 547 Lines • ▼ Show 20 Lines assert(Node->getNumOperands() == Offset + 2 &&
"Unexpected number of operands"); "Unexpected number of operands");
unsigned SEW = unsigned SEW =
RISCVVType::decodeVSEW(Node->getConstantOperandVal(Offset) & 0x7); RISCVVType::decodeVSEW(Node->getConstantOperandVal(Offset) & 0x7);
RISCVII::VLMUL VLMul = static_cast<RISCVII::VLMUL>( RISCVII::VLMUL VLMul = static_cast<RISCVII::VLMUL>(
Node->getConstantOperandVal(Offset + 1) & 0x7); Node->getConstantOperandVal(Offset + 1) & 0x7);
unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, SEW, /*TailAgnostic*/ true, unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, SEW, /*TailAgnostic*/ true,
/*MaskAgnostic*/ false); /*MaskAgnostic*/ true);
SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT); SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT);
SmallVector<EVT, 2> VTs = {XLenVT}; SmallVector<EVT, 2> VTs = {XLenVT};
SDValue VLOperand; SDValue VLOperand;
unsigned Opcode = RISCV::PseudoVSETVLI; unsigned Opcode = RISCV::PseudoVSETVLI;
if (VLMax) { if (VLMax) {
VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT); VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);
▲ Show 20 Lines • Show All 2,439 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tumu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tumu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_tumu_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_tumu_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma
; CHECK-NEXT: vslide1down.vx v9, v9, a0 ; CHECK-NEXT: vslide1down.vx v9, v9, a0
; CHECK-NEXT: vslide1down.vx v9, v9, a1 ; CHECK-NEXT: vslide1down.vx v9, v9, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tamu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tamu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_tamu_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_tamu_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma
; CHECK-NEXT: vslide1down.vx v9, v9, a0 ; CHECK-NEXT: vslide1down.vx v9, v9, a0
; CHECK-NEXT: vslide1down.vx v9, v9, a1 ; CHECK-NEXT: vslide1down.vx v9, v9, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
; Fallback vslide1 to mask undisturbed until InsertVSETVLI supports mask agnostic. ; Fallback vslide1 to mask undisturbed until InsertVSETVLI supports mask agnostic.
define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_tuma_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma
; CHECK-NEXT: vslide1down.vx v9, v9, a0 ; CHECK-NEXT: vslide1down.vx v9, v9, a0
; CHECK-NEXT: vslide1down.vx v9, v9, a1 ; CHECK-NEXT: vslide1down.vx v9, v9, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4, i32 2) i32 %4, i32 2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
; Fallback vslide1 to mask undisturbed until InsertVSETVLI supports mask agnostic. ; Fallback vslide1 to mask undisturbed until InsertVSETVLI supports mask agnostic.
define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_tama_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 3) i32 %3, i32 3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tama_undef_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_mask_tama_undef_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_tama_undef_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_tama_undef_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
<vscale x 1 x i1> undef, <vscale x 1 x i1> undef,
i32 %2, i32 3) i32 %2, i32 3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 112 ; CHECK-NEXT: addi s0, sp, 112
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: sw zero, -36(s0) ; CHECK-NEXT: sw zero, -36(s0)
; CHECK-NEXT: sd zero, -48(s0) ; CHECK-NEXT: sd zero, -48(s0)
; CHECK-NEXT: sd zero, -56(s0) ; CHECK-NEXT: sd zero, -56(s0)
; CHECK-NEXT: vsetivli a0, 4, e32, m8, ta, mu ; CHECK-NEXT: vsetivli a0, 4, e32, m8, ta, ma
; CHECK-NEXT: sd a0, -64(s0) ; CHECK-NEXT: sd a0, -64(s0)
; CHECK-NEXT: ld a0, -64(s0) ; CHECK-NEXT: ld a0, -64(s0)
; CHECK-NEXT: addi a1, s0, -56 ; CHECK-NEXT: addi a1, s0, -56
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: csrr s1, vlenb ; CHECK-NEXT: csrr s1, vlenb
; CHECK-NEXT: slli s1, s1, 3 ; CHECK-NEXT: slli s1, s1, 3
; CHECK-NEXT: sub s1, s0, s1 ; CHECK-NEXT: sub s1, s0, s1
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll

Show First 20 Lines • Show All 699 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli a2, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli a2, a2, e64, m1, ta, ma
; RV32-NEXT: slli a2, a2, 1 ; RV32-NEXT: slli a2, a2, 1
; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, ma ; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, ma
; RV32-NEXT: vmv1r.v v10, v8 ; RV32-NEXT: vmv1r.v v10, v8
; RV32-NEXT: vslide1down.vx v10, v9, a0 ; RV32-NEXT: vslide1down.vx v10, v9, a0
; RV32-NEXT: vslide1down.vx v8, v10, a1 ; RV32-NEXT: vslide1down.vx v8, v10, a1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:
Show All 15 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli a2, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli a2, a2, e64, m1, ta, ma
; RV32-NEXT: slli a2, a2, 1 ; RV32-NEXT: slli a2, a2, 1
; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, ma ; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, ma
; RV32-NEXT: vmv1r.v v10, v8 ; RV32-NEXT: vmv1r.v v10, v8
; RV32-NEXT: vslide1up.vx v10, v9, a1 ; RV32-NEXT: vslide1up.vx v10, v9, a1
; RV32-NEXT: vslide1up.vx v8, v10, a0 ; RV32-NEXT: vslide1up.vx v8, v10, a0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:
▲ Show 20 Lines • Show All 1,951 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
declare i64 @llvm.riscv.vsetvli( declare i64 @llvm.riscv.vsetvli(
i64, i64, i64); i64, i64, i64);
define signext i32 @vsetvl_sext() { define signext i32 @vsetvl_sext() {
; CHECK-LABEL: vsetvl_sext: ; CHECK-LABEL: vsetvl_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, mu ; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1) %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)
%b = trunc i64 %a to i32 %b = trunc i64 %a to i32
ret i32 %b ret i32 %b
} }
define zeroext i32 @vsetvl_zext() { define zeroext i32 @vsetvl_zext() {
; CHECK-LABEL: vsetvl_zext: ; CHECK-LABEL: vsetvl_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, mu ; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1) %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)
%b = trunc i64 %a to i32 %b = trunc i64 %a to i32
ret i32 %b ret i32 %b
} }
define i64 @vsetvl_and17bits() { define i64 @vsetvl_and17bits() {
; CHECK-LABEL: vsetvl_and17bits: ; CHECK-LABEL: vsetvl_and17bits:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, mu ; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1) %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)
%b = and i64 %a, 131071 %b = and i64 %a, 131071
ret i64 %b ret i64 %b
} }

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

Show All 17 Lines
declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32( <vscale x 2 x float>, float, i64) declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32( <vscale x 2 x float>, float, i64)
declare void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64) declare void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64)
declare void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>* nocapture, i64) declare void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>* nocapture, i64)
define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: beqz a1, .LBB0_2 ; CHECK-NEXT: beqz a1, .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: # %if.else ; CHECK-NEXT: .LBB0_2: # %if.else
; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 14 Linesif.end: ; preds = %if.else, %if.then
ret <vscale x 1 x double> %c.0 ret <vscale x 1 x double> %c.0
} }
@scratch = global i8 0, align 16 @scratch = global i8 0, align 16
define <vscale x 1 x double> @test2(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test2(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: beqz a1, .LBB1_2 ; CHECK-NEXT: beqz a1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vfadd.vv v9, v8, v9 ; CHECK-NEXT: vfadd.vv v9, v8, v9
; CHECK-NEXT: vfmul.vv v8, v9, v8 ; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: # %if.else ; CHECK-NEXT: .LBB1_2: # %if.else
; CHECK-NEXT: vfsub.vv v9, v8, v9 ; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: vfmul.vv v8, v9, v8 ; CHECK-NEXT: vfmul.vv v8, v9, v8
Show All 17 Linesif.end: ; preds = %if.else, %if.then
ret <vscale x 1 x double> %3 ret <vscale x 1 x double> %3
} }
define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: beqz a1, .LBB2_2 ; CHECK-NEXT: beqz a1, .LBB2_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v9, v8, v9 ; CHECK-NEXT: vfadd.vv v9, v8, v9
; CHECK-NEXT: j .LBB2_3 ; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: # %if.else ; CHECK-NEXT: .LBB2_2: # %if.else
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, ma
; CHECK-NEXT: vfsub.vv v9, v8, v9 ; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: .LBB2_3: # %if.end
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vfmul.vv v8, v9, v8 ; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%tobool = icmp eq i8 %cond, 0 %tobool = icmp eq i8 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0) %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesif.end: ; preds = %if.else, %if.then
%8 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %l, <vscale x 1 x double> %r, i64 %avl) %8 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %l, <vscale x 1 x double> %r, i64 %avl)
ret <vscale x 1 x double> %8 ret <vscale x 1 x double> %8
} }
define <vscale x 1 x double> @test5(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test5(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a2, a1, 1 ; CHECK-NEXT: andi a2, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: bnez a2, .LBB4_3 ; CHECK-NEXT: bnez a2, .LBB4_3
; CHECK-NEXT: # %bb.1: # %if.else ; CHECK-NEXT: # %bb.1: # %if.else
; CHECK-NEXT: vfsub.vv v9, v8, v9 ; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: andi a1, a1, 2 ; CHECK-NEXT: andi a1, a1, 2
; CHECK-NEXT: beqz a1, .LBB4_4 ; CHECK-NEXT: beqz a1, .LBB4_4
; CHECK-NEXT: .LBB4_2: # %if.then4 ; CHECK-NEXT: .LBB4_2: # %if.then4
; CHECK-NEXT: vfmul.vv v8, v9, v8 ; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Show All 40 Lines
; FIXME: The explicit vsetvli in if.then4 could be removed as it is redundant ; FIXME: The explicit vsetvli in if.then4 could be removed as it is redundant
; with the one in the entry, but we lack the ability to remove explicit ; with the one in the entry, but we lack the ability to remove explicit
; vsetvli instructions. ; vsetvli instructions.
define <vscale x 1 x double> @test6(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test6(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a3, a1, 1 ; CHECK-NEXT: andi a3, a1, 1
; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, ma
; CHECK-NEXT: bnez a3, .LBB5_3 ; CHECK-NEXT: bnez a3, .LBB5_3
; CHECK-NEXT: # %bb.1: # %if.else ; CHECK-NEXT: # %bb.1: # %if.else
; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: andi a1, a1, 2 ; CHECK-NEXT: andi a1, a1, 2
; CHECK-NEXT: beqz a1, .LBB5_4 ; CHECK-NEXT: beqz a1, .LBB5_4
; CHECK-NEXT: .LBB5_2: # %if.then4 ; CHECK-NEXT: .LBB5_2: # %if.then4
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: lui a0, %hi(.LCPI5_1) ; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_1) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_1)
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vfadd.vv v9, v9, v10 ; CHECK-NEXT: vfadd.vv v9, v9, v10
; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: lui a0, %hi(scratch)
; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch)
; CHECK-NEXT: vse64.v v9, (a0) ; CHECK-NEXT: vse64.v v9, (a0)
; CHECK-NEXT: j .LBB5_5 ; CHECK-NEXT: j .LBB5_5
; CHECK-NEXT: .LBB5_3: # %if.then ; CHECK-NEXT: .LBB5_3: # %if.then
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: andi a1, a1, 2 ; CHECK-NEXT: andi a1, a1, 2
; CHECK-NEXT: bnez a1, .LBB5_2 ; CHECK-NEXT: bnez a1, .LBB5_2
; CHECK-NEXT: .LBB5_4: # %if.else5 ; CHECK-NEXT: .LBB5_4: # %if.else5
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: lui a0, 260096 ; CHECK-NEXT: lui a0, 260096
; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: lui a0, 262144 ; CHECK-NEXT: lui a0, 262144
; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vfadd.vv v9, v9, v10 ; CHECK-NEXT: vfadd.vv v9, v9, v10
; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: lui a0, %hi(scratch)
; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch)
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test8: ; CHECK-LABEL: test8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, ma
; CHECK-NEXT: beqz a1, .LBB6_2 ; CHECK-NEXT: beqz a1, .LBB6_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: j .LBB6_3 ; CHECK-NEXT: j .LBB6_3
; CHECK-NEXT: .LBB6_2: # %if.else ; CHECK-NEXT: .LBB6_2: # %if.else
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp ; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test9: ; CHECK-LABEL: test9:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, ma
; CHECK-NEXT: beqz a1, .LBB7_2 ; CHECK-NEXT: beqz a1, .LBB7_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: vfadd.vv v9, v8, v9 ; CHECK-NEXT: vfadd.vv v9, v8, v9
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a0, a0, sp ; CHECK-NEXT: add a0, a0, sp
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
Show All 36 Linesif.end: ; preds = %if.else, %if.then
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ] %c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
%3 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %c.0, <vscale x 1 x double> %a, i64 %0) %3 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %c.0, <vscale x 1 x double> %a, i64 %0)
ret <vscale x 1 x double> %3 ret <vscale x 1 x double> %3
} }
define void @saxpy_vec(i64 %n, float %a, float* nocapture readonly %x, float* nocapture %y) { define void @saxpy_vec(i64 %n, float %a, float* nocapture readonly %x, float* nocapture %y) {
; CHECK-LABEL: saxpy_vec: ; CHECK-LABEL: saxpy_vec:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a3, a0, e32, m8, ta, ma
; CHECK-NEXT: beqz a3, .LBB8_2 ; CHECK-NEXT: beqz a3, .LBB8_2
; CHECK-NEXT: .LBB8_1: # %for.body ; CHECK-NEXT: .LBB8_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vle32.v v16, (a2) ; CHECK-NEXT: vle32.v v16, (a2)
; CHECK-NEXT: slli a4, a3, 2 ; CHECK-NEXT: slli a4, a3, 2
; CHECK-NEXT: add a1, a1, a4 ; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, ma
; CHECK-NEXT: vfmacc.vf v16, fa0, v8 ; CHECK-NEXT: vfmacc.vf v16, fa0, v8
; CHECK-NEXT: vse32.v v16, (a2) ; CHECK-NEXT: vse32.v v16, (a2)
; CHECK-NEXT: sub a0, a0, a3 ; CHECK-NEXT: sub a0, a0, a3
; CHECK-NEXT: vsetvli a3, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a3, a0, e32, m8, ta, ma
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: bnez a3, .LBB8_1 ; CHECK-NEXT: bnez a3, .LBB8_1
; CHECK-NEXT: .LBB8_2: # %for.end ; CHECK-NEXT: .LBB8_2: # %for.end
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 2, i64 3) %0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 2, i64 3)
%cmp.not13 = icmp eq i64 %0, 0 %cmp.not13 = icmp eq i64 %0, 0
br i1 %cmp.not13, label %for.end, label %for.body br i1 %cmp.not13, label %for.end, label %for.body
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Linesif2.end:
ret <vscale x 2 x i32> %h ret <vscale x 2 x i32> %h
} }
declare <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i16>, i64) declare <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i16>, i64)
; We should only need 1 vsetvli for this code. ; We should only need 1 vsetvli for this code.
define void @vlmax(i64 %N, double* %c, double* %a, double* %b) { define void @vlmax(i64 %N, double* %c, double* %a, double* %b) {
; CHECK-LABEL: vlmax: ; CHECK-LABEL: vlmax:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a6, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; CHECK-NEXT: blez a0, .LBB11_3 ; CHECK-NEXT: blez a0, .LBB11_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: slli a4, a6, 3 ; CHECK-NEXT: slli a4, a6, 3
; CHECK-NEXT: .LBB11_2: # %for.body ; CHECK-NEXT: .LBB11_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a2) ; CHECK-NEXT: vle64.v v8, (a2)
; CHECK-NEXT: vle64.v v9, (a3) ; CHECK-NEXT: vle64.v v9, (a3)
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: add a5, a5, a6 ; CHECK-NEXT: add a5, a5, a6
; CHECK-NEXT: add a1, a1, a4 ; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: add a3, a3, a4 ; CHECK-NEXT: add a3, a3, a4
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a2, a2, a4
Show All 24 Lines
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
; A single vector store in the loop with VL controlled by VLMAX ; A single vector store in the loop with VL controlled by VLMAX
define void @vector_init_vlmax(i64 %N, double* %c) { define void @vector_init_vlmax(i64 %N, double* %c) {
; CHECK-LABEL: vector_init_vlmax: ; CHECK-LABEL: vector_init_vlmax:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: blez a0, .LBB12_3 ; CHECK-NEXT: blez a0, .LBB12_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: slli a4, a2, 3 ; CHECK-NEXT: slli a4, a2, 3
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB12_2: # %for.body ; CHECK-NEXT: .LBB12_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: add a3, a3, a2 ; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: add a1, a1, a4 ; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: blt a3, a0, .LBB12_2 ; CHECK-NEXT: blt a3, a0, .LBB12_2
; CHECK-NEXT: .LBB12_3: # %for.end ; CHECK-NEXT: .LBB12_3: # %for.end
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) %0 = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
Show All 12 Lines
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
; Same as above, but VL comes from user provided AVL value ; Same as above, but VL comes from user provided AVL value
define void @vector_init_vsetvli_N(i64 %N, double* %c) { define void @vector_init_vsetvli_N(i64 %N, double* %c) {
; CHECK-LABEL: vector_init_vsetvli_N: ; CHECK-LABEL: vector_init_vsetvli_N:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, ma
; CHECK-NEXT: blez a0, .LBB13_3 ; CHECK-NEXT: blez a0, .LBB13_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: slli a4, a2, 3 ; CHECK-NEXT: slli a4, a2, 3
; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB13_2: # %for.body ; CHECK-NEXT: .LBB13_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
Show All 22 Linesfor.end: ; preds = %for.body, %entry
ret void ret void
} }
; Same as above, but VL is a hard coded constant (in the preheader) ; Same as above, but VL is a hard coded constant (in the preheader)
define void @vector_init_vsetvli_fv(i64 %N, double* %c) { define void @vector_init_vsetvli_fv(i64 %N, double* %c) {
; CHECK-LABEL: vector_init_vsetvli_fv: ; CHECK-LABEL: vector_init_vsetvli_fv:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: vsetivli a3, 4, e64, m1, ta, mu ; CHECK-NEXT: vsetivli a3, 4, e64, m1, ta, ma
; CHECK-NEXT: slli a4, a3, 3 ; CHECK-NEXT: slli a4, a3, 3
; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB14_1: # %for.body ; CHECK-NEXT: .LBB14_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: add a2, a2, a3 ; CHECK-NEXT: add a2, a2, a3
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines %res = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32> %b, <vscale x 4 x i1> %mask, i64 %vl, i64 0) <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask, i64 %vl, i64 0)
ret <vscale x 4 x i32> %res ret <vscale x 4 x i32> %res
} }
define <vscale x 2 x i32> @pre_lmul(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i1 %cond) nounwind { define <vscale x 2 x i32> @pre_lmul(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i1 %cond) nounwind {
; CHECK-LABEL: pre_lmul: ; CHECK-LABEL: pre_lmul:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) %vl = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 %vl) %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 %vl)
br i1 %cond, label %if, label %if.end br i1 %cond, label %if, label %if.end
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>*, <vscale x 1 x i64>*,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64, i64) i64, i64)
define <vscale x 1 x double> @test1(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test1(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7) %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64( %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
<vscale x 1 x double> undef, <vscale x 1 x double> undef,
<vscale x 1 x double> %a, <vscale x 1 x double> %a,
Show All 16 Lines %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
<vscale x 1 x double> %b, <vscale x 1 x double> %b,
i64 %avl) i64 %avl)
ret <vscale x 1 x double> %1 ret <vscale x 1 x double> %1
} }
define <vscale x 1 x i64> @test3(i64 %avl, <vscale x 1 x i64> %a, <vscale x 1 x i64>* %b, <vscale x 1 x i1> %c) nounwind { define <vscale x 1 x i64> @test3(i64 %avl, <vscale x 1 x i64> %a, <vscale x 1 x i64>* %b, <vscale x 1 x i1> %c) nounwind {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, ma
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a1), v0.t ; CHECK-NEXT: vle64.v v8, (a1), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0) %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
%1 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64( %1 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(
<vscale x 1 x i64> %a, <vscale x 1 x i64> %a,
<vscale x 1 x i64>* %b, <vscale x 1 x i64>* %b,
Show All 19 Linesentry:
ret <vscale x 1 x i64> %1 ret <vscale x 1 x i64> %1
} }
; Make sure we don't insert a vsetvli for the vmand instruction. ; Make sure we don't insert a vsetvli for the vmand instruction.
define <vscale x 1 x i1> @test5(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %avl) nounwind { define <vscale x 1 x i1> @test5(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %avl) nounwind {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmand.mm v0, v8, v0 ; CHECK-NEXT: vmand.mm v0, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0) %vl = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %vl) %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %vl)
%b = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %a, <vscale x 1 x i1> %2, i64 %vl) %b = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %a, <vscale x 1 x i1> %2, i64 %vl)
ret <vscale x 1 x i1> %b ret <vscale x 1 x i1> %b
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64)
declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64)
; Make sure we don't insert a vsetvli for the vmor instruction. ; Make sure we don't insert a vsetvli for the vmor instruction.
define void @test6(i32* nocapture readonly %A, i32* nocapture %B, i64 %n) { define void @test6(i32* nocapture readonly %A, i32* nocapture %B, i64 %n) {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e32, m1, ta, ma
; CHECK-NEXT: beqz a3, .LBB5_3 ; CHECK-NEXT: beqz a3, .LBB5_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li a4, 0
; CHECK-NEXT: .LBB5_2: # %for.body ; CHECK-NEXT: .LBB5_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: slli a5, a4, 2 ; CHECK-NEXT: slli a6, a4, 2
; CHECK-NEXT: add a6, a0, a5 ; CHECK-NEXT: add a5, a0, a6
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a5)
; CHECK-NEXT: vle32.v v8, (a6)
; CHECK-NEXT: vmsle.vi v9, v8, -3 ; CHECK-NEXT: vmsle.vi v9, v8, -3
; CHECK-NEXT: vmsgt.vi v10, v8, 2 ; CHECK-NEXT: vmsgt.vi v10, v8, 2
; CHECK-NEXT: vmor.mm v0, v9, v10 ; CHECK-NEXT: vmor.mm v0, v9, v10
; CHECK-NEXT: add a5, a5, a1 ; CHECK-NEXT: add a6, a6, a1
; CHECK-NEXT: vse32.v v8, (a5), v0.t ; CHECK-NEXT: vse32.v v8, (a6), v0.t
; CHECK-NEXT: add a4, a4, a3 ; CHECK-NEXT: add a4, a4, a3
; CHECK-NEXT: vsetvli a3, a2, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e32, m1, ta, ma
; CHECK-NEXT: bnez a3, .LBB5_2 ; CHECK-NEXT: bnez a3, .LBB5_2
; CHECK-NEXT: .LBB5_3: # %for.cond.cleanup ; CHECK-NEXT: .LBB5_3: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 2, i64 0) %0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 2, i64 0)
%cmp.not11 = icmp eq i64 %0, 0 %cmp.not11 = icmp eq i64 %0, 0
br i1 %cmp.not11, label %for.cond.cleanup, label %for.body br i1 %cmp.not11, label %for.cond.cleanup, label %for.body
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines %0 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
<vscale x 1 x double> %b, <vscale x 1 x double> %b,
i64 -1) i64 -1)
ret <vscale x 1 x double> %0 ret <vscale x 1 x double> %0
} }
define <vscale x 1 x double> @test14(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test14(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test14: ; CHECK-LABEL: test14:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7) %vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
%f1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64( %f1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
Show All 32 Lines
} }
@gdouble = external global double @gdouble = external global double
define <vscale x 1 x double> @test16(i64 %avl, double %a, <vscale x 1 x double> %b) nounwind { define <vscale x 1 x double> @test16(i64 %avl, double %a, <vscale x 1 x double> %b) nounwind {
; CHECK-LABEL: test16: ; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e64, mf2, ta, ma
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v8, v9, v8 ; CHECK-NEXT: vfadd.vv v8, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 7) %vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 7)
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines %y = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(
<vscale x 1 x double> %a, double %b, i64 2) <vscale x 1 x double> %a, double %b, i64 2)
%y2 = fadd <vscale x 1 x double> %y, %a %y2 = fadd <vscale x 1 x double> %y, %a
ret <vscale x 1 x double> %y2 ret <vscale x 1 x double> %y2
} }
define i64 @avl_forward1(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p) nounwind { define i64 @avl_forward1(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p) nounwind {
; CHECK-LABEL: avl_forward1: ; CHECK-LABEL: avl_forward1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli a1, 6, e32, m1, ta, mu ; CHECK-NEXT: vsetivli a1, 6, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvli(i64 6, i64 2, i64 0) %vl = tail call i64 @llvm.riscv.vsetvli(i64 6, i64 2, i64 0)
call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl) call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl)
ret i64 %vl ret i64 %vl
} }
; Incompatible vtype ; Incompatible vtype
define i64 @avl_forward1b_neg(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p) nounwind { define i64 @avl_forward1b_neg(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p) nounwind {
; CHECK-LABEL: avl_forward1b_neg: ; CHECK-LABEL: avl_forward1b_neg:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli a1, 6, e16, m1, ta, mu ; CHECK-NEXT: vsetivli a1, 6, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvli(i64 6, i64 1, i64 0) %vl = tail call i64 @llvm.riscv.vsetvli(i64 6, i64 1, i64 0)
call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl) call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl)
ret i64 %vl ret i64 %vl
} }
define i64 @avl_forward2(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p) nounwind { define i64 @avl_forward2(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p) nounwind {
; CHECK-LABEL: avl_forward2: ; CHECK-LABEL: avl_forward2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvlimax(i64 2, i64 0) %vl = tail call i64 @llvm.riscv.vsetvlimax(i64 2, i64 0)
call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl) call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl)
ret i64 %vl ret i64 %vl
} }
; %vl is intentionally used only once ; %vl is intentionally used only once
define void @avl_forward3(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %reg) nounwind { define void @avl_forward3(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %reg) nounwind {
; CHECK-LABEL: avl_forward3: ; CHECK-LABEL: avl_forward3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvli(i64 %reg, i64 2, i64 0) %vl = tail call i64 @llvm.riscv.vsetvli(i64 %reg, i64 2, i64 0)
call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl) call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl)
ret void ret void
} }
; %vl has multiple uses ; %vl has multiple uses
define i64 @avl_forward3b(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %reg) nounwind { define i64 @avl_forward3b(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %reg) nounwind {
; CHECK-LABEL: avl_forward3b: ; CHECK-LABEL: avl_forward3b:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, a1, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvli(i64 %reg, i64 2, i64 0) %vl = tail call i64 @llvm.riscv.vsetvli(i64 %reg, i64 2, i64 0)
call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl) call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl)
ret i64 %vl ret i64 %vl
} }
; Like4, but with incompatible VTYPE ; Like4, but with incompatible VTYPE
define void @avl_forward4(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %reg) nounwind { define void @avl_forward4(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %reg) nounwind {
; CHECK-LABEL: avl_forward4: ; CHECK-LABEL: avl_forward4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, a1, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvli(i64 %reg, i64 1, i64 0) %vl = tail call i64 @llvm.riscv.vsetvli(i64 %reg, i64 1, i64 0)
call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl) call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl)
ret void ret void
} }
; Like4b, but with incompatible VTYPE ; Like4b, but with incompatible VTYPE
define i64 @avl_forward4b(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %reg) nounwind { define i64 @avl_forward4b(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %reg) nounwind {
; CHECK-LABEL: avl_forward4b: ; CHECK-LABEL: avl_forward4b:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, a1, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%vl = tail call i64 @llvm.riscv.vsetvli(i64 %reg, i64 1, i64 0) %vl = tail call i64 @llvm.riscv.vsetvli(i64 %reg, i64 1, i64 0)
call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl) call void @llvm.riscv.vse.nxv2i32.i64(<vscale x 2 x i32> %v, <vscale x 2 x i32>* %p, i64 %vl)
ret i64 %vl ret i64 %vl
} }
; Fault first loads can modify VL. ; Fault first loads can modify VL.
; TODO: The VSETVLI of vadd could be removed here. ; TODO: The VSETVLI of vadd could be removed here.
define <vscale x 1 x i64> @vleNff(i64* %str, i64 %n, i64 %x) { define <vscale x 1 x i64> @vleNff(i64* %str, i64 %n, i64 %x) {
; CHECK-LABEL: vleNff: ; CHECK-LABEL: vleNff:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, a1, e8, m4, ta, ma
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, ma
; CHECK-NEXT: vadd.vx v8, v8, a2 ; CHECK-NEXT: vadd.vx v8, v8, a2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 0, i64 2) %0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 0, i64 2)
%1 = bitcast i64* %str to <vscale x 1 x i64>* %1 = bitcast i64* %str to <vscale x 1 x i64>*
%2 = tail call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %1, i64 %0) %2 = tail call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %1, i64 %0)
%3 = extractvalue { <vscale x 1 x i64>, i64 } %2, 0 %3 = extractvalue { <vscale x 1 x i64>, i64 } %2, 0
%4 = extractvalue { <vscale x 1 x i64>, i64 } %2, 1 %4 = extractvalue { <vscale x 1 x i64>, i64 } %2, 1
%5 = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> %3, <vscale x 1 x i64> %3, i64 %x, i64 %4) %5 = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> %3, <vscale x 1 x i64> %3, i64 %x, i64 %4)
ret <vscale x 1 x i64> %5 ret <vscale x 1 x i64> %5
} }
; Similiar test case, but use same policy for vleff and vadd. ; Similiar test case, but use same policy for vleff and vadd.
; Note: The test may be redundant if we could fix the TODO of @vleNff. ; Note: The test may be redundant if we could fix the TODO of @vleNff.
define <vscale x 1 x i64> @vleNff2(i64* %str, i64 %n, i64 %x) { define <vscale x 1 x i64> @vleNff2(i64* %str, i64 %n, i64 %x) {
; CHECK-LABEL: vleNff2: ; CHECK-LABEL: vleNff2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, a1, e8, m4, ta, ma
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: vadd.vx v8, v8, a2 ; CHECK-NEXT: vadd.vx v8, v8, a2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 0, i64 2) %0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %n, i64 0, i64 2)
%1 = bitcast i64* %str to <vscale x 1 x i64>* %1 = bitcast i64* %str to <vscale x 1 x i64>*
%2 = tail call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %1, i64 %0) %2 = tail call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %1, i64 %0)
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declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64.i64(
<vscale x 1 x i64>, i64, i64) <vscale x 1 x i64>, i64, i64)
; Ensure AVL register is alive when forwarding an AVL immediate that does not fit in 5 bits ; Ensure AVL register is alive when forwarding an AVL immediate that does not fit in 5 bits
define <vscale x 2 x i32> @avl_forward5(<vscale x 2 x i32>* %addr) { define <vscale x 2 x i32> @avl_forward5(<vscale x 2 x i32>* %addr) {
; CHECK-LABEL: avl_forward5: ; CHECK-LABEL: avl_forward5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli a1, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, a1, e8, m4, ta, ma
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%gvl = tail call i64 @llvm.riscv.vsetvli.i64(i64 32, i64 0, i64 2) %gvl = tail call i64 @llvm.riscv.vsetvli.i64(i64 32, i64 0, i64 2)
%ret = tail call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* %addr, i64 %gvl) %ret = tail call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i32>* %addr, i64 %gvl)
ret <vscale x 2 x i32> %ret ret <vscale x 2 x i32> %ret
} }
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llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
declare iXLen @llvm.riscv.vsetvli.iXLen(iXLen, iXLen, iXLen) declare iXLen @llvm.riscv.vsetvli.iXLen(iXLen, iXLen, iXLen)
declare iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen, iXLen) declare iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen, iXLen)
define iXLen @test_vsetvli_e8m1(iXLen %avl) nounwind { define iXLen @test_vsetvli_e8m1(iXLen %avl) nounwind {
; CHECK-LABEL: test_vsetvli_e8m1: ; CHECK-LABEL: test_vsetvli_e8m1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e8, m1, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 0, iXLen 0) %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 0, iXLen 0)
ret iXLen %vl ret iXLen %vl
} }
define iXLen @test_vsetvli_e16mf4(iXLen %avl) nounwind { define iXLen @test_vsetvli_e16mf4(iXLen %avl) nounwind {
; CHECK-LABEL: test_vsetvli_e16mf4: ; CHECK-LABEL: test_vsetvli_e16mf4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e16, mf4, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 1, iXLen 6) %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 1, iXLen 6)
ret iXLen %vl ret iXLen %vl
} }
define iXLen @test_vsetvli_e64mf8(iXLen %avl) nounwind { define iXLen @test_vsetvli_e64mf8(iXLen %avl) nounwind {
; CHECK-LABEL: test_vsetvli_e64mf8: ; CHECK-LABEL: test_vsetvli_e64mf8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e64, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e64, mf8, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 3, iXLen 5) %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 3, iXLen 5)
ret iXLen %vl ret iXLen %vl
} }
define iXLen @test_vsetvli_e8mf2_zero_avl() nounwind { define iXLen @test_vsetvli_e8mf2_zero_avl() nounwind {
; CHECK-LABEL: test_vsetvli_e8mf2_zero_avl: ; CHECK-LABEL: test_vsetvli_e8mf2_zero_avl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 0, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli a0, 0, e8, mf2, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 0, iXLen 0, iXLen 7) %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 0, iXLen 0, iXLen 7)
ret iXLen %vl ret iXLen %vl
} }
define iXLen @test_vsetvli_e32mf8_zero_avl() nounwind { define iXLen @test_vsetvli_e32mf8_zero_avl() nounwind {
; CHECK-LABEL: test_vsetvli_e32mf8_zero_avl: ; CHECK-LABEL: test_vsetvli_e32mf8_zero_avl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 0, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli a0, 0, e16, mf4, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 0, iXLen 1, iXLen 6) %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 0, iXLen 1, iXLen 6)
ret iXLen %vl ret iXLen %vl
} }
define iXLen @test_vsetvlimax_e32m2() nounwind { define iXLen @test_vsetvlimax_e32m2() nounwind {
; CHECK-LABEL: test_vsetvlimax_e32m2: ; CHECK-LABEL: test_vsetvlimax_e32m2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 2, iXLen 1) %vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 2, iXLen 1)
ret iXLen %vl ret iXLen %vl
} }
define iXLen @test_vsetvlimax_e64m4() nounwind { define iXLen @test_vsetvlimax_e64m4() nounwind {
; CHECK-LABEL: test_vsetvlimax_e64m4: ; CHECK-LABEL: test_vsetvlimax_e64m4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 3, iXLen 2) %vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 3, iXLen 2)
ret iXLen %vl ret iXLen %vl
} }
define iXLen @test_vsetvlimax_e64m8() nounwind { define iXLen @test_vsetvlimax_e64m8() nounwind {
; CHECK-LABEL: test_vsetvlimax_e64m8: ; CHECK-LABEL: test_vsetvlimax_e64m8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 3, iXLen 3) %vl = call iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen 3, iXLen 3)
ret iXLen %vl ret iXLen %vl
} }
; Check that we remove the intrinsic if it's unused. ; Check that we remove the intrinsic if it's unused.
define void @test_vsetvli_e8m1_nouse(iXLen %avl) nounwind { define void @test_vsetvli_e8m1_nouse(iXLen %avl) nounwind {
; CHECK-LABEL: test_vsetvli_e8m1_nouse: ; CHECK-LABEL: test_vsetvli_e8m1_nouse:
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} }
declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.iXLen(<vscale x 4 x i32>, <vscale x 4 x i32>*, iXLen) declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.iXLen(<vscale x 4 x i32>, <vscale x 4 x i32>*, iXLen)
; Check that we remove the redundant vsetvli when followed by another operation ; Check that we remove the redundant vsetvli when followed by another operation
define <vscale x 4 x i32> @redundant_vsetvli(iXLen %avl, <vscale x 4 x i32>* %ptr) nounwind { define <vscale x 4 x i32> @redundant_vsetvli(iXLen %avl, <vscale x 4 x i32>* %ptr) nounwind {
; CHECK-LABEL: redundant_vsetvli: ; CHECK-LABEL: redundant_vsetvli:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 2, iXLen 1) %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 2, iXLen 1)
%x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.iXLen(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, iXLen %vl) %x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.iXLen(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, iXLen %vl)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
; Check that we remove the repeated/redundant vsetvli when followed by another ; Check that we remove the repeated/redundant vsetvli when followed by another
; operation ; operation
; FIXME: We don't catch the second vsetvli because it has a use of its output. ; FIXME: We don't catch the second vsetvli because it has a use of its output.
; We could replace it with the output of the first vsetvli. ; We could replace it with the output of the first vsetvli.
define <vscale x 4 x i32> @repeated_vsetvli(iXLen %avl, <vscale x 4 x i32>* %ptr) nounwind { define <vscale x 4 x i32> @repeated_vsetvli(iXLen %avl, <vscale x 4 x i32>* %ptr) nounwind {
; CHECK-LABEL: repeated_vsetvli: ; CHECK-LABEL: repeated_vsetvli:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, ma
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vl0 = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 2, iXLen 1) %vl0 = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %avl, iXLen 2, iXLen 1)
%vl1 = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %vl0, iXLen 2, iXLen 1) %vl1 = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %vl0, iXLen 2, iXLen 1)
%x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.iXLen(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, iXLen %vl1) %x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.iXLen(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, iXLen %vl1)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }

llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll

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; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-512-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
; CHECK-512-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a1
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2: ; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
; CHECK-64-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 2) i32 2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3: ; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 3, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 3, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3: ; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli zero, 6, e32, m1, ta, ma ; CHECK-512-NEXT: vsetivli zero, 6, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
; CHECK-512-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a1
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3: ; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
; CHECK-64-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 3) i32 3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8: ; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 8, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 8, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8: ; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli zero, 16, e32, m1, ta, ma ; CHECK-512-NEXT: vsetivli zero, 16, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
; CHECK-512-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a1
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8: ; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
; CHECK-64-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 8) i32 8)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9: ; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 9, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 9, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9: ; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli a2, 9, e64, m1, ta, mu ; CHECK-512-NEXT: vsetivli a2, 9, e64, m1, ta, ma
; CHECK-512-NEXT: slli a2, a2, 1 ; CHECK-512-NEXT: slli a2, a2, 1
; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
; CHECK-512-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a1
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9: ; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
; CHECK-64-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 9) i32 9)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15: ; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 15, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 15, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15: ; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli a2, 15, e64, m1, ta, mu ; CHECK-512-NEXT: vsetivli a2, 15, e64, m1, ta, ma
; CHECK-512-NEXT: slli a2, a2, 1 ; CHECK-512-NEXT: slli a2, a2, 1
; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
; CHECK-512-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a1
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15: ; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
; CHECK-64-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 15) i32 15)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16: ; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 16, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 16, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16: ; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-512-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
; CHECK-512-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a1
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16: ; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
; CHECK-64-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 16) i32 16)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047: ; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: li a2, 2047 ; CHECK-128-65536-NEXT: li a2, 2047
; CHECK-128-65536-NEXT: vsetvli a2, a2, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetvli a2, a2, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0
; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047: ; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-512-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
; CHECK-512-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a1
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047: ; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
; CHECK-64-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 2047) i32 2047)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2048(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2048(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2048: ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2048:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 2048) i32 2048)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll

Show First 20 Lines • Show All 850 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
Show All 10 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma
; CHECK-NEXT: vslide1down.vx v9, v9, a0 ; CHECK-NEXT: vslide1down.vx v9, v9, a0
; CHECK-NEXT: vslide1down.vx v9, v9, a1 ; CHECK-NEXT: vslide1down.vx v9, v9, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m2, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma
; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
Show All 10 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m2, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma
; CHECK-NEXT: vslide1down.vx v10, v10, a0 ; CHECK-NEXT: vslide1down.vx v10, v10, a0
; CHECK-NEXT: vslide1down.vx v10, v10, a1 ; CHECK-NEXT: vslide1down.vx v10, v10, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m4, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
Show All 10 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m4, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, ma
; CHECK-NEXT: vslide1down.vx v12, v12, a0 ; CHECK-NEXT: vslide1down.vx v12, v12, a0
; CHECK-NEXT: vslide1down.vx v12, v12, a1 ; CHECK-NEXT: vslide1down.vx v12, v12, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m8, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
Show All 10 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64(
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m8, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vslide1down.vx v16, v16, a0 ; CHECK-NEXT: vslide1down.vx v16, v16, a0
; CHECK-NEXT: vslide1down.vx v16, v16, a1 ; CHECK-NEXT: vslide1down.vx v16, v16, a1
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 9 Lines

llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-512-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-512-NEXT: vslide1up.vx v9, v8, a1
; CHECK-512-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-512-NEXT: vslide1up.vx v8, v9, a0
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2: ; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-64-NEXT: vslide1up.vx v9, v8, a1
; CHECK-64-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-64-NEXT: vslide1up.vx v8, v9, a0
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 2) i32 2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl3(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl3(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl3: ; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl3:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 3, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 3, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1
; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl3: ; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl3:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli zero, 6, e32, m1, ta, ma ; CHECK-512-NEXT: vsetivli zero, 6, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-512-NEXT: vslide1up.vx v9, v8, a1
; CHECK-512-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-512-NEXT: vslide1up.vx v8, v9, a0
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl3: ; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl3:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-64-NEXT: vslide1up.vx v9, v8, a1
; CHECK-64-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-64-NEXT: vslide1up.vx v8, v9, a0
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 3) i32 3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl8(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl8(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl8: ; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl8:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 8, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 8, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1
; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl8: ; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl8:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli zero, 16, e32, m1, ta, ma ; CHECK-512-NEXT: vsetivli zero, 16, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-512-NEXT: vslide1up.vx v9, v8, a1
; CHECK-512-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-512-NEXT: vslide1up.vx v8, v9, a0
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl8: ; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl8:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-64-NEXT: vslide1up.vx v9, v8, a1
; CHECK-64-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-64-NEXT: vslide1up.vx v8, v9, a0
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 8) i32 8)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl9(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl9(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl9: ; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl9:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 9, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 9, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1
; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl9: ; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl9:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli a2, 9, e64, m1, ta, mu ; CHECK-512-NEXT: vsetivli a2, 9, e64, m1, ta, ma
; CHECK-512-NEXT: slli a2, a2, 1 ; CHECK-512-NEXT: slli a2, a2, 1
; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-512-NEXT: vslide1up.vx v9, v8, a1
; CHECK-512-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-512-NEXT: vslide1up.vx v8, v9, a0
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl9: ; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl9:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-64-NEXT: vslide1up.vx v9, v8, a1
; CHECK-64-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-64-NEXT: vslide1up.vx v8, v9, a0
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 9) i32 9)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl15(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl15(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl15: ; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl15:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 15, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 15, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1
; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl15: ; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl15:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetivli a2, 15, e64, m1, ta, mu ; CHECK-512-NEXT: vsetivli a2, 15, e64, m1, ta, ma
; CHECK-512-NEXT: slli a2, a2, 1 ; CHECK-512-NEXT: slli a2, a2, 1
; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-512-NEXT: vslide1up.vx v9, v8, a1
; CHECK-512-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-512-NEXT: vslide1up.vx v8, v9, a0
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl15: ; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl15:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-64-NEXT: vslide1up.vx v9, v8, a1
; CHECK-64-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-64-NEXT: vslide1up.vx v8, v9, a0
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 15) i32 15)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl16(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl16(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl16: ; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl16:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: vsetivli a2, 16, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetivli a2, 16, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1
; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl16: ; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl16:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-512-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-512-NEXT: vslide1up.vx v9, v8, a1
; CHECK-512-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-512-NEXT: vslide1up.vx v8, v9, a0
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl16: ; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl16:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-64-NEXT: vslide1up.vx v9, v8, a1
; CHECK-64-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-64-NEXT: vslide1up.vx v8, v9, a0
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 16) i32 16)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2047(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2047(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2047: ; CHECK-128-65536-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2047:
; CHECK-128-65536: # %bb.0: # %entry ; CHECK-128-65536: # %bb.0: # %entry
; CHECK-128-65536-NEXT: li a2, 2047 ; CHECK-128-65536-NEXT: li a2, 2047
; CHECK-128-65536-NEXT: vsetvli a2, a2, e64, m1, ta, mu ; CHECK-128-65536-NEXT: vsetvli a2, a2, e64, m1, ta, ma
; CHECK-128-65536-NEXT: slli a2, a2, 1 ; CHECK-128-65536-NEXT: slli a2, a2, 1
; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-128-65536-NEXT: vslide1up.vx v9, v8, a1
; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-128-65536-NEXT: vslide1up.vx v8, v9, a0
; CHECK-128-65536-NEXT: ret ; CHECK-128-65536-NEXT: ret
; ;
; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2047: ; CHECK-512-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2047:
; CHECK-512: # %bb.0: # %entry ; CHECK-512: # %bb.0: # %entry
; CHECK-512-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-512-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-512-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-512-NEXT: vslide1up.vx v9, v8, a1
; CHECK-512-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-512-NEXT: vslide1up.vx v8, v9, a0
; CHECK-512-NEXT: ret ; CHECK-512-NEXT: ret
; ;
; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2047: ; CHECK-64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2047:
; CHECK-64: # %bb.0: # %entry ; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-64-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-64-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-64-NEXT: vslide1up.vx v9, v8, a1
; CHECK-64-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-64-NEXT: vslide1up.vx v8, v9, a0
; CHECK-64-NEXT: ret ; CHECK-64-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 2047) i32 2047)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2048(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2048(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2048: ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64_vl2048:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-NEXT: vslide1up.vx v9, v8, a1
; CHECK-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-NEXT: vslide1up.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 2048) i32 2048)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll

Show First 20 Lines • Show All 868 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
; CHECK-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-NEXT: vslide1up.vx v9, v8, a1
; CHECK-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-NEXT: vslide1up.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
Show All 10 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64(
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma
; CHECK-NEXT: vslide1up.vx v10, v9, a1 ; CHECK-NEXT: vslide1up.vx v10, v9, a1
; CHECK-NEXT: vslide1up.vx v9, v10, a0 ; CHECK-NEXT: vslide1up.vx v9, v10, a0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m2, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma
; CHECK-NEXT: vslide1up.vx v10, v8, a1 ; CHECK-NEXT: vslide1up.vx v10, v8, a1
; CHECK-NEXT: vslide1up.vx v8, v10, a0 ; CHECK-NEXT: vslide1up.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
Show All 10 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64(
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m2, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma
; CHECK-NEXT: vslide1up.vx v12, v10, a1 ; CHECK-NEXT: vslide1up.vx v12, v10, a1
; CHECK-NEXT: vslide1up.vx v10, v12, a0 ; CHECK-NEXT: vslide1up.vx v10, v12, a0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m4, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vslide1up.vx v12, v8, a1 ; CHECK-NEXT: vslide1up.vx v12, v8, a1
; CHECK-NEXT: vslide1up.vx v8, v12, a0 ; CHECK-NEXT: vslide1up.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
Show All 10 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64(
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m4, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, ma
; CHECK-NEXT: vslide1up.vx v16, v12, a1 ; CHECK-NEXT: vslide1up.vx v16, v12, a1
; CHECK-NEXT: vslide1up.vx v12, v16, a0 ; CHECK-NEXT: vslide1up.vx v12, v16, a0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e64, m8, ta, ma
; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vslide1up.vx v16, v8, a1 ; CHECK-NEXT: vslide1up.vx v16, v8, a1
; CHECK-NEXT: vslide1up.vx v8, v16, a0 ; CHECK-NEXT: vslide1up.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
Show All 10 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64(
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a3, a2, e64, m8, ta, ma
; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vslide1up.vx v24, v16, a1 ; CHECK-NEXT: vslide1up.vx v24, v16, a1
; CHECK-NEXT: vslide1up.vx v16, v24, a0 ; CHECK-NEXT: vslide1up.vx v16, v24, a0
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 9 Lines

llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O3 -mattr=+v -lsr-drop-solution | FileCheck --check-prefix=CHECK %s ; RUN: llc < %s -O3 -mattr=+v -lsr-drop-solution | FileCheck --check-prefix=CHECK %s
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64-unknown-linux-gnu" target triple = "riscv64-unknown-linux-gnu"
define ptr @foo(ptr %a0, ptr %a1, i64 %a2) { define ptr @foo(ptr %a0, ptr %a1, i64 %a2) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a4, a2, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a4, a2, e8, m8, ta, ma
; CHECK-NEXT: bne a4, a2, .LBB0_2 ; CHECK-NEXT: bne a4, a2, .LBB0_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a0 ; CHECK-NEXT: mv a3, a0
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: vse8.v v8, (a3)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: # %if.then ; CHECK-NEXT: .LBB0_2: # %if.then
; CHECK-NEXT: add a2, a0, a2 ; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: sub a5, a2, a4 ; CHECK-NEXT: sub a5, a2, a4
; CHECK-NEXT: mv a3, a0 ; CHECK-NEXT: mv a3, a0
; CHECK-NEXT: .LBB0_3: # %do.body ; CHECK-NEXT: .LBB0_3: # %do.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: vse8.v v8, (a3)
; CHECK-NEXT: add a3, a3, a4 ; CHECK-NEXT: add a3, a3, a4
; CHECK-NEXT: add a1, a1, a4 ; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: bltu a3, a5, .LBB0_3 ; CHECK-NEXT: bltu a3, a5, .LBB0_3
; CHECK-NEXT: # %bb.4: # %do.end ; CHECK-NEXT: # %bb.4: # %do.end
; CHECK-NEXT: sub a2, a2, a3 ; CHECK-NEXT: sub a2, a2, a3
; CHECK-NEXT: vsetvli a2, a2, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a2, a2, e8, m8, ta, ma
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: vse8.v v8, (a3)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%0 = ptrtoint ptr %a0 to i64 %0 = ptrtoint ptr %a0 to i64
%1 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %a2, i64 0, i64 3) %1 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %a2, i64 0, i64 3)
%cmp.not = icmp eq i64 %1, %a2 %cmp.not = icmp eq i64 %1, %a2
Show All 38 Lines