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Differential D143472

[clang] Cast the pointer to right type with different address space
Needs ReviewPublic

Authored by cdai2 on Feb 7 2023, 12:37 AM.

Details

Reviewers
Anastasia
Summary

The source type has OpenCL general address space but dest type does
not have address space. Address space cast is needed for this scenario.

Diff Detail

Unit TestsFailed

TimeTest
620 msx64 debian > Clang.Driver::rocm-detect.hip

Event Timeline

cdai2 created this revision.Feb 7 2023, 12:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 7 2023, 12:37 AM
Herald added subscribers: pengfei, arichardson, Anastasia. · View Herald Transcript
cdai2 requested review of this revision.Feb 7 2023, 12:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 7 2023, 12:37 AM
Herald added a subscriber: cfe-commits. · View Herald Transcript
Harbormaster completed remote builds in B212294: Diff 495402.Feb 7 2023, 1:45 AM
cdai2 updated this revision to Diff 496033.Feb 8 2023, 11:36 PM

[clang] update test case

Harbormaster completed remote builds in B212748: Diff 496033.Feb 9 2023, 12:10 AM
cdai2 updated this revision to Diff 496275.Feb 9 2023, 4:16 PM

Update cases to cover both opaque pointer and typed pointer

bader added a reviewer: Anastasia.Feb 9 2023, 5:07 PM
Harbormaster completed remote builds in B212923: Diff 496275.Feb 9 2023, 6:51 PM
Anastasia added inline comments.Feb 12 2023, 12:55 PM
clang/lib/CodeGen/CGBuiltin.cpp
12412

I think the semantics of builtin functions is that they accept any address space. So you should preserve the address space from Ops[1].

Revision Contents

PathSize
clang/
lib/
CodeGen/
8 lines
test/
CodeGen/
X86/
67 lines
69 lines

Diff 496275

clang/lib/CodeGen/CGBuiltin.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===// //===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 12,395 Lines • ▼ Show 20 Lines MaskVec = CGF.Builder.CreateShuffleVector(
MaskVec, MaskVec, ArrayRef(Indices, NumElts), "extract"); MaskVec, MaskVec, ArrayRef(Indices, NumElts), "extract");
} }
return MaskVec; return MaskVec;
} }
static Value *EmitX86MaskedStore(CodeGenFunction &CGF, ArrayRef<Value *> Ops, static Value *EmitX86MaskedStore(CodeGenFunction &CGF, ArrayRef<Value *> Ops,
Align Alignment) { Align Alignment) {
// Cast the pointer to right type. // Cast the pointer to right type.
Value *Ptr = CGF.Builder.CreateBitCast(Ops[0], Value *Ptr = CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(
AnastasiaUnsubmitted
Not Done
ReplyInline Actions

I think the semantics of builtin functions is that they accept any address space. So you should preserve the address space from Ops[1].

Anastasia: I think the semantics of builtin functions is that they accept any address space. So you should…
llvm::PointerType::getUnqual(Ops[1]->getType())); Ops[0], llvm::PointerType::getUnqual(Ops[1]->getType()));
Value *MaskVec = getMaskVecValue( Value *MaskVec = getMaskVecValue(
CGF, Ops[2], CGF, Ops[2],
cast<llvm::FixedVectorType>(Ops[1]->getType())->getNumElements()); cast<llvm::FixedVectorType>(Ops[1]->getType())->getNumElements());
return CGF.Builder.CreateMaskedStore(Ops[1], Ptr, Alignment, MaskVec); return CGF.Builder.CreateMaskedStore(Ops[1], Ptr, Alignment, MaskVec);
} }
static Value *EmitX86MaskedLoad(CodeGenFunction &CGF, ArrayRef<Value *> Ops, static Value *EmitX86MaskedLoad(CodeGenFunction &CGF, ArrayRef<Value *> Ops,
Align Alignment) { Align Alignment) {
// Cast the pointer to right type. // Cast the pointer to right type.
llvm::Type *Ty = Ops[1]->getType(); llvm::Type *Ty = Ops[1]->getType();
Value *Ptr = Value *Ptr = CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(
CGF.Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty)); Ops[0], llvm::PointerType::getUnqual(Ty));
Value *MaskVec = getMaskVecValue( Value *MaskVec = getMaskVecValue(
CGF, Ops[2], cast<llvm::FixedVectorType>(Ty)->getNumElements()); CGF, Ops[2], cast<llvm::FixedVectorType>(Ty)->getNumElements());
return CGF.Builder.CreateMaskedLoad(Ty, Ptr, Alignment, MaskVec, Ops[1]); return CGF.Builder.CreateMaskedLoad(Ty, Ptr, Alignment, MaskVec, Ops[1]);
} }
static Value *EmitX86ExpandLoad(CodeGenFunction &CGF, static Value *EmitX86ExpandLoad(CodeGenFunction &CGF,
▲ Show 20 Lines • Show All 7,387 Lines • Show Last 20 Lines

clang/test/CodeGen/X86/x86-builtins-intrinsic-opaqueptr.cl

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 %s -triple x86_64-pc-linux \
// RUN: -emit-llvm -O0 -cl-std=CL2.0 -ffake-address-space-map \
// RUN: -target-cpu skx -o - | FileCheck %s
typedef int __v16si __attribute__((__vector_size__(64)));
// CHECK-LABEL: @load(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[__U_ADDR:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[__P_ADDR:%.*]] = alloca ptr addrspace(4), align 8
// CHECK-NEXT: [[DD:%.*]] = alloca <16 x i32>, align 64
// CHECK-NEXT: store i16 [[__U:%.*]], ptr [[__U_ADDR]], align 2
// CHECK-NEXT: store ptr addrspace(4) [[__P:%.*]], ptr [[__P_ADDR]], align 8
// CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[DD]], align 64
// CHECK-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr [[__P_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[DD]], align 64
// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[__U_ADDR]], align 2
// CHECK-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(4) [[TMP0]] to ptr
// CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>
// CHECK-NEXT: [[TMP5:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0(ptr [[TMP3]], i32 1, <16 x i1> [[TMP4]], <16 x i32> [[TMP1]])
// CHECK-NEXT: ret void
//
void load(unsigned short __U, void const *__P) {
__v16si dd = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
__builtin_ia32_loaddqusi512_mask(__P, dd, __U);
}
// CHECK-LABEL: @store(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[__U_ADDR:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[__P_ADDR:%.*]] = alloca ptr addrspace(4), align 8
// CHECK-NEXT: [[AA:%.*]] = alloca <16 x i32>, align 64
// CHECK-NEXT: store i16 [[__U:%.*]], ptr [[__U_ADDR]], align 2
// CHECK-NEXT: store ptr addrspace(4) [[__P:%.*]], ptr [[__P_ADDR]], align 8
// CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[AA]], align 64
// CHECK-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr [[__P_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[AA]], align 64
// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[__U_ADDR]], align 2
// CHECK-NEXT: [[TMP3:%.*]] = addrspacecast ptr addrspace(4) [[TMP0]] to ptr
// CHECK-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>
// CHECK-NEXT: call void @llvm.masked.store.v16i32.p0(<16 x i32> [[TMP1]], ptr [[TMP3]], i32 1, <16 x i1> [[TMP4]])
// CHECK-NEXT: ret void
//
void store(unsigned short __U, void const *__P) {
__v16si aa = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
__builtin_ia32_storedqusi512_mask((int *)__P, aa, __U);
}
// CHECK-LABEL: @foo(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[PLOADSTORE_ADDR:%.*]] = alloca ptr addrspace(4), align 8
// CHECK-NEXT: [[MASK_ADDR:%.*]] = alloca i16, align 2
// CHECK-NEXT: store ptr addrspace(4) [[PLOADSTORE:%.*]], ptr [[PLOADSTORE_ADDR]], align 8
// CHECK-NEXT: store i16 [[MASK:%.*]], ptr [[MASK_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[MASK_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load ptr addrspace(4), ptr [[PLOADSTORE_ADDR]], align 8
// CHECK-NEXT: call void @load(i16 noundef zeroext [[TMP0]], ptr addrspace(4) noundef [[TMP1]]) #[[ATTR4:[0-9]+]]
// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[MASK_ADDR]], align 2
// CHECK-NEXT: [[TMP3:%.*]] = load ptr addrspace(4), ptr [[PLOADSTORE_ADDR]], align 8
// CHECK-NEXT: call void @store(i16 noundef zeroext [[TMP2]], ptr addrspace(4) noundef [[TMP3]]) #[[ATTR4]]
// CHECK-NEXT: ret void
//
void foo(void const *pLoadStore, unsigned short mask) {
load(mask, pLoadStore);
store(mask, pLoadStore);
}

clang/test/CodeGen/X86/x86-builtins-intrinsic-typedptr.cl

  • This file was added.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -no-opaque-pointers %s -triple x86_64-pc-linux \
// RUN: -emit-llvm -O0 -cl-std=CL2.0 -ffake-address-space-map \
// RUN: -target-cpu skx -o - | FileCheck %s
typedef int __v16si __attribute__((__vector_size__(64)));
// CHECK-LABEL: @load(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[__U_ADDR:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[__P_ADDR:%.*]] = alloca i8 addrspace(4)*, align 8
// CHECK-NEXT: [[DD:%.*]] = alloca <16 x i32>, align 64
// CHECK-NEXT: store i16 [[__U:%.*]], i16* [[__U_ADDR]], align 2
// CHECK-NEXT: store i8 addrspace(4)* [[__P:%.*]], i8 addrspace(4)** [[__P_ADDR]], align 8
// CHECK-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* [[DD]], align 64
// CHECK-NEXT: [[TMP0:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[__P_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(4)* [[TMP0]] to i32 addrspace(4)*
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[DD]], align 64
// CHECK-NEXT: [[TMP3:%.*]] = load i16, i16* [[__U_ADDR]], align 2
// CHECK-NEXT: [[TMP4:%.*]] = addrspacecast i32 addrspace(4)* [[TMP1]] to <16 x i32>*
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>
// CHECK-NEXT: [[TMP6:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* [[TMP4]], i32 1, <16 x i1> [[TMP5]], <16 x i32> [[TMP2]])
// CHECK-NEXT: ret void
//
void load(unsigned short __U, void const *__P) {
__v16si dd = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
__builtin_ia32_loaddqusi512_mask(__P, dd, __U);
}
// CHECK-LABEL: @store(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[__U_ADDR:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[__P_ADDR:%.*]] = alloca i8 addrspace(4)*, align 8
// CHECK-NEXT: [[AA:%.*]] = alloca <16 x i32>, align 64
// CHECK-NEXT: store i16 [[__U:%.*]], i16* [[__U_ADDR]], align 2
// CHECK-NEXT: store i8 addrspace(4)* [[__P:%.*]], i8 addrspace(4)** [[__P_ADDR]], align 8
// CHECK-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* [[AA]], align 64
// CHECK-NEXT: [[TMP0:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[__P_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(4)* [[TMP0]] to i32 addrspace(4)*
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[AA]], align 64
// CHECK-NEXT: [[TMP3:%.*]] = load i16, i16* [[__U_ADDR]], align 2
// CHECK-NEXT: [[TMP4:%.*]] = addrspacecast i32 addrspace(4)* [[TMP1]] to <16 x i32>*
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP3]] to <16 x i1>
// CHECK-NEXT: call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32> [[TMP2]], <16 x i32>* [[TMP4]], i32 1, <16 x i1> [[TMP5]])
// CHECK-NEXT: ret void
//
void store(unsigned short __U, void const *__P) {
__v16si aa = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
__builtin_ia32_storedqusi512_mask((int *)__P, aa, __U);
}
// CHECK-LABEL: @foo(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[PLOADSTORE_ADDR:%.*]] = alloca i8 addrspace(4)*, align 8
// CHECK-NEXT: [[MASK_ADDR:%.*]] = alloca i16, align 2
// CHECK-NEXT: store i8 addrspace(4)* [[PLOADSTORE:%.*]], i8 addrspace(4)** [[PLOADSTORE_ADDR]], align 8
// CHECK-NEXT: store i16 [[MASK:%.*]], i16* [[MASK_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[MASK_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[PLOADSTORE_ADDR]], align 8
// CHECK-NEXT: call void @load(i16 noundef zeroext [[TMP0]], i8 addrspace(4)* noundef [[TMP1]]) #[[ATTR4:[0-9]+]]
// CHECK-NEXT: [[TMP2:%.*]] = load i16, i16* [[MASK_ADDR]], align 2
// CHECK-NEXT: [[TMP3:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[PLOADSTORE_ADDR]], align 8
// CHECK-NEXT: call void @store(i16 noundef zeroext [[TMP2]], i8 addrspace(4)* noundef [[TMP3]]) #[[ATTR4]]
// CHECK-NEXT: ret void
//
void foo(void const *pLoadStore, unsigned short mask) {
load(mask, pLoadStore);
store(mask, pLoadStore);
}