[AMDGPU] GFX11: accept global_atomic_csub as an alias

[foad]

Summary

GFX11 renamed this instruction to global_atomic_csub_u32 but should
accept the old name as an alias, for consistency with the other global
atomics and with buffer_atomic_csub.

[arsenm]

I didn't realize we had any instruction missing a type suffix.

BTW if you're looking at this instruction, I think I noticed we're missing a selection predicate on the intrinsic pattern

llvm/lib/Target/AMDGPU/FLATInstructions.td

class FLAT_Real_gfx11 <bits<7> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
 
   let Inst{13}    = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlcValue);
   let Inst{14}    = !if(ps.has_glc, cpol{CPolBit.GLC}, ps.glcValue);
   let Inst{15}    = cpol{CPolBit.SLC};
   let Inst{17-16} = seg;
   let Inst{55}    = ps.sve;
 }
 
-multiclass FLAT_Real_Base_gfx11<bits<7> op, string ps, string opName, int renamed = false> {
+multiclass FLAT_Aliases_gfx11<string ps, string opName, int renamed> {
+  if renamed then
+    def _renamed_gfx11 : MnemonicAlias<!cast<FLAT_Pseudo>(ps).Mnemonic, opName>, Requires<[isGFX11Plus]>;
+}
+
+multiclass FLAT_Real_Base_gfx11<bits<7> op, string ps, string opName, int renamed = false> :
+  FLAT_Aliases_gfx11<ps, opName, renamed> {
   def _gfx11 : FLAT_Real_gfx11<op, !cast<FLAT_Pseudo>(ps), opName> {
     let Inst{54-48} = !cast<int>(SGPR_NULL_gfx11plus.HWEncoding);
   }
-  if renamed then
-    def _renamed_gfx11 : MnemonicAlias<!cast<FLAT_Pseudo>(ps).Mnemonic, opName>, Requires<[isGFX11Plus]>;
 }
 
 multiclass FLAT_Real_RTN_gfx11<bits<7> op, string ps, string opName> {
   def _RTN_gfx11 : FLAT_Real_gfx11<op, !cast<FLAT_Pseudo>(ps#"_RTN"), opName> {
     let Inst{54-48} = !cast<int>(SGPR_NULL_gfx11plus.HWEncoding);
   }
 }
 
multiclass FLAT_Real_Atomics_gfx11<bits<7> op, string ps, string opName, int renamed = false> :
   FLAT_Real_Base_gfx11<op, ps, opName, renamed>,
   FLAT_Real_RTN_gfx11<op, ps, opName>;
 
 multiclass FLAT_Real_GlblAtomics_gfx11<bits<7> op, string ps, string opName, int renamed = false> :
   FLAT_Real_AllAddr_gfx11<op, ps, opName, renamed>,
   FLAT_Real_RTN_gfx11<op, ps, opName>,
   FLAT_Real_SADDR_RTN_gfx11<op, ps, opName>;
 
-multiclass FLAT_Real_GlblAtomics_RTN_gfx11<bits<7> op, string ps, string opName> :
+multiclass FLAT_Real_GlblAtomics_RTN_gfx11<bits<7> op, string ps, string opName, int renamed = false> :
+  FLAT_Aliases_gfx11<ps#"_RTN", opName, renamed>,
   FLAT_Real_RTN_gfx11<op, ps, opName>,
   FLAT_Real_SADDR_RTN_gfx11<op, ps, opName>;
 
 multiclass FLAT_Real_ScratchAllAddr_gfx11<bits<7> op, string ps, string opName, int renamed = false> :
   FLAT_Real_Base_gfx11<op, ps, opName, renamed>,
   FLAT_Real_SADDR_gfx11<op, ps, opName>,
   FLAT_Real_ST_gfx11<op, ps, opName>,
   FLAT_Real_SVS_gfx11<op, ps, opName>;

 defm GLOBAL_STORE_D16_HI_B8     : FLAT_Real_AllAddr_gfx11<0x024, "GLOBAL_STORE_BYTE_D16_HI", "global_store_d16_hi_b8">;
 defm GLOBAL_STORE_D16_HI_B16    : FLAT_Real_AllAddr_gfx11<0x025, "GLOBAL_STORE_SHORT_D16_HI", "global_store_d16_hi_b16">;
 defm GLOBAL_LOAD_ADDTID_B32     : FLAT_Real_AllAddr_gfx11<0x028, "GLOBAL_LOAD_DWORD_ADDTID", "global_load_addtid_b32">;
 defm GLOBAL_STORE_ADDTID_B32    : FLAT_Real_AllAddr_gfx11<0x029, "GLOBAL_STORE_DWORD_ADDTID", "global_store_addtid_b32">;
 defm GLOBAL_ATOMIC_SWAP_B32     : FLAT_Real_GlblAtomics_gfx11<0x033, "GLOBAL_ATOMIC_SWAP", "global_atomic_swap_b32", true>;
 defm GLOBAL_ATOMIC_CMPSWAP_B32  : FLAT_Real_GlblAtomics_gfx11<0x034, "GLOBAL_ATOMIC_CMPSWAP", "global_atomic_cmpswap_b32", true>;
 defm GLOBAL_ATOMIC_ADD_U32      : FLAT_Real_GlblAtomics_gfx11<0x035, "GLOBAL_ATOMIC_ADD", "global_atomic_add_u32", true>;
 defm GLOBAL_ATOMIC_SUB_U32      : FLAT_Real_GlblAtomics_gfx11<0x036, "GLOBAL_ATOMIC_SUB", "global_atomic_sub_u32", true>;
-defm GLOBAL_ATOMIC_CSUB_U32     : FLAT_Real_GlblAtomics_RTN_gfx11<0x037, "GLOBAL_ATOMIC_CSUB", "global_atomic_csub_u32">;
+defm GLOBAL_ATOMIC_CSUB_U32     : FLAT_Real_GlblAtomics_RTN_gfx11<0x037, "GLOBAL_ATOMIC_CSUB", "global_atomic_csub_u32", true>;
 defm GLOBAL_ATOMIC_MIN_I32      : FLAT_Real_GlblAtomics_gfx11<0x038, "GLOBAL_ATOMIC_SMIN", "global_atomic_min_i32", true>;
 defm GLOBAL_ATOMIC_MIN_U32      : FLAT_Real_GlblAtomics_gfx11<0x039, "GLOBAL_ATOMIC_UMIN", "global_atomic_min_u32", true>;
 defm GLOBAL_ATOMIC_MAX_I32      : FLAT_Real_GlblAtomics_gfx11<0x03a, "GLOBAL_ATOMIC_SMAX", "global_atomic_max_i32", true>;
 defm GLOBAL_ATOMIC_MAX_U32      : FLAT_Real_GlblAtomics_gfx11<0x03b, "GLOBAL_ATOMIC_UMAX", "global_atomic_max_u32", true>;
 defm GLOBAL_ATOMIC_AND_B32      : FLAT_Real_GlblAtomics_gfx11<0x03c, "GLOBAL_ATOMIC_AND", "global_atomic_and_b32", true>;
 defm GLOBAL_ATOMIC_OR_B32       : FLAT_Real_GlblAtomics_gfx11<0x03d, "GLOBAL_ATOMIC_OR", "global_atomic_or_b32", true>;
 defm GLOBAL_ATOMIC_XOR_B32      : FLAT_Real_GlblAtomics_gfx11<0x03e, "GLOBAL_ATOMIC_XOR", "global_atomic_xor_b32", true>;
 defm GLOBAL_ATOMIC_INC_U32      : FLAT_Real_GlblAtomics_gfx11<0x03f, "GLOBAL_ATOMIC_INC", "global_atomic_inc_u32", true>;

llvm/test/MC/AMDGPU/gfx11_asm_flat.s

 // GFX11: [0x00,0x00,0x0a,0xdd,0xff,0x02,0x68,0x00]
 
 global_atomic_cmpswap_x2 v[5:6], v255, v[2:5], vcc offset:4095 glc
 // GFX11: [0xff,0x4f,0x0a,0xdd,0xff,0x02,0x6a,0x05]
 
 global_atomic_cmpswap_x2 v[254:255], v255, v[252:255], ttmp[14:15] offset:-4096 glc slc dlc
 // GFX11: [0x00,0xf0,0x0a,0xdd,0xff,0xfc,0x7a,0xfe]
 
+global_atomic_csub v5, v[1:2], v2, off glc
+// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x7c,0x05]
+
+global_atomic_csub v5, v[254:255], v2, off glc
+// GFX11: [0x00,0x40,0xde,0xdc,0xfe,0x02,0x7c,0x05]
+
+global_atomic_csub v5, v1, v2, s[6:7] glc
+// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x06,0x05]
+
+global_atomic_csub v5, v1, v2, s[104:105] glc
+// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x68,0x05]
+
+global_atomic_csub v5, v1, v2, vcc glc
+// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x6a,0x05]
+
+global_atomic_csub v5, v1, v2, ttmp[14:15] glc
+// GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x7a,0x05]
+
+global_atomic_csub v5, v255, v2, s[6:7] offset:-1 glc
+// GFX11: [0xff,0x5f,0xde,0xdc,0xff,0x02,0x06,0x05]
+
+global_atomic_csub v5, v255, v2, s[104:105] offset:0 glc
+// GFX11: [0x00,0x40,0xde,0xdc,0xff,0x02,0x68,0x05]
+
+global_atomic_csub v5, v255, v2, vcc offset:4095 glc
+// GFX11: [0xff,0x4f,0xde,0xdc,0xff,0x02,0x6a,0x05]
+
+global_atomic_csub v255, v255, v255, ttmp[14:15] offset:-4096 glc slc dlc
+// GFX11: [0x00,0xf0,0xde,0xdc,0xff,0xff,0x7a,0xff]
+
 global_atomic_csub_u32 v5, v[1:2], v2, off glc
 // GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x7c,0x05]
 
 global_atomic_csub_u32 v5, v[254:255], v2, off glc
 // GFX11: [0x00,0x40,0xde,0xdc,0xfe,0x02,0x7c,0x05]
 
 global_atomic_csub_u32 v5, v1, v2, s[6:7] glc
 // GFX11: [0x00,0x40,0xde,0xdc,0x01,0x02,0x06,0x05]