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Differential D143134

[AMDGPU][SDAG] attempt to custom legalize uaddo/usubo for long operands
Needs RevisionPublic

Authored by vikramRH on Feb 1 2023, 8:15 PM.

Details

Reviewers
arsenm
foad
alex-t
Summary

The goal here was to eliminate the redundant compare instruction generated in addition to add/sub2. Tries to address the issue discussed here, https://github.com/RadeonOpenCompute/ROCm/issues/477

Im having to modify the instruction selection for uniform addcarry/subcarry node when one of the carry users have already been selected to VALU to avoid suboptimal pattern. I have some concerns here and would like to know if it could be done in a better way.

Diff Detail

Event Timeline

vikramRH created this revision.Feb 1 2023, 8:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 1 2023, 8:15 PM
Herald added subscribers: kosarev, StephenFan, kerbowa and 6 others. · View Herald Transcript
vikramRH requested review of this revision.Feb 1 2023, 8:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 1 2023, 8:15 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B211376: Diff 494153.Feb 1 2023, 9:00 PM
arsenm added a comment.Feb 2 2023, 3:09 AM

Are there any new tests that demonstrate what you are trying to do?

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
893–894

Spaces after // and capitalize

llvm/lib/Target/AMDGPU/SIISelLowering.cpp
5436

I don't see the point of this, you're just doing what the default legalization should do in 1 step instead of 2

llvm/test/CodeGen/AMDGPU/carryout-selection.ll
197

In a precommit can you convert this to generated checks? It's hard to see what's going on here

llvm/test/CodeGen/AMDGPU/udiv64.ll
352–354

This is a regression

llvm/test/CodeGen/AMDGPU/usubsat.ll
684–687

This is an improvement

vikramRH mentioned this in D143987: [AMDGPU] Autogenerate carryout-selection.ll, uaddo.ll, usubo.ll (NFC).Feb 14 2023, 12:47 AM
alex-t added inline comments.Feb 20 2023, 9:16 AM
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
899

if (!RC) is "true" which means getOperandRegClass has returned NULL we've got to evaluate the second part of the condition and will call the SIRegisterInfo::isSGPRClass with nullptr? Shouldn't there be OR instead?

alex-t added inline comments.Feb 20 2023, 9:36 AM
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
906

What if N is not divergent but has just one user selected to VALU and has yet 10 SALU users? Would this still be optimal?

945

Does this really belong to this change?

arsenm requested changes to this revision.Aug 15 2023, 10:42 AM
This revision now requires changes to proceed.Aug 15 2023, 10:42 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
30 lines
2 lines
32 lines
test/
CodeGen/
AMDGPU/
56 lines
569 lines
557 lines
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551 lines
399 lines
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Diff 494153

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Show First 20 Lines • Show All 881 Lines • ▼ Show 20 Lines
} }
void AMDGPUDAGToDAGISel::SelectAddcSubb(SDNode *N) { void AMDGPUDAGToDAGISel::SelectAddcSubb(SDNode *N) {
SDLoc DL(N); SDLoc DL(N);
SDValue LHS = N->getOperand(0); SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1); SDValue RHS = N->getOperand(1);
SDValue CI = N->getOperand(2); SDValue CI = N->getOperand(2);
if (N->isDivergent()) { bool IsAdd = N->getOpcode() == ISD::ADDCARRY;
unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64 bool IsVALU = N->isDivergent();
//trying to avoid suboptimal selection pattern when the carry user has
//already been selected to VALU
arsenmUnsubmitted
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Spaces after // and capitalize

arsenm: Spaces after // and capitalize
for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;
++UI){
if((UI.getUse().getResNo() == 1) && (*UI)->isMachineOpcode()){
const TargetRegisterClass *RC = getOperandRegClass(*UI, UI.getOperandNo());
if(!RC && Subtarget->getRegisterInfo()->isSGPRClass(RC))
alex-tUnsubmitted
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if (!RC) is "true" which means getOperandRegClass has returned NULL we've got to evaluate the second part of the condition and will call the SIRegisterInfo::isSGPRClass with nullptr? Shouldn't there be OR instead?

alex-t: if (!RC) is "true" which means getOperandRegClass has returned NULL we've got to evaluate the…
continue;
IsVALU = true;
break;
}
}
if (IsVALU) {
alex-tUnsubmitted
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What if N is not divergent but has just one user selected to VALU and has yet 10 SALU users? Would this still be optimal?

alex-t: What if N is not divergent but has just one user selected to VALU and has yet 10 SALU users?
unsigned Opc = IsAdd ? AMDGPU::V_ADDC_U32_e64
: AMDGPU::V_SUBB_U32_e64; : AMDGPU::V_SUBB_U32_e64;
CurDAG->SelectNodeTo( CurDAG->SelectNodeTo(
N, Opc, N->getVTList(), N, Opc, N->getVTList(),
{LHS, RHS, CI, {LHS, RHS, CI,
CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/}); CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
} else { } else {
unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::S_ADD_CO_PSEUDO unsigned Opc = IsAdd ? AMDGPU::S_ADD_CO_PSEUDO
: AMDGPU::S_SUB_CO_PSEUDO; : AMDGPU::S_SUB_CO_PSEUDO;
CurDAG->SelectNodeTo(N, Opc, N->getVTList(), {LHS, RHS, CI}); CurDAG->SelectNodeTo(N, Opc, N->getVTList(), {LHS, RHS, CI});
} }
} }
void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) { void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
// The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned // The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned
// carry out despite the _i32 name. These were renamed in VI to _U32. // carry out despite the _i32 name. These were renamed in VI to _U32.
// FIXME: We should probably rename the opcodes here. // FIXME: We should probably rename the opcodes here.
Show All 13 Linesvoid AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
if (IsVALU) { if (IsVALU) {
unsigned Opc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64; unsigned Opc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;
CurDAG->SelectNodeTo( CurDAG->SelectNodeTo(
N, Opc, N->getVTList(), N, Opc, N->getVTList(),
{N->getOperand(0), N->getOperand(1), {N->getOperand(0), N->getOperand(1),
CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/}); CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
} else { } else {
unsigned Opc = N->getOpcode() == ISD::UADDO ? AMDGPU::S_UADDO_PSEUDO unsigned Opc = IsAdd ? AMDGPU::S_UADDO_PSEUDO
alex-tUnsubmitted
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Does this really belong to this change?

alex-t: Does this really belong to this change?
: AMDGPU::S_USUBO_PSEUDO; : AMDGPU::S_USUBO_PSEUDO;
CurDAG->SelectNodeTo(N, Opc, N->getVTList(), CurDAG->SelectNodeTo(N, Opc, N->getVTList(),
{N->getOperand(0), N->getOperand(1)}); {N->getOperand(0), N->getOperand(1)});
} }
} }
void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) { void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
SDLoc SL(N); SDLoc SL(N);
▲ Show 20 Lines • Show All 2,066 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIISelLowering.h

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Linesprivate:
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
SelectionDAG &DAG, ArrayRef<SDValue> Ops, SelectionDAG &DAG, ArrayRef<SDValue> Ops,
bool IsIntrinsic = false) const; bool IsIntrinsic = false) const;
SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
ArrayRef<SDValue> Ops) const; ArrayRef<SDValue> Ops) const;
SDValue lowerUADDOSUBBO(SDValue Op, SelectionDAG &DAG) const;
// Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
// dwordx4 if on SI. // dwordx4 if on SI.
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
ArrayRef<SDValue> Ops, EVT MemVT, ArrayRef<SDValue> Ops, EVT MemVT,
MachineMemOperand *MMO, SelectionDAG &DAG) const; MachineMemOperand *MMO, SelectionDAG &DAG) const;
SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
bool ImageStore = false) const; bool ImageStore = false) const;
▲ Show 20 Lines • Show All 410 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 238 Lines • ▼ Show 20 Lines setOperationAction(ISD::SIGN_EXTEND_INREG,
Custom); Custom);
setOperationAction(ISD::BRCOND, MVT::Other, Custom); setOperationAction(ISD::BRCOND, MVT::Other, Custom);
setOperationAction(ISD::BR_CC, setOperationAction(ISD::BR_CC,
{MVT::i1, MVT::i32, MVT::i64, MVT::f32, MVT::f64}, Expand); {MVT::i1, MVT::i32, MVT::i64, MVT::f32, MVT::f64}, Expand);
setOperationAction({ISD::UADDO, ISD::USUBO}, MVT::i32, Legal); setOperationAction({ISD::UADDO, ISD::USUBO}, MVT::i32, Legal);
setOperationAction({ISD::UADDO, ISD::USUBO}, MVT::i64, Custom);
setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i32, Legal); setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i32, Legal);
setOperationAction({ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}, MVT::i64, setOperationAction({ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}, MVT::i64,
Expand); Expand);
#if 0 #if 0
setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i64, Legal); setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i64, Legal);
#endif #endif
▲ Show 20 Lines • Show All 4,531 Lines • ▼ Show 20 LinesSDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SMULO: case ISD::SMULO:
case ISD::UMULO: case ISD::UMULO:
return lowerXMULO(Op, DAG); return lowerXMULO(Op, DAG);
case ISD::SMUL_LOHI: case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: case ISD::UMUL_LOHI:
return lowerXMUL_LOHI(Op, DAG); return lowerXMUL_LOHI(Op, DAG);
case ISD::DYNAMIC_STACKALLOC: case ISD::DYNAMIC_STACKALLOC:
return LowerDYNAMIC_STACKALLOC(Op, DAG); return LowerDYNAMIC_STACKALLOC(Op, DAG);
case ISD::UADDO:
case ISD::USUBO:
return lowerUADDOSUBBO(Op, DAG);
} }
return SDValue(); return SDValue();
} }
// Used for D16: Casts the result of an instruction into the right vector, // Used for D16: Casts the result of an instruction into the right vector,
// packs values if loads return unpacked values. // packs values if loads return unpacked values.
static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT, static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
const SDLoc &DL, const SDLoc &DL,
▲ Show 20 Lines • Show All 621 Lines • ▼ Show 20 Lines if (Subtarget->hasSMulHi()) {
return SDValue(); return SDValue();
} }
// The multiply is uniform but we would have to use V_MUL_HI_[IU]32 to // The multiply is uniform but we would have to use V_MUL_HI_[IU]32 to
// calculate the high part, so we might as well do the whole thing with // calculate the high part, so we might as well do the whole thing with
// V_MAD_[IU]64_[IU]32. // V_MAD_[IU]64_[IU]32.
return Op; return Op;
} }
SDValue SITargetLowering::lowerUADDOSUBBO(SDValue Op, SelectionDAG &DAG) const {
arsenmUnsubmitted
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I don't see the point of this, you're just doing what the default legalization should do in 1 step instead of 2

arsenm: I don't see the point of this, you're just doing what the default legalization should do in 1…
SDValue Src1 = Op->getOperand(0);
SDValue Src2 = Op->getOperand(1);
SDLoc DL = SDLoc(Op);
auto ResOpc = (Op.getOpcode() == ISD::UADDO) ? ISD::ADDCARRY : ISD::SUBCARRY;
SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
SDValue One = DAG.getConstant(1, DL, MVT::i32);
SDValue VSrc1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Src1);
SDValue VSrc2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Src2);
SDValue Src1Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, VSrc1, Zero);
SDValue Src2Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, VSrc2, Zero);
SDValue ResLo = DAG.getNode(ResOpc, SDLoc(Op), {MVT::i32, MVT::i1}, {Src1Lo, Src2Lo, Zero});
SDValue Src1Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, VSrc1, One);
SDValue Src2Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, VSrc2, One);
SDValue ResHi = DAG.getNode(ResOpc, SDLoc(Op), {MVT::i32, MVT::i1}, {Src1Hi, Src2Hi, SDValue(ResLo.getNode(), 1)});
SDValue ResV = DAG.getBuildVector(MVT::v2i32, DL, {SDValue(ResLo.getNode(), 0), SDValue(ResHi.getNode(), 0)});
SDValue Res = DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), ResV);
return DAG.getMergeValues({Res, SDValue(ResHi.getNode(), 1)}, DL);
}
SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const { SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
if (!Subtarget->isTrapHandlerEnabled() || if (!Subtarget->isTrapHandlerEnabled() ||
Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA)
return lowerTrapEndpgm(Op, DAG); return lowerTrapEndpgm(Op, DAG);
if (std::optional<uint8_t> HsaAbiVer = AMDGPU::getHsaAbiVersion(Subtarget)) { if (std::optional<uint8_t> HsaAbiVer = AMDGPU::getHsaAbiVersion(Subtarget)) {
switch (*HsaAbiVer) { switch (*HsaAbiVer) {
case ELF::ELFABIVERSION_AMDGPU_HSA_V2: case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
▲ Show 20 Lines • Show All 7,892 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/carryout-selection.ll

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @uaddo32_vcc_user(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i32 %a, i32 %b) #0 {
store i32 %val, ptr addrspace(1) %out, align 4 store i32 %val, ptr addrspace(1) %out, align 4
store i1 %carry, ptr addrspace(1) %carryout store i1 %carry, ptr addrspace(1) %carryout
ret void ret void
} }
; GCN-ISEL-LABEL: name: suaddo64 ; GCN-ISEL-LABEL: name: suaddo64
; GCN-ISEL-LABEL: body: ; GCN-ISEL-LABEL: body:
; GCN-ISEL-LABEL: bb.0 ; GCN-ISEL-LABEL: bb.0
; GCN-ISEL: S_ADD_U64_PSEUDO ; GCN-ISEL: V_ADDC_U32_e64
; GCN-LABEL: @suaddo64 ; GCN-LABEL: @suaddo64
; ;
; GCN: s_add_u32 ; CISI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
; GCN: s_addc_u32 ; CISI: v_addc_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
;
; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
;
; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
;
; GFX10W32: v_add_co_u32 v{{[0-9]+}}, [[CARRY:vcc_lo]], s{{[0-9]+}}, s{{[0-9]+}}
; GFX10W64: v_add_co_u32 v{{[0-9]+}}, [[CARRY:vcc]], s{{[0-9]+}}, s{{[0-9]+}}
; GFX1010: v_add_co_ci_u32_e32 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, v{{[0-9]+}}, [[CARRY]]
; GFX1030: v_add_co_ci_u32_e32 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, v{{[0-9]+}}, [[CARRY]]
;
; GFX11: v_add_co_u32 v{{[0-9]+}}, [[CARRY:vcc_lo]], s{{[0-9]+}}, s{{[0-9]+}}
; GFX11: v_add_co_ci_u32_e32 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, v{{[0-9]+}}, [[CARRY]]
define amdgpu_kernel void @suaddo64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) #0 { define amdgpu_kernel void @suaddo64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) #0 {
%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue { i64, i1 } %uadd, 0 %val = extractvalue { i64, i1 } %uadd, 0
%carry = extractvalue { i64, i1 } %uadd, 1 %carry = extractvalue { i64, i1 } %uadd, 1
store i64 %val, ptr addrspace(1) %out, align 8 store i64 %val, ptr addrspace(1) %out, align 8
store i1 %carry, ptr addrspace(1) %carryout store i1 %carry, ptr addrspace(1) %carryout
ret void ret void
} }
; GCN-ISEL-LABEL: name: vuaddo64 ; GCN-ISEL-LABEL: name: vuaddo64
; GCN-ISEL-LABEL: body: ; GCN-ISEL-LABEL: body:
; GCN-ISEL-LABEL: bb.0 ; GCN-ISEL-LABEL: bb.0
; GCN-ISEL: V_ADD_U64_PSEUDO ; GCN-ISEL: V_ADDC_U32_e64
; GCN-LABEL: @vuaddo64 ; GCN-LABEL: @vuaddo64
; ;
; CISI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 ; CISI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
; CISI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc ; CISI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
; ;
; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 ; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc ; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
; ;
; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 ; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc ; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
; ;
; GFX10W32: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0 ; GFX10W32: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
; GFX10W64: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v0 ; GFX10W64: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v0
; GFX1010: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]] ; GFX1010: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY2:.+]], s{{[0-9]+}}, 0, [[CARRY]]
; GFX1030: v_add_co_ci_u32_e64 v{{[0-9]+}}, null, s{{[0-9]+}}, 0, [[CARRY]] ; GFX1030: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY2:.+]], s{{[0-9]+}}, 0, [[CARRY]]
; ;
; GFX11: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0 ; GFX11: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
; GFX11: v_add_co_ci_u32_e64 v{{[0-9]+}}, null, s{{[0-9]+}}, 0, [[CARRY]] ; GFX11: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]]
define amdgpu_kernel void @vuaddo64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a) #0 { define amdgpu_kernel void @vuaddo64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a) #0 {
arsenmUnsubmitted
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In a precommit can you convert this to generated checks? It's hard to see what's going on here

arsenm: In a precommit can you convert this to generated checks? It's hard to see what's going on here
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %tid.ext) %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %tid.ext)
%val = extractvalue { i64, i1 } %uadd, 0 %val = extractvalue { i64, i1 } %uadd, 0
%carry = extractvalue { i64, i1 } %uadd, 1 %carry = extractvalue { i64, i1 } %uadd, 1
store i64 %val, ptr addrspace(1) %out, align 8 store i64 %val, ptr addrspace(1) %out, align 8
store i1 %carry, ptr addrspace(1) %carryout store i1 %carry, ptr addrspace(1) %carryout
ret void ret void
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @usubo32_vcc_user(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i32 %a, i32 %b) #0 {
store i32 %val, ptr addrspace(1) %out, align 4 store i32 %val, ptr addrspace(1) %out, align 4
store i1 %carry, ptr addrspace(1) %carryout store i1 %carry, ptr addrspace(1) %carryout
ret void ret void
} }
; GCN-ISEL-LABEL: name: susubo64 ; GCN-ISEL-LABEL: name: susubo64
; GCN-ISEL-LABEL: body: ; GCN-ISEL-LABEL: body:
; GCN-ISEL-LABEL: bb.0 ; GCN-ISEL-LABEL: bb.0
; GCN-ISEL: S_SUB_U64_PSEUDO ; GCN-ISEL: V_SUBB_U32_e64
; GCN-LABEL: @susubo64 ; GCN-LABEL: @susubo64
; ;
; GCN: s_sub_u32 ; CISI: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
; GCN: s_subb_u32 ; CISI: v_subb_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
;
; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
;
; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
;
; GFX10W32: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:vcc_lo]], s{{[0-9]+}}, s{{[0-9]+}}
; GFX10W64: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:vcc]], s{{[0-9]+}}, s{{[0-9]+}}
; GFX1010: v_sub_co_ci_u32_e32 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, v{{[0-9]+}}, [[CARRY]]
; GFX1030: v_sub_co_ci_u32_e32 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, v{{[0-9]+}}, [[CARRY]]
;
; GFX11: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:vcc_lo]], s{{[0-9]+}}, s{{[0-9]+}}
; GFX11: v_sub_co_ci_u32_e32 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, v{{[0-9]+}}, [[CARRY]]
define amdgpu_kernel void @susubo64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) #0 { define amdgpu_kernel void @susubo64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) #0 {
%usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue { i64, i1 } %usub, 0 %val = extractvalue { i64, i1 } %usub, 0
%carry = extractvalue { i64, i1 } %usub, 1 %carry = extractvalue { i64, i1 } %usub, 1
store i64 %val, ptr addrspace(1) %out, align 8 store i64 %val, ptr addrspace(1) %out, align 8
store i1 %carry, ptr addrspace(1) %carryout store i1 %carry, ptr addrspace(1) %carryout
ret void ret void
} }
; GCN-ISEL-LABEL: name: vusubo64 ; GCN-ISEL-LABEL: name: vusubo64
; GCN-ISEL-LABEL: body: ; GCN-ISEL-LABEL: body:
; GCN-ISEL-LABEL: bb.0 ; GCN-ISEL-LABEL: bb.0
; GCN-ISEL: V_SUB_U64_PSEUDO ; GCN-ISEL: V_SUBB_U32_e64
; GCN-LABEL: @vusubo64 ; GCN-LABEL: @vusubo64
; ;
; CISI: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 ; CISI: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
; CISI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc ; CISI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
; ;
; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 ; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
; VI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc ; VI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
; ;
; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0 ; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc ; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
; ;
; GFX10W32: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0 ; GFX10W32: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
; GFX10W64: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v0 ; GFX10W64: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v0
; GFX1010: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]] ; GFX1010: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY2:.+]], s{{[0-9]+}}, 0, [[CARRY]]
; GFX1030: v_sub_co_ci_u32_e64 v{{[0-9]+}}, null, s{{[0-9]+}}, 0, [[CARRY]] ; GFX1030: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY2:.+]], s{{[0-9]+}}, 0, [[CARRY]]
; ;
; GFX11: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0 ; GFX11: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
; GFX11: v_sub_co_ci_u32_e64 v{{[0-9]+}}, null, s{{[0-9]+}}, 0, [[CARRY]] ; GFX11: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]]
define amdgpu_kernel void @vusubo64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a) #0 { define amdgpu_kernel void @vusubo64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %tid.ext) %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %tid.ext)
%val = extractvalue { i64, i1 } %usub, 0 %val = extractvalue { i64, i1 } %usub, 0
%carry = extractvalue { i64, i1 } %usub, 1 %carry = extractvalue { i64, i1 } %usub, 1
store i64 %val, ptr addrspace(1) %out, align 8 store i64 %val, ptr addrspace(1) %out, align 8
store i1 %carry, ptr addrspace(1) %carryout store i1 %carry, ptr addrspace(1) %carryout
Show All 31 Lines

llvm/test/CodeGen/AMDGPU/sdiv64.ll

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_sdiv: ; GCN-IR-LABEL: s_test_sdiv:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; GCN-IR-NEXT: s_mov_b32 s15, 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i32 s0, s7, 31 ; GCN-IR-NEXT: s_ashr_i32 s0, s7, 31
; GCN-IR-NEXT: s_mov_b32 s1, s0 ; GCN-IR-NEXT: s_mov_b32 s1, s0
; GCN-IR-NEXT: s_ashr_i32 s2, s9, 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s9, 31
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], s[6:7] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], s[6:7]
; GCN-IR-NEXT: s_mov_b32 s3, s2 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_sub_u32 s12, s6, s0 ; GCN-IR-NEXT: s_sub_u32 s10, s6, s0
; GCN-IR-NEXT: s_subb_u32 s13, s7, s0 ; GCN-IR-NEXT: s_subb_u32 s11, s7, s0
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[8:9] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s6, s6, s2 ; GCN-IR-NEXT: s_sub_u32 s8, s6, s2
; GCN-IR-NEXT: s_subb_u32 s7, s7, s2 ; GCN-IR-NEXT: s_subb_u32 s9, s7, s2
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[12:13], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[8:9], 0
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[8:9] ; GCN-IR-NEXT: s_flbit_i32_b32 s14, s11
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s8
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_min_u32 s14, s8, s9 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s9
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s12 ; GCN-IR-NEXT: s_min_u32 s6, s6, s7
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s10
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s13 ; GCN-IR-NEXT: s_add_i32 s7, s7, 32
; GCN-IR-NEXT: s_min_u32 s18, s8, s9 ; GCN-IR-NEXT: s_min_u32 s14, s7, s14
; GCN-IR-NEXT: s_sub_u32 s16, s14, s18 ; GCN-IR-NEXT: s_sub_u32 s16, s6, s14
; GCN-IR-NEXT: s_subb_u32 s17, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s17, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[16:17], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[16:17], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[16:17], 63
; GCN-IR-NEXT: s_or_b64 s[20:21], s[10:11], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[12:13], s[18:19]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[20:21], exec ; GCN-IR-NEXT: s_and_b64 s[12:13], s[18:19], exec
; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13 ; GCN-IR-NEXT: s_cselect_b32 s13, 0, s11
; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12 ; GCN-IR-NEXT: s_cselect_b32 s12, 0, s10
; GCN-IR-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21]
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[20:21] ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s20, s16, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s17
; GCN-IR-NEXT: s_addc_u32 s21, s17, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s16, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[20:21], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s16, 63, s16 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s16
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: v_readfirstlane_b32 s15, v1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[10:11], s12
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s20 ; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[10:11], s15
; GCN-IR-NEXT: s_add_u32 s19, s6, -1 ; GCN-IR-NEXT: s_add_u32 s15, s8, -1
; GCN-IR-NEXT: s_addc_u32 s20, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s18, s9, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15] ; GCN-IR-NEXT: s_not_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_add_u32 s12, s8, s18 ; GCN-IR-NEXT: s_add_u32 s20, s10, s14
; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s21, s11, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s20
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s21
; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s13, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[10:11], s[12:13]
; GCN-IR-NEXT: s_sub_u32 s8, s19, s16 ; GCN-IR-NEXT: s_sub_u32 s6, s15, s16
; GCN-IR-NEXT: s_subb_u32 s8, s20, s17 ; GCN-IR-NEXT: s_subb_u32 s6, s18, s17
; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s8, s14, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b32 s6, s10, 1
; GCN-IR-NEXT: s_sub_u32 s16, s16, s14 ; GCN-IR-NEXT: s_and_b64 s[20:21], s[10:11], s[8:9]
; GCN-IR-NEXT: s_subb_u32 s17, s17, s15 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s12, s12, 1 ; GCN-IR-NEXT: s_sub_u32 s16, s16, s20
; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[12:13], 0 ; GCN-IR-NEXT: s_subb_u32 s17, s17, s21
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[22:23]
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: .LBB0_4: ; %Flow6 ; GCN-IR-NEXT: s_branch .LBB0_5
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1 ; GCN-IR-NEXT: .LBB0_4:
; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7] ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: .LBB0_5: ; %udiv-end ; GCN-IR-NEXT: .LBB0_5: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[6:7], s[8:9]
; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[12:13], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s0, s2, s0 ; GCN-IR-NEXT: s_sub_u32 s0, s2, s0
; GCN-IR-NEXT: s_subb_u32 s1, s3, s1 ; GCN-IR-NEXT: s_subb_u32 s1, s3, s1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v12, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v12, v2, v3
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v10 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v10
; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v11 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v11
; GCN-IR-NEXT: v_min_u32_e32 v13, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v13, v2, v3
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[6:7], v12, v13 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[6:7], v12, v13
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
; GCN-IR-NEXT: v_subb_u32_e64 v3, s[6:7], 0, 0, s[6:7] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[6:7], 0, 0, s[6:7]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[2:3] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[8:9]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[8:9]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v6, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v4
; GCN-IR-NEXT: v_mov_b32_e32 v7, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v5
; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v11, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v11, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v8, v10, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v10, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v8
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v8
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[10:11], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[10:11], v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_not_b32_e32 v9, v12 ; GCN-IR-NEXT: v_not_b32_e32 v9, v12
; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[10:11], v14 ; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[10:11], v14
; GCN-IR-NEXT: v_not_b32_e32 v8, 0 ; GCN-IR-NEXT: v_not_b32_e32 v8, 0
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v9, v13 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v9, v13
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 ; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8 ; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v16, v14 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v16, v14
; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v17, v15, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v17, v15, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v8 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v8
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3
; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1
; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0
; GCN-IR-NEXT: v_sub_i32_e32 v14, vcc, v14, v12
; GCN-IR-NEXT: v_subb_u32_e32 v15, vcc, v15, v13, vcc
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v14, v12
; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v13, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v13, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v9
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v8
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v1 ; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v1
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 ; GCN-IR-NEXT: v_or_b32_e32 v3, v8, v0
; GCN-IR-NEXT: .LBB1_6: ; %Flow4 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v4 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v4
; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v6 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v6
; GCN-IR-NEXT: v_xor_b32_e32 v3, v8, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v3, v0
; GCN-IR-NEXT: v_xor_b32_e32 v2, v9, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v2, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, %y %result = sdiv i64 %x, %y
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_sdiv24_64(ptr addrspace(1) %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_sdiv24_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
▲ Show 20 Lines • Show All 499 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4 ; GCN-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_sdiv24_48: ; GCN-IR-LABEL: s_test_sdiv24_48:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GCN-IR-NEXT: s_mov_b32 s15, 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_sext_i32_i16 s5, s5 ; GCN-IR-NEXT: s_sext_i32_i16 s5, s5
; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[4:5], 24 ; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[4:5], 24
; GCN-IR-NEXT: s_sext_i32_i16 s7, s7 ; GCN-IR-NEXT: s_sext_i32_i16 s7, s7
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 16 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 24 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 24
; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 16 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 16
; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31
; GCN-IR-NEXT: s_lshl_b64 s[4:5], s[4:5], 16 ; GCN-IR-NEXT: s_lshl_b64 s[4:5], s[4:5], 16
; GCN-IR-NEXT: s_mov_b32 s3, s2 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 16 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 16
; GCN-IR-NEXT: s_ashr_i32 s4, s5, 31 ; GCN-IR-NEXT: s_ashr_i32 s4, s5, 31
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[6:7] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[6:7]
; GCN-IR-NEXT: s_mov_b32 s5, s4 ; GCN-IR-NEXT: s_mov_b32 s5, s4
; GCN-IR-NEXT: s_sub_u32 s12, s6, s2 ; GCN-IR-NEXT: s_sub_u32 s10, s6, s2
; GCN-IR-NEXT: s_subb_u32 s13, s7, s2 ; GCN-IR-NEXT: s_subb_u32 s11, s7, s2
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], s[8:9] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s6, s6, s4 ; GCN-IR-NEXT: s_sub_u32 s8, s6, s4
; GCN-IR-NEXT: s_subb_u32 s7, s7, s4 ; GCN-IR-NEXT: s_subb_u32 s9, s7, s4
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[12:13], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] ; GCN-IR-NEXT: s_flbit_i32_b32 s14, s11
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[6:7], s[12:13]
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s8
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_min_u32 s14, s8, s9 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s9
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s12 ; GCN-IR-NEXT: s_min_u32 s6, s6, s7
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s10
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s13 ; GCN-IR-NEXT: s_add_i32 s7, s7, 32
; GCN-IR-NEXT: s_min_u32 s18, s8, s9 ; GCN-IR-NEXT: s_min_u32 s14, s7, s14
; GCN-IR-NEXT: s_sub_u32 s16, s14, s18 ; GCN-IR-NEXT: s_sub_u32 s16, s6, s14
; GCN-IR-NEXT: s_subb_u32 s17, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s17, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[16:17], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[16:17], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[16:17], 63
; GCN-IR-NEXT: s_or_b64 s[20:21], s[10:11], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[12:13], s[18:19]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[20:21], exec ; GCN-IR-NEXT: s_and_b64 s[12:13], s[18:19], exec
; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13 ; GCN-IR-NEXT: s_cselect_b32 s13, 0, s11
; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12 ; GCN-IR-NEXT: s_cselect_b32 s12, 0, s10
; GCN-IR-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21]
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[20:21] ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s20, s16, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s17
; GCN-IR-NEXT: s_addc_u32 s21, s17, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s16, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[20:21], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s16, 63, s16 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s16
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: v_readfirstlane_b32 s15, v1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[10:11], s12
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s20 ; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[10:11], s15
; GCN-IR-NEXT: s_add_u32 s19, s6, -1 ; GCN-IR-NEXT: s_add_u32 s15, s8, -1
; GCN-IR-NEXT: s_addc_u32 s20, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s18, s9, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15] ; GCN-IR-NEXT: s_not_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_add_u32 s12, s8, s18 ; GCN-IR-NEXT: s_add_u32 s20, s10, s14
; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s21, s11, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s20
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s21
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s13, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[10:11], s[12:13]
; GCN-IR-NEXT: s_sub_u32 s8, s19, s16 ; GCN-IR-NEXT: s_sub_u32 s6, s15, s16
; GCN-IR-NEXT: s_subb_u32 s8, s20, s17 ; GCN-IR-NEXT: s_subb_u32 s6, s18, s17
; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s8, s14, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b32 s6, s10, 1
; GCN-IR-NEXT: s_sub_u32 s16, s16, s14 ; GCN-IR-NEXT: s_and_b64 s[20:21], s[10:11], s[8:9]
; GCN-IR-NEXT: s_subb_u32 s17, s17, s15 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s12, s12, 1 ; GCN-IR-NEXT: s_sub_u32 s16, s16, s20
; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[12:13], 0 ; GCN-IR-NEXT: s_subb_u32 s17, s17, s21
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[22:23]
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3
; GCN-IR-NEXT: .LBB9_4: ; %Flow3 ; GCN-IR-NEXT: s_branch .LBB9_5
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1 ; GCN-IR-NEXT: .LBB9_4:
; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7] ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: .LBB9_5: ; %udiv-end ; GCN-IR-NEXT: .LBB9_5: ; %Flow3
; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[12:13], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[6:7], s[8:9]
; GCN-IR-NEXT: .LBB9_6: ; %udiv-end
; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[4:5], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[4:5], s[2:3]
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[12:13], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s0, s2, s0 ; GCN-IR-NEXT: s_sub_u32 s0, s2, s0
; GCN-IR-NEXT: s_subb_u32 s1, s3, s1 ; GCN-IR-NEXT: s_subb_u32 s1, s3, s1
; GCN-IR-NEXT: s_mov_b32 s15, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
; GCN-IR-NEXT: s_mov_b32 s14, -1 ; GCN-IR-NEXT: s_mov_b32 s10, -1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: buffer_store_short v0, off, s[12:15], 0 offset:4 ; GCN-IR-NEXT: buffer_store_short v0, off, s[8:11], 0 offset:4
; GCN-IR-NEXT: s_waitcnt expcnt(0) ; GCN-IR-NEXT: s_waitcnt expcnt(0)
; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
; GCN-IR-NEXT: buffer_store_dword v0, off, s[12:15], 0 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[8:11], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = ashr i48 %x, 24 %1 = ashr i48 %x, 24
%2 = ashr i48 %y, 24 %2 = ashr i48 %y, 24
%result = sdiv i48 %1, %2 %result = sdiv i48 %1, %2
store i48 %result, ptr addrspace(1) %out store i48 %result, ptr addrspace(1) %out
ret void ret void
} }
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_sdiv_k_num_i64: ; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31
; GCN-IR-NEXT: s_mov_b32 s5, s4 ; GCN-IR-NEXT: s_mov_b32 s5, s4
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s2, s2, s4 ; GCN-IR-NEXT: s_sub_u32 s2, s2, s4
; GCN-IR-NEXT: s_subb_u32 s3, s3, s4 ; GCN-IR-NEXT: s_subb_u32 s3, s3, s4
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3
; GCN-IR-NEXT: s_min_u32 s10, s10, s11 ; GCN-IR-NEXT: s_min_u32 s10, s8, s9
; GCN-IR-NEXT: s_add_u32 s12, s10, 0xffffffc5 ; GCN-IR-NEXT: s_add_u32 s8, s10, 0xffffffc5
; GCN-IR-NEXT: s_addc_u32 s13, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[8:9], 63
; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[6:7], s[12:13]
; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[12:13], exec
; GCN-IR-NEXT: s_cselect_b32 s8, 0, 24 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s14, s12, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: s_addc_u32 s15, s13, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s8, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s11, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: v_readfirstlane_b32 s6, v1
; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s11 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s14 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s6
; GCN-IR-NEXT: s_add_u32 s16, s2, -1 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
; GCN-IR-NEXT: s_addc_u32 s17, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
; GCN-IR-NEXT: s_sub_u32 s10, 58, s10 ; GCN-IR-NEXT: s_sub_u32 s16, 58, s10
; GCN-IR-NEXT: s_subb_u32 s11, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s17, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s16
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s17
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s6, s16, s12 ; GCN-IR-NEXT: s_sub_u32 s6, s14, s12
; GCN-IR-NEXT: s_subb_u32 s6, s17, s13 ; GCN-IR-NEXT: s_subb_u32 s6, s15, s13
; GCN-IR-NEXT: s_ashr_i32 s14, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s6, s14, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[2:3] ; GCN-IR-NEXT: s_and_b32 s6, s10, 1
; GCN-IR-NEXT: s_sub_u32 s12, s12, s14 ; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[2:3]
; GCN-IR-NEXT: s_subb_u32 s13, s13, s15 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s10, s10, 1 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[10:11], 0 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3
; GCN-IR-NEXT: .LBB10_4: ; %Flow5 ; GCN-IR-NEXT: s_branch .LBB10_5
; GCN-IR-NEXT: .LBB10_4:
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: .LBB10_5: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
; GCN-IR-NEXT: .LBB10_5: ; %udiv-end ; GCN-IR-NEXT: .LBB10_6: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s4, s6, s4 ; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
; GCN-IR-NEXT: s_subb_u32 s5, s7, s5 ; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_mov_b32_e32 v1, s5 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[5:6] ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[5:6]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, 24, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, 24, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], s[6:7]
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10] ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 63, v5
; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v9 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v9
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 58, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 58, v8
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1
; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0
; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v10, v12
; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v11, v13, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB11_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB11_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v6, v0 ; GCN-IR-NEXT: v_or_b32_e32 v7, v6, v0
; GCN-IR-NEXT: .LBB11_6: ; %Flow4 ; GCN-IR-NEXT: .LBB11_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v7, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v7, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 24, %x %result = sdiv i64 24, %x
ret i64 %result ret i64 %result
} }
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0x8000 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0x8000
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6]
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0x8000
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[8:9], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5 ; GCN-IR-NEXT: s_xor_b64 s[10:11], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10] ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 63, v5
; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[8:9], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[6:7], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v9 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[10:11], v9
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1
; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0
; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v10, v12
; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v11, v13, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v6, v0 ; GCN-IR-NEXT: v_or_b32_e32 v7, v6, v0
; GCN-IR-NEXT: .LBB12_6: ; %Flow4 ; GCN-IR-NEXT: .LBB12_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v7, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v7, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 32768, %x %result = sdiv i64 32768, %x
ret i64 %result ret i64 %result
} }
Show All 26 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[3:4] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v3
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v3 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10] ; GCN-IR-NEXT: v_sub_i32_e32 v3, vcc, 63, v3
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[7:8], v3 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[7:8], v3
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v0
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[7:8], v9
; GCN-IR-NEXT: v_addc_u32_e64 v7, s[10:11], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s10, 0x7fff
; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v5, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v5
; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0
; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v7
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v5 ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s10, v8
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v9 ; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v5
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v10
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_and_b32_e32 v10, 0x8000, v10
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v8, v10
; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9 ; GCN-IR-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5] ; GCN-IR-NEXT: v_or_b32_e32 v4, v11, v4
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB13_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB13_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: .LBB13_6: ; %Flow4 ; GCN-IR-NEXT: .LBB13_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2
; GCN-IR-NEXT: v_xor_b32_e32 v3, v6, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v6, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, 32768 %result = sdiv i64 %x, 32768
ret i64 %result ret i64 %result
} }
▲ Show 20 Lines • Show All 242 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/srem64.ll

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GCN-IR-LABEL: s_test_srem: ; GCN-IR-LABEL: s_test_srem:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[4:5], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[4:5], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s2
; GCN-IR-NEXT: s_min_u32 s10, s10, s11 ; GCN-IR-NEXT: s_min_u32 s6, s10, s11
; GCN-IR-NEXT: s_min_u32 s14, s6, s7 ; GCN-IR-NEXT: s_add_i32 s7, s7, 32
; GCN-IR-NEXT: s_sub_u32 s12, s10, s14 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s3
; GCN-IR-NEXT: s_min_u32 s10, s7, s10
; GCN-IR-NEXT: s_sub_u32 s12, s6, s10
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
; GCN-IR-NEXT: s_or_b64 s[16:17], s[8:9], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
; GCN-IR-NEXT: s_and_b64 s[8:9], s[16:17], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_6
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s12, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[16:17], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: v_readfirstlane_b32 s11, v1
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s16 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s11
; GCN-IR-NEXT: s_add_u32 s16, s4, -1 ; GCN-IR-NEXT: s_add_u32 s14, s4, -1
; GCN-IR-NEXT: s_addc_u32 s17, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s5, -1
; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[16:17], s[6:7]
; GCN-IR-NEXT: s_add_u32 s10, s6, s14 ; GCN-IR-NEXT: s_add_u32 s16, s16, s10
; GCN-IR-NEXT: s_addc_u32 s11, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s17, s17, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s16
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s17
; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s6, s16, s12 ; GCN-IR-NEXT: s_sub_u32 s6, s14, s12
; GCN-IR-NEXT: s_subb_u32 s6, s17, s13 ; GCN-IR-NEXT: s_subb_u32 s6, s15, s13
; GCN-IR-NEXT: s_ashr_i32 s14, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s6, s14, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[4:5] ; GCN-IR-NEXT: s_and_b32 s6, s10, 1
; GCN-IR-NEXT: s_sub_u32 s12, s12, s14 ; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[4:5]
; GCN-IR-NEXT: s_subb_u32 s13, s13, s15 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s10, s10, 1 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[10:11], 0 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: .LBB0_4: ; %Flow6 ; GCN-IR-NEXT: s_branch .LBB0_5
; GCN-IR-NEXT: .LBB0_4:
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: .LBB0_5: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: .LBB0_5: ; %udiv-end ; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0
; GCN-IR-NEXT: s_mov_b32 s12, s0 ; GCN-IR-NEXT: s_mov_b32 s12, s0
; GCN-IR-NEXT: s_mul_i32 s0, s4, s9 ; GCN-IR-NEXT: s_mul_i32 s0, s4, s9
; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GCN-IR-NEXT: s_mul_i32 s0, s5, s8 ; GCN-IR-NEXT: s_mul_i32 s0, s5, s8
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0
▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[7:8] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[7:8]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[7:8]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v5, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v4
; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v7 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v7
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], 63, v7 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 63, v7
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[0:1], v6 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[0:1], v6
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v9, v10 ; GCN-IR-NEXT: v_not_b32_e32 v9, v10
; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12 ; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12
; GCN-IR-NEXT: v_not_b32_e32 v8, 0 ; GCN-IR-NEXT: v_not_b32_e32 v8, 0
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v9, v11 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v9, v11
; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v14, 0
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v15, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 ; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v7 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v7
; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v8 ; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v8
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v16, v12 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v16, v12
; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v17, v13, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v17, v13, vcc
; GCN-IR-NEXT: v_or_b32_e32 v6, v14, v6 ; GCN-IR-NEXT: v_or_b32_e32 v6, v14, v6
; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v8 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v8
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
; GCN-IR-NEXT: v_or_b32_e32 v7, v15, v7 ; GCN-IR-NEXT: v_or_b32_e32 v7, v15, v7
; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v14 ; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v14
; GCN-IR-NEXT: v_and_b32_e32 v15, v14, v3 ; GCN-IR-NEXT: v_and_b32_e32 v15, v14, v3
; GCN-IR-NEXT: v_and_b32_e32 v14, v14, v2 ; GCN-IR-NEXT: v_and_b32_e32 v14, v14, v2
; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v14
; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v15, vcc
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v14
; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v15, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v15, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v15, v9
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v14, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v14, v8
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v7 ; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v7
; GCN-IR-NEXT: v_or_b32_e32 v6, v8, v6 ; GCN-IR-NEXT: v_or_b32_e32 v6, v8, v6
; GCN-IR-NEXT: .LBB1_6: ; %Flow4 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mul_lo_u32 v7, v2, v9 ; GCN-IR-NEXT: v_mul_lo_u32 v7, v2, v9
; GCN-IR-NEXT: v_mul_hi_u32 v8, v2, v6 ; GCN-IR-NEXT: v_mul_hi_u32 v8, v2, v6
; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v7, v3 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v7, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
▲ Show 20 Lines • Show All 569 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_srem33_64: ; GCN-IR-LABEL: s_test_srem33_64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN-IR-NEXT: s_mov_b32 s13, 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[6:7], 31 ; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[6:7], 31
; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[0:1], 31 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[0:1], 31
; GCN-IR-NEXT: s_ashr_i32 s0, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s0, s3, 31
; GCN-IR-NEXT: s_ashr_i32 s10, s7, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s7, 31
; GCN-IR-NEXT: s_mov_b32 s1, s0 ; GCN-IR-NEXT: s_mov_b32 s1, s0
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s2, s2, s0 ; GCN-IR-NEXT: s_sub_u32 s2, s2, s0
; GCN-IR-NEXT: s_subb_u32 s3, s3, s0 ; GCN-IR-NEXT: s_subb_u32 s3, s3, s0
; GCN-IR-NEXT: s_sub_u32 s8, s6, s10 ; GCN-IR-NEXT: s_sub_u32 s8, s6, s10
; GCN-IR-NEXT: s_subb_u32 s9, s7, s10 ; GCN-IR-NEXT: s_subb_u32 s9, s7, s10
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s12, s3
; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s8 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s8
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s9 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s9
; GCN-IR-NEXT: s_min_u32 s12, s6, s7 ; GCN-IR-NEXT: s_min_u32 s6, s6, s7
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s2
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s7, s7, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_min_u32 s12, s7, s12
; GCN-IR-NEXT: s_min_u32 s16, s6, s7 ; GCN-IR-NEXT: s_sub_u32 s14, s6, s12
; GCN-IR-NEXT: s_sub_u32 s14, s12, s16
; GCN-IR-NEXT: s_subb_u32 s15, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[14:15], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[14:15], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[14:15], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[14:15], 63
; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[10:11], s[16:17]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec ; GCN-IR-NEXT: s_and_b64 s[10:11], s[16:17], exec
; GCN-IR-NEXT: s_cselect_b32 s11, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s11, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s10, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s10, 0, s2
; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19] ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s18, s14, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s15
; GCN-IR-NEXT: s_addc_u32 s19, s15, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s14, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s14, 63, s14 ; GCN-IR-NEXT: s_sub_i32 s10, 63, s14
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: v_readfirstlane_b32 s13, v1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[2:3], s14 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[2:3], s18 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[2:3], s13
; GCN-IR-NEXT: s_add_u32 s18, s8, -1 ; GCN-IR-NEXT: s_add_u32 s16, s8, -1
; GCN-IR-NEXT: s_addc_u32 s19, s9, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s9, -1
; GCN-IR-NEXT: s_not_b64 s[6:7], s[12:13] ; GCN-IR-NEXT: s_not_b64 s[18:19], s[6:7]
; GCN-IR-NEXT: s_add_u32 s12, s6, s16 ; GCN-IR-NEXT: s_add_u32 s18, s18, s12
; GCN-IR-NEXT: s_addc_u32 s13, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s19, s19, 0
; GCN-IR-NEXT: s_mov_b64 s[16:17], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s18
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s19
; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[16:17], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s6, s18, s14 ; GCN-IR-NEXT: s_sub_u32 s6, s16, s14
; GCN-IR-NEXT: s_subb_u32 s6, s19, s15 ; GCN-IR-NEXT: s_subb_u32 s6, s17, s15
; GCN-IR-NEXT: s_ashr_i32 s16, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s12, s6, 31
; GCN-IR-NEXT: s_mov_b32 s17, s16 ; GCN-IR-NEXT: s_mov_b32 s13, s12
; GCN-IR-NEXT: s_and_b32 s6, s16, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[16:17], s[16:17], s[8:9] ; GCN-IR-NEXT: s_and_b32 s6, s12, 1
; GCN-IR-NEXT: s_sub_u32 s14, s14, s16 ; GCN-IR-NEXT: s_and_b64 s[18:19], s[12:13], s[8:9]
; GCN-IR-NEXT: s_subb_u32 s15, s15, s17 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s12, s12, 1 ; GCN-IR-NEXT: s_sub_u32 s14, s14, s18
; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[6:7]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0 ; GCN-IR-NEXT: s_subb_u32 s15, s15, s19
; GCN-IR-NEXT: s_mov_b64 s[16:17], s[6:7] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21]
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_3
; GCN-IR-NEXT: .LBB8_4: ; %Flow6 ; GCN-IR-NEXT: s_branch .LBB8_5
; GCN-IR-NEXT: .LBB8_4:
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: .LBB8_5: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GCN-IR-NEXT: .LBB8_5: ; %udiv-end ; GCN-IR-NEXT: .LBB8_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: v_mul_hi_u32 v0, s8, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s8, v0
; GCN-IR-NEXT: s_mul_i32 s11, s8, s11 ; GCN-IR-NEXT: s_mul_i32 s11, s8, s11
; GCN-IR-NEXT: s_mul_i32 s9, s9, s10 ; GCN-IR-NEXT: s_mul_i32 s9, s9, s10
; GCN-IR-NEXT: s_mul_i32 s8, s8, s10 ; GCN-IR-NEXT: s_mul_i32 s8, s8, s10
; GCN-IR-NEXT: v_readfirstlane_b32 s12, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s11, v0
; GCN-IR-NEXT: s_add_i32 s11, s12, s11 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s9, v0
; GCN-IR-NEXT: s_add_i32 s11, s11, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: s_sub_u32 s2, s2, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
; GCN-IR-NEXT: s_subb_u32 s3, s3, s11 ; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] ; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc
; GCN-IR-NEXT: s_sub_u32 s0, s2, s0 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s0, v1
; GCN-IR-NEXT: s_subb_u32 s1, s3, s1 ; GCN-IR-NEXT: v_xor_b32_e32 v2, s1, v0
; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s1
; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v1
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v3, vcc
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 31 %1 = ashr i64 %x, 31
%2 = ashr i64 %y, 31 %2 = ashr i64 %y, 31
%result = srem i64 %1, %2 %result = srem i64 %1, %2
store i64 %result, ptr addrspace(1) %out store i64 %result, ptr addrspace(1) %out
ret void ret void
} }
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4 ; GCN-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_srem24_48: ; GCN-IR-LABEL: s_test_srem24_48:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GCN-IR-NEXT: s_mov_b32 s13, 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_sext_i32_i16 s5, s5 ; GCN-IR-NEXT: s_sext_i32_i16 s5, s5
; GCN-IR-NEXT: s_sext_i32_i16 s7, s7 ; GCN-IR-NEXT: s_sext_i32_i16 s7, s7
; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[4:5], 24 ; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[4:5], 24
; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 24 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 24
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 16 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GCN-IR-NEXT: s_lshl_b64 s[4:5], s[4:5], 16 ; GCN-IR-NEXT: s_lshl_b64 s[4:5], s[4:5], 16
; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 16 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 16
; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31
; GCN-IR-NEXT: s_ashr_i32 s10, s5, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s5, 31
; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 16 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 16
; GCN-IR-NEXT: s_mov_b32 s3, s2 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[6:7], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[6:7], s[2:3]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[10:11] ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s4, s4, s2 ; GCN-IR-NEXT: s_sub_u32 s4, s4, s2
; GCN-IR-NEXT: s_subb_u32 s5, s5, s2 ; GCN-IR-NEXT: s_subb_u32 s5, s5, s2
; GCN-IR-NEXT: s_sub_u32 s6, s6, s10 ; GCN-IR-NEXT: s_sub_u32 s6, s6, s10
; GCN-IR-NEXT: s_subb_u32 s7, s7, s10 ; GCN-IR-NEXT: s_subb_u32 s7, s7, s10
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[4:5], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[4:5], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s12, s5
; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_min_u32 s12, s8, s9 ; GCN-IR-NEXT: s_min_u32 s8, s8, s9
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s4
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s9, s9, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s5 ; GCN-IR-NEXT: s_min_u32 s12, s9, s12
; GCN-IR-NEXT: s_min_u32 s16, s8, s9 ; GCN-IR-NEXT: s_sub_u32 s14, s8, s12
; GCN-IR-NEXT: s_sub_u32 s14, s12, s16
; GCN-IR-NEXT: s_subb_u32 s15, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[14:15], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[14:15], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[14:15], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[14:15], 63
; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[10:11], s[16:17]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec ; GCN-IR-NEXT: s_and_b64 s[10:11], s[16:17], exec
; GCN-IR-NEXT: s_cselect_b32 s11, 0, s5 ; GCN-IR-NEXT: s_cselect_b32 s11, 0, s5
; GCN-IR-NEXT: s_cselect_b32 s10, 0, s4 ; GCN-IR-NEXT: s_cselect_b32 s10, 0, s4
; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19] ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s18, s14, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s15
; GCN-IR-NEXT: s_addc_u32 s19, s15, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s14, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s14, 63, s14 ; GCN-IR-NEXT: s_sub_i32 s10, 63, s14
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: v_readfirstlane_b32 s13, v1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[4:5], s14 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[4:5], s10
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[4:5], s18 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[4:5], s13
; GCN-IR-NEXT: s_add_u32 s18, s6, -1 ; GCN-IR-NEXT: s_add_u32 s16, s6, -1
; GCN-IR-NEXT: s_addc_u32 s19, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s7, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[12:13] ; GCN-IR-NEXT: s_not_b64 s[18:19], s[8:9]
; GCN-IR-NEXT: s_add_u32 s12, s8, s16 ; GCN-IR-NEXT: s_add_u32 s18, s18, s12
; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s19, s19, 0
; GCN-IR-NEXT: s_mov_b64 s[16:17], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s18
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s19
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[16:17], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s8, s18, s14 ; GCN-IR-NEXT: s_sub_u32 s8, s16, s14
; GCN-IR-NEXT: s_subb_u32 s8, s19, s15 ; GCN-IR-NEXT: s_subb_u32 s8, s17, s15
; GCN-IR-NEXT: s_ashr_i32 s16, s8, 31 ; GCN-IR-NEXT: s_ashr_i32 s12, s8, 31
; GCN-IR-NEXT: s_mov_b32 s17, s16 ; GCN-IR-NEXT: s_mov_b32 s13, s12
; GCN-IR-NEXT: s_and_b32 s8, s16, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[16:17], s[16:17], s[6:7] ; GCN-IR-NEXT: s_and_b32 s8, s12, 1
; GCN-IR-NEXT: s_sub_u32 s14, s14, s16 ; GCN-IR-NEXT: s_and_b64 s[18:19], s[12:13], s[6:7]
; GCN-IR-NEXT: s_subb_u32 s15, s15, s17 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s12, s12, 1 ; GCN-IR-NEXT: s_sub_u32 s14, s14, s18
; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[8:9]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0 ; GCN-IR-NEXT: s_subb_u32 s15, s15, s19
; GCN-IR-NEXT: s_mov_b64 s[16:17], s[8:9] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21]
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3
; GCN-IR-NEXT: .LBB9_4: ; %Flow3 ; GCN-IR-NEXT: s_branch .LBB9_5
; GCN-IR-NEXT: .LBB9_4:
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: .LBB9_5: ; %Flow3
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
; GCN-IR-NEXT: .LBB9_5: ; %udiv-end ; GCN-IR-NEXT: .LBB9_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, v0
; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9
; GCN-IR-NEXT: s_mul_i32 s0, s6, s11 ; GCN-IR-NEXT: s_mul_i32 s0, s6, s11
; GCN-IR-NEXT: v_mov_b32_e32 v2, s5 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s5
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GCN-IR-NEXT: s_mul_i32 s0, s7, s10 ; GCN-IR-NEXT: s_mul_i32 s0, s7, s10
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_srem_k_num_i64: ; GCN-IR-LABEL: s_test_srem_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i32 s8, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s6, s3, 31
; GCN-IR-NEXT: s_mov_b32 s9, s8 ; GCN-IR-NEXT: s_mov_b32 s7, s6
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s4, s2, s8 ; GCN-IR-NEXT: s_sub_u32 s4, s2, s6
; GCN-IR-NEXT: s_subb_u32 s5, s3, s8 ; GCN-IR-NEXT: s_subb_u32 s5, s3, s6
; GCN-IR-NEXT: s_flbit_i32_b32 s2, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s2, s4
; GCN-IR-NEXT: s_add_i32 s2, s2, 32 ; GCN-IR-NEXT: s_add_i32 s2, s2, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s3, s5
; GCN-IR-NEXT: s_min_u32 s8, s2, s3 ; GCN-IR-NEXT: s_min_u32 s8, s2, s3
; GCN-IR-NEXT: s_add_u32 s2, s8, 0xffffffc5 ; GCN-IR-NEXT: s_add_u32 s2, s8, 0xffffffc5
; GCN-IR-NEXT: s_addc_u32 s3, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s3, 0, -1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[4:5], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[4:5], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[2:3], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[2:3], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[2:3], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[2:3], 63
; GCN-IR-NEXT: s_or_b64 s[12:13], s[10:11], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[12:13], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[10:11], exec
; GCN-IR-NEXT: s_cselect_b32 s10, 0, 24 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s10, s2, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
; GCN-IR-NEXT: s_addc_u32 s11, s3, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s2, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s2, 63, s2 ; GCN-IR-NEXT: s_sub_i32 s2, 63, s2
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: v_readfirstlane_b32 s6, v1
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[2:3], 24, s2 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], 24, s2
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s10 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s6
; GCN-IR-NEXT: s_add_u32 s14, s4, -1 ; GCN-IR-NEXT: s_add_u32 s12, s4, -1
; GCN-IR-NEXT: s_addc_u32 s15, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s13, s5, -1
; GCN-IR-NEXT: s_sub_u32 s8, 58, s8 ; GCN-IR-NEXT: s_sub_u32 s14, 58, s8
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s14
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s15
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s3, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s3, 31
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[2:3], s[12:13], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s6, s14, s10 ; GCN-IR-NEXT: s_sub_u32 s6, s12, s10
; GCN-IR-NEXT: s_subb_u32 s6, s15, s11 ; GCN-IR-NEXT: s_subb_u32 s6, s13, s11
; GCN-IR-NEXT: s_ashr_i32 s12, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s8, s6, 31
; GCN-IR-NEXT: s_mov_b32 s13, s12 ; GCN-IR-NEXT: s_mov_b32 s9, s8
; GCN-IR-NEXT: s_and_b32 s6, s12, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], s[4:5] ; GCN-IR-NEXT: s_and_b32 s6, s8, 1
; GCN-IR-NEXT: s_sub_u32 s10, s10, s12 ; GCN-IR-NEXT: s_and_b64 s[14:15], s[8:9], s[4:5]
; GCN-IR-NEXT: s_subb_u32 s11, s11, s13 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s14
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], s[6:7]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0 ; GCN-IR-NEXT: s_subb_u32 s11, s11, s15
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[6:7] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3
; GCN-IR-NEXT: .LBB10_4: ; %Flow5 ; GCN-IR-NEXT: s_branch .LBB10_5
; GCN-IR-NEXT: .LBB10_4:
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: .LBB10_5: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
; GCN-IR-NEXT: .LBB10_5: ; %udiv-end ; GCN-IR-NEXT: .LBB10_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0
; GCN-IR-NEXT: s_mul_i32 s6, s4, s11 ; GCN-IR-NEXT: s_mul_i32 s7, s4, s7
; GCN-IR-NEXT: s_mul_i32 s5, s5, s10 ; GCN-IR-NEXT: s_mul_i32 s5, s5, s6
; GCN-IR-NEXT: s_mul_i32 s4, s4, s10 ; GCN-IR-NEXT: s_mul_i32 s4, s4, s6
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s7, v0
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s5, v0 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s5, v0
; GCN-IR-NEXT: v_sub_i32_e64 v0, vcc, 24, s4 ; GCN-IR-NEXT: v_sub_i32_e64 v0, vcc, 24, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%result = srem i64 24, %x %result = srem i64 24, %x
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, 24, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, 24, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], s[6:7]
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v7
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 58, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 58, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v8, v10
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v9, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB11_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB11_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v6 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v6
; GCN-IR-NEXT: .LBB11_6: ; %Flow4 ; GCN-IR-NEXT: .LBB11_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2
; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v3 ; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v3
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v3 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v3
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v3 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v3
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4]
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0x8000 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0x8000
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0x8000
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[8:9], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v3
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v4, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3 ; GCN-IR-NEXT: s_xor_b64 s[10:11], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v3
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[10:11], v7
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v8, v10
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v9, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7
; GCN-IR-NEXT: v_or_b32_e32 v5, v4, v6 ; GCN-IR-NEXT: v_or_b32_e32 v5, v4, v6
; GCN-IR-NEXT: .LBB12_6: ; %Flow4 ; GCN-IR-NEXT: .LBB12_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2
; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v5 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v5
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v5
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v5
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
Show All 32 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10] ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 63, v4
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v9
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v9
; GCN-IR-NEXT: v_addc_u32_e64 v9, s[10:11], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s10, 0x7fff
; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s10, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v12, 0x8000, v12 ; GCN-IR-NEXT: v_and_b32_e32 v12, 0x8000, v12
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] ; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v10, v12
; GCN-IR-NEXT: v_subbrev_u32_e32 v11, vcc, 0, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB13_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB13_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: .LBB13_6: ; %Flow4 ; GCN-IR-NEXT: .LBB13_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[6:7], 15 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[6:7], 15
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
▲ Show 20 Lines • Show All 277 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/uaddo.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; FUNC-LABEL: {{^}}s_uaddo_i64_zext: ; FUNC-LABEL: {{^}}s_uaddo_i64_zext:
; GCN: s_add_u32 ; SI: v_add_i32_e32
; GCN: s_addc_u32 ; SI: v_addc_u32_e32
; GCN: v_cmp_lt_u64_e32 vcc
; VI: v_add_u32_e32
; VI: v_addc_u32_e32
; GFX9: v_add_co_u32_e32
; GFX9: v_addc_co_u32_e32
; GCN: v_cndmask_b32_e64
; EG: ADDC_UINT ; EG: ADDC_UINT
; EG: ADDC_UINT ; EG: ADDC_UINT
define amdgpu_kernel void @s_uaddo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b) #0 { define amdgpu_kernel void @s_uaddo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue { i64, i1 } %uadd, 0 %val = extractvalue { i64, i1 } %uadd, 0
%carry = extractvalue { i64, i1 } %uadd, 1 %carry = extractvalue { i64, i1 } %uadd, 1
%ext = zext i1 %carry to i64 %ext = zext i1 %carry to i64
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_uaddo_i32_novcc(ptr addrspace(1) %out, ptr addrspace(1) %carryout, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
%carry = extractvalue { i32, i1 } %uadd, 1 %carry = extractvalue { i32, i1 } %uadd, 1
store volatile i32 %val, ptr addrspace(1) %out, align 4 store volatile i32 %val, ptr addrspace(1) %out, align 4
call void asm sideeffect "", "~{vcc}"() #0 call void asm sideeffect "", "~{vcc}"() #0
store volatile i1 %carry, ptr addrspace(1) %carryout store volatile i1 %carry, ptr addrspace(1) %carryout
ret void ret void
} }
; FUNC-LABEL: {{^}}s_uaddo_i64: ; FUNC-LABEL: {{^}}s_uaddo_i64:
; GCN: s_add_u32 ; SI: v_add_i32_e32
; GCN: s_addc_u32 ; SI: v_addc_u32_e32
; VI: v_add_u32_e32
; VI: v_addc_u32_e32
; GFX9: v_add_co_u32_e32
; GFX9: v_addc_co_u32_e32
; GCN: v_cndmask_b32_e64
; EG: ADDC_UINT ; EG: ADDC_UINT
; EG: ADD_INT ; EG: ADD_INT
define amdgpu_kernel void @s_uaddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) #0 { define amdgpu_kernel void @s_uaddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) #0 {
%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue { i64, i1 } %uadd, 0 %val = extractvalue { i64, i1 } %uadd, 0
%carry = extractvalue { i64, i1 } %uadd, 1 %carry = extractvalue { i64, i1 } %uadd, 1
store i64 %val, ptr addrspace(1) %out, align 8 store i64 %val, ptr addrspace(1) %out, align 8
▲ Show 20 Lines • Show All 144 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/uaddsat.ll

Show First 20 Lines • Show All 579 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret <16 x i32> %result ret <16 x i32> %result
} }
define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) { define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-LABEL: v_uaddsat_i64: ; GFX6-LABEL: v_uaddsat_i64:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_uaddsat_i64: ; GFX8-LABEL: v_uaddsat_i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_uaddsat_i64: ; GFX9-LABEL: v_uaddsat_i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_uaddsat_i64: ; GFX10-LABEL: v_uaddsat_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1] ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, -1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, -1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs) %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result ret i64 %result
} }
declare i8 @llvm.uadd.sat.i8(i8, i8) #0 declare i8 @llvm.uadd.sat.i8(i8, i8) #0
declare i16 @llvm.uadd.sat.i16(i16, i16) #0 declare i16 @llvm.uadd.sat.i16(i16, i16) #0
declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>) #0 declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>) #0
Show All 11 Lines

llvm/test/CodeGen/AMDGPU/udiv64.ll

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
; GCN-IR-LABEL: s_test_udiv_i64: ; GCN-IR-LABEL: s_test_udiv_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[4:5], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[4:5], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s2
; GCN-IR-NEXT: s_min_u32 s10, s10, s11 ; GCN-IR-NEXT: s_min_u32 s6, s10, s11
; GCN-IR-NEXT: s_min_u32 s14, s6, s7 ; GCN-IR-NEXT: s_add_i32 s7, s7, 32
; GCN-IR-NEXT: s_sub_u32 s12, s10, s14 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s3
; GCN-IR-NEXT: s_min_u32 s10, s7, s10
; GCN-IR-NEXT: s_sub_u32 s12, s6, s10
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
; GCN-IR-NEXT: s_or_b64 s[16:17], s[8:9], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
; GCN-IR-NEXT: s_and_b64 s[8:9], s[16:17], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_6
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s12, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[16:17], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: v_readfirstlane_b32 s11, v1
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s16 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s11
; GCN-IR-NEXT: s_add_u32 s15, s4, -1 ; GCN-IR-NEXT: s_add_u32 s11, s4, -1
; GCN-IR-NEXT: s_addc_u32 s16, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s14, s5, -1
; GCN-IR-NEXT: s_not_b64 s[2:3], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[2:3], s[6:7]
; GCN-IR-NEXT: s_add_u32 s2, s2, s14 ; GCN-IR-NEXT: s_add_u32 s16, s2, s10
; GCN-IR-NEXT: s_addc_u32 s3, s3, 0 ; GCN-IR-NEXT: s_addc_u32 s17, s3, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s16
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b64 s[2:3], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s17
; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s6, s15, s12 ; GCN-IR-NEXT: s_sub_u32 s2, s11, s12
; GCN-IR-NEXT: s_subb_u32 s6, s16, s13 ; GCN-IR-NEXT: s_subb_u32 s2, s14, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s2, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s3, s2
; GCN-IR-NEXT: s_and_b32 s6, s10, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], s[4:5] ; GCN-IR-NEXT: s_and_b32 s6, s2, 1
; GCN-IR-NEXT: s_sub_u32 s12, s12, s10 ; GCN-IR-NEXT: s_and_b64 s[16:17], s[2:3], s[4:5]
; GCN-IR-NEXT: s_subb_u32 s13, s13, s11 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s2, s2, 1 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
; GCN-IR-NEXT: s_addc_u32 s3, s3, 0 ; GCN-IR-NEXT: s_mov_b64 s[2:3], s[6:7]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[2:3], 0 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: .LBB0_4: ; %Flow6 ; GCN-IR-NEXT: s_branch .LBB0_5
; GCN-IR-NEXT: .LBB0_4:
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: .LBB0_5: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[2:3]
; GCN-IR-NEXT: .LBB0_5: ; %udiv-end ; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%result = udiv i64 %x, %y %result = udiv i64 %x, %y
store i64 %result, ptr addrspace(1) %out store i64 %result, ptr addrspace(1) %out
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; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, s[6:7] ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, s[6:7]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[6:7] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[6:7]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 63, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
arsenmUnsubmitted
Not Done
ReplyInline Actions

This is a regression

arsenm: This is a regression
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v2
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v10 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v10
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v0, v8 ; GCN-IR-NEXT: v_not_b32_e32 v0, v8
; GCN-IR-NEXT: v_not_b32_e32 v1, 0 ; GCN-IR-NEXT: v_not_b32_e32 v1, 0
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v9 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v9
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v12, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v12, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v13, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v13, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v5, v9, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v9, v5
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8
; GCN-IR-NEXT: v_and_b32_e32 v9, v8, v3 ; GCN-IR-NEXT: v_and_b32_e32 v9, v8, v3
; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v2 ; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v2
; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v10, v8
; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v11, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v8
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v9, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v7
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
; GCN-IR-NEXT: v_or_b32_e32 v5, v6, v0 ; GCN-IR-NEXT: v_or_b32_e32 v5, v6, v0
; GCN-IR-NEXT: .LBB1_6: ; %Flow4 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v5
; GCN-IR-NEXT: v_mov_b32_e32 v1, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v4
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 %x, %y %result = udiv i64 %x, %y
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_udiv24_64(ptr addrspace(1) %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_udiv24_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
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; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
; GCN-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4 ; GCN-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv24_i48: ; GCN-IR-LABEL: s_test_udiv24_i48:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
; GCN-IR-NEXT: s_mov_b32 s11, 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_and_b32 s3, s5, 0xffff ; GCN-IR-NEXT: s_and_b32 s3, s5, 0xffff
; GCN-IR-NEXT: s_and_b32 s2, s4, 0xff000000 ; GCN-IR-NEXT: s_and_b32 s2, s4, 0xff000000
; GCN-IR-NEXT: s_and_b32 s5, s7, 0xffff ; GCN-IR-NEXT: s_and_b32 s5, s7, 0xffff
; GCN-IR-NEXT: s_and_b32 s4, s6, 0xff000000 ; GCN-IR-NEXT: s_and_b32 s4, s6, 0xff000000
; GCN-IR-NEXT: s_lshr_b64 s[8:9], s[2:3], 24 ; GCN-IR-NEXT: s_lshr_b64 s[6:7], s[2:3], 24
; GCN-IR-NEXT: s_lshr_b64 s[2:3], s[4:5], 24 ; GCN-IR-NEXT: s_lshr_b64 s[2:3], s[4:5], 24
; GCN-IR-NEXT: s_and_b32 s9, s9, 0xffff ; GCN-IR-NEXT: s_and_b32 s7, s7, 0xffff
; GCN-IR-NEXT: s_and_b32 s3, s3, 0xffff ; GCN-IR-NEXT: s_and_b32 s3, s3, 0xffff
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7] ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s7
; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
; GCN-IR-NEXT: s_add_i32 s4, s4, 32 ; GCN-IR-NEXT: s_add_i32 s4, s4, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
; GCN-IR-NEXT: s_min_u32 s10, s4, s5 ; GCN-IR-NEXT: s_min_u32 s4, s4, s5
; GCN-IR-NEXT: s_flbit_i32_b32 s4, s8 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s6
; GCN-IR-NEXT: s_add_i32 s4, s4, 32 ; GCN-IR-NEXT: s_add_i32 s5, s5, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s9 ; GCN-IR-NEXT: s_min_u32 s10, s5, s10
; GCN-IR-NEXT: s_min_u32 s14, s4, s5 ; GCN-IR-NEXT: s_sub_u32 s12, s4, s10
; GCN-IR-NEXT: s_sub_u32 s12, s10, s14
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
; GCN-IR-NEXT: s_or_b64 s[16:17], s[6:7], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[16:17], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
; GCN-IR-NEXT: s_cselect_b32 s7, 0, s9 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s7
; GCN-IR-NEXT: s_cselect_b32 s6, 0, s8 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s6
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s12, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[16:17], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: v_readfirstlane_b32 s11, v1
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], s12 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[8:9], s16 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[6:7], s11
; GCN-IR-NEXT: s_add_u32 s15, s2, -1 ; GCN-IR-NEXT: s_add_u32 s11, s2, -1
; GCN-IR-NEXT: s_addc_u32 s16, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s14, s3, -1
; GCN-IR-NEXT: s_not_b64 s[4:5], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_add_u32 s8, s4, s14 ; GCN-IR-NEXT: s_add_u32 s16, s6, s10
; GCN-IR-NEXT: s_addc_u32 s9, s5, 0 ; GCN-IR-NEXT: s_addc_u32 s17, s7, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s16
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s17
; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s4, s15, s12 ; GCN-IR-NEXT: s_sub_u32 s4, s11, s12
; GCN-IR-NEXT: s_subb_u32 s4, s16, s13 ; GCN-IR-NEXT: s_subb_u32 s4, s14, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s6, s4, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s7, s6
; GCN-IR-NEXT: s_and_b32 s4, s10, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], s[2:3] ; GCN-IR-NEXT: s_and_b32 s4, s6, 1
; GCN-IR-NEXT: s_sub_u32 s12, s12, s10 ; GCN-IR-NEXT: s_and_b64 s[16:17], s[6:7], s[2:3]
; GCN-IR-NEXT: s_subb_u32 s13, s13, s11 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[8:9], 0 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
; GCN-IR-NEXT: .LBB7_4: ; %Flow3 ; GCN-IR-NEXT: s_branch .LBB7_5
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1 ; GCN-IR-NEXT: .LBB7_4:
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3] ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: .LBB7_5: ; %udiv-end ; GCN-IR-NEXT: .LBB7_5: ; %Flow3
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[2:3]
; GCN-IR-NEXT: .LBB7_6: ; %udiv-end
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: v_mov_b32_e32 v1, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4 ; GCN-IR-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
; GCN-IR-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dword v1, off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%1 = lshr i48 %x, 24 %1 = lshr i48 %x, 24
%2 = lshr i48 %y, 24 %2 = lshr i48 %y, 24
%result = udiv i48 %1, %2 %result = udiv i48 %1, %2
store i48 %result, ptr addrspace(1) %out store i48 %result, ptr addrspace(1) %out
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv_k_num_i64: ; GCN-IR-LABEL: s_test_udiv_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_min_u32 s8, s8, s9 ; GCN-IR-NEXT: s_min_u32 s8, s6, s7
; GCN-IR-NEXT: s_add_u32 s10, s8, 0xffffffc5 ; GCN-IR-NEXT: s_add_u32 s6, s8, 0xffffffc5
; GCN-IR-NEXT: s_addc_u32 s11, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s7, 0, -1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[6:7], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[6:7], 63
; GCN-IR-NEXT: s_or_b64 s[12:13], s[6:7], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[12:13], exec ; GCN-IR-NEXT: s_and_b64 s[4:5], s[10:11], exec
; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24 ; GCN-IR-NEXT: s_cselect_b32 s4, 0, 24
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s10, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: s_addc_u32 s13, s11, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s6, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[12:13], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s9, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s6, 63, s6
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: v_readfirstlane_b32 s4, v1
; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s9 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s6
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s12 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s4
; GCN-IR-NEXT: s_add_u32 s14, s2, -1 ; GCN-IR-NEXT: s_add_u32 s12, s2, -1
; GCN-IR-NEXT: s_addc_u32 s15, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s13, s3, -1
; GCN-IR-NEXT: s_sub_u32 s8, 58, s8 ; GCN-IR-NEXT: s_sub_u32 s14, 58, s8
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s14
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s15
; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s4, s14, s10 ; GCN-IR-NEXT: s_sub_u32 s4, s12, s10
; GCN-IR-NEXT: s_subb_u32 s4, s15, s11 ; GCN-IR-NEXT: s_subb_u32 s4, s13, s11
; GCN-IR-NEXT: s_ashr_i32 s12, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s8, s4, 31
; GCN-IR-NEXT: s_mov_b32 s13, s12 ; GCN-IR-NEXT: s_mov_b32 s9, s8
; GCN-IR-NEXT: s_and_b32 s4, s12, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], s[2:3] ; GCN-IR-NEXT: s_and_b32 s4, s8, 1
; GCN-IR-NEXT: s_sub_u32 s10, s10, s12 ; GCN-IR-NEXT: s_and_b64 s[14:15], s[8:9], s[2:3]
; GCN-IR-NEXT: s_subb_u32 s11, s11, s13 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s14
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0 ; GCN-IR-NEXT: s_subb_u32 s11, s11, s15
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[4:5] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_3
; GCN-IR-NEXT: .LBB8_4: ; %Flow5 ; GCN-IR-NEXT: s_branch .LBB8_5
; GCN-IR-NEXT: .LBB8_4:
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: .LBB8_5: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[2:3]
; GCN-IR-NEXT: .LBB8_5: ; %udiv-end ; GCN-IR-NEXT: .LBB8_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%result = udiv i64 24, %x %result = udiv i64 24, %x
store i64 %result, ptr addrspace(1) %out store i64 %result, ptr addrspace(1) %out
ret void ret void
} }
; define i64 @v_test_udiv_k_num_i64(i64 %x) { ; define i64 @v_test_udiv_k_num_i64(i64 %x) {
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0x8000 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0x8000
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0x8000
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[8:9], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB9_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: s_xor_b64 s[10:11], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB9_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[10:11], v7
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v8, v10
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v9, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB9_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB9_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
; GCN-IR-NEXT: .LBB9_6: ; %Flow4 ; GCN-IR-NEXT: .LBB9_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 32768, %x %result = udiv i64 32768, %x
ret i64 %result ret i64 %result
} }
define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) { define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
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; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB10_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB10_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB10_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB10_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[10:11], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s10, 0x7fff
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s10, v6
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7
; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7 ; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v6, v7
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB10_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB10_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB10_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB10_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
; GCN-IR-NEXT: .LBB10_6: ; %Flow4 ; GCN-IR-NEXT: .LBB10_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 %x, 32768 %result = udiv i64 %x, 32768
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_udiv_k_den_i64(ptr addrspace(1) %out, i64 %x) { define amdgpu_kernel void @s_test_udiv_k_den_i64(ptr addrspace(1) %out, i64 %x) {
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv_k_den_i64: ; GCN-IR-LABEL: s_test_udiv_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s4, s4, 32
; GCN-IR-NEXT: s_min_u32 s10, s6, s7 ; GCN-IR-NEXT: s_min_u32 s4, s4, s5
; GCN-IR-NEXT: s_sub_u32 s8, 59, s10 ; GCN-IR-NEXT: s_sub_u32 s8, 59, s4
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[6:7], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[8:9], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[10:11], exec
; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB11_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s8, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s8, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[12:13], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8 ; GCN-IR-NEXT: s_sub_i32 s6, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: v_readfirstlane_b32 s9, v1
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s8 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s6
; GCN-IR-NEXT: s_cbranch_vccz .LBB11_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[8:9], s[2:3], s12 ; GCN-IR-NEXT: s_lshr_b64 s[8:9], s[2:3], s9
; GCN-IR-NEXT: s_add_u32 s2, s10, 0xffffffc4 ; GCN-IR-NEXT: s_add_u32 s10, s4, 0xffffffc4
; GCN-IR-NEXT: s_addc_u32 s3, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s11, 0, -1
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b64 s[2:3], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s11
; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[2:3], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s4, 23, s8 ; GCN-IR-NEXT: s_sub_u32 s2, 23, s8
; GCN-IR-NEXT: s_subb_u32 s4, 0, s9 ; GCN-IR-NEXT: s_subb_u32 s2, 0, s9
; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s2, 31
; GCN-IR-NEXT: s_and_b32 s4, s10, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b32 s10, s10, 24 ; GCN-IR-NEXT: s_and_b32 s4, s2, 1
; GCN-IR-NEXT: s_sub_u32 s8, s8, s10 ; GCN-IR-NEXT: s_and_b32 s2, s2, 24
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_sub_u32 s8, s8, s2
; GCN-IR-NEXT: s_mov_b64 s[2:3], s[4:5]
; GCN-IR-NEXT: s_subb_u32 s9, s9, 0 ; GCN-IR-NEXT: s_subb_u32 s9, s9, 0
; GCN-IR-NEXT: s_add_u32 s2, s2, 1 ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_cbranch_vccz .LBB11_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_3
; GCN-IR-NEXT: .LBB11_4: ; %Flow5 ; GCN-IR-NEXT: s_branch .LBB11_5
; GCN-IR-NEXT: .LBB11_4:
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: .LBB11_5: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3]
; GCN-IR-NEXT: .LBB11_5: ; %udiv-end ; GCN-IR-NEXT: .LBB11_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%result = udiv i64 %x, 24 %result = udiv i64 %x, 24
store i64 %result, ptr addrspace(1) %out store i64 %result, ptr addrspace(1) %out
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; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[10:11], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7
; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7 ; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v6, v7
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB12_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
; GCN-IR-NEXT: .LBB12_6: ; %Flow4 ; GCN-IR-NEXT: .LBB12_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 %x, 24 %result = udiv i64 %x, 24
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_udiv24_k_num_i64(ptr addrspace(1) %out, i64 %x) { define amdgpu_kernel void @s_test_udiv24_k_num_i64(ptr addrspace(1) %out, i64 %x) {
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llvm/test/CodeGen/AMDGPU/urem64.ll

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GCN-IR-LABEL: s_test_urem_i64: ; GCN-IR-LABEL: s_test_urem_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[4:5], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[4:5], 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s2
; GCN-IR-NEXT: s_min_u32 s10, s10, s11 ; GCN-IR-NEXT: s_min_u32 s6, s10, s11
; GCN-IR-NEXT: s_min_u32 s14, s6, s7 ; GCN-IR-NEXT: s_add_i32 s7, s7, 32
; GCN-IR-NEXT: s_sub_u32 s12, s10, s14 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s3
; GCN-IR-NEXT: s_min_u32 s10, s7, s10
; GCN-IR-NEXT: s_sub_u32 s12, s6, s10
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
; GCN-IR-NEXT: s_or_b64 s[16:17], s[8:9], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
; GCN-IR-NEXT: s_and_b64 s[8:9], s[16:17], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_6
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s13
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s12, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[16:17], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: v_readfirstlane_b32 s11, v1
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s16 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s11
; GCN-IR-NEXT: s_add_u32 s16, s4, -1 ; GCN-IR-NEXT: s_add_u32 s14, s4, -1
; GCN-IR-NEXT: s_addc_u32 s17, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s5, -1
; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[16:17], s[6:7]
; GCN-IR-NEXT: s_add_u32 s10, s6, s14 ; GCN-IR-NEXT: s_add_u32 s16, s16, s10
; GCN-IR-NEXT: s_addc_u32 s11, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s17, s17, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s16
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s17
; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s6, s16, s12 ; GCN-IR-NEXT: s_sub_u32 s6, s14, s12
; GCN-IR-NEXT: s_subb_u32 s6, s17, s13 ; GCN-IR-NEXT: s_subb_u32 s6, s15, s13
; GCN-IR-NEXT: s_ashr_i32 s14, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s6, s14, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[4:5] ; GCN-IR-NEXT: s_and_b32 s6, s10, 1
; GCN-IR-NEXT: s_sub_u32 s12, s12, s14 ; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[4:5]
; GCN-IR-NEXT: s_subb_u32 s13, s13, s15 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s10, s10, 1 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
; GCN-IR-NEXT: s_addc_u32 s11, s11, 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[10:11], 0 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: .LBB0_4: ; %Flow6 ; GCN-IR-NEXT: s_branch .LBB0_5
; GCN-IR-NEXT: .LBB0_4:
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: .LBB0_5: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: .LBB0_5: ; %udiv-end ; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0
; GCN-IR-NEXT: s_mov_b32 s12, s0 ; GCN-IR-NEXT: s_mov_b32 s12, s0
; GCN-IR-NEXT: s_mul_i32 s0, s4, s9 ; GCN-IR-NEXT: s_mul_i32 s0, s4, s9
; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GCN-IR-NEXT: s_mul_i32 s0, s5, s8 ; GCN-IR-NEXT: s_mul_i32 s0, s5, s8
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_subb_u32_e64 v6, s[6:7], 0, 0, s[6:7] ; GCN-IR-NEXT: v_subb_u32_e64 v6, s[6:7], 0, 0, s[6:7]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[5:6] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[5:6]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v5 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v5
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 63, v5
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v7, v8 ; GCN-IR-NEXT: v_not_b32_e32 v7, v8
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v10 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v10
; GCN-IR-NEXT: v_not_b32_e32 v6, 0 ; GCN-IR-NEXT: v_not_b32_e32 v6, 0
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v9 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v9
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3
; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2
; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v10, v12
; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v11, v13, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v4
; GCN-IR-NEXT: .LBB1_6: ; %Flow4 ; GCN-IR-NEXT: .LBB1_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v7 ; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v7
; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4 ; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4
; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4
; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
▲ Show 20 Lines • Show All 393 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem_k_num_i64: ; GCN-IR-LABEL: s_test_urem_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_min_u32 s8, s8, s9 ; GCN-IR-NEXT: s_min_u32 s8, s6, s7
; GCN-IR-NEXT: s_add_u32 s10, s8, 0xffffffc5 ; GCN-IR-NEXT: s_add_u32 s6, s8, 0xffffffc5
; GCN-IR-NEXT: s_addc_u32 s11, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s7, 0, -1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[6:7], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[6:7], 63
; GCN-IR-NEXT: s_or_b64 s[12:13], s[6:7], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[12:13], exec ; GCN-IR-NEXT: s_and_b64 s[4:5], s[10:11], exec
; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24 ; GCN-IR-NEXT: s_cselect_b32 s4, 0, 24
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB6_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s10, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
; GCN-IR-NEXT: s_addc_u32 s13, s11, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s6, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[12:13], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s9, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s6, 63, s6
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: v_readfirstlane_b32 s4, v1
; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s9 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s6
; GCN-IR-NEXT: s_cbranch_vccz .LBB6_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s12 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s4
; GCN-IR-NEXT: s_add_u32 s14, s2, -1 ; GCN-IR-NEXT: s_add_u32 s12, s2, -1
; GCN-IR-NEXT: s_addc_u32 s15, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s13, s3, -1
; GCN-IR-NEXT: s_sub_u32 s8, 58, s8 ; GCN-IR-NEXT: s_sub_u32 s14, 58, s8
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s14
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s15
; GCN-IR-NEXT: .LBB6_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB6_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s4, s14, s10 ; GCN-IR-NEXT: s_sub_u32 s4, s12, s10
; GCN-IR-NEXT: s_subb_u32 s4, s15, s11 ; GCN-IR-NEXT: s_subb_u32 s4, s13, s11
; GCN-IR-NEXT: s_ashr_i32 s12, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s8, s4, 31
; GCN-IR-NEXT: s_mov_b32 s13, s12 ; GCN-IR-NEXT: s_mov_b32 s9, s8
; GCN-IR-NEXT: s_and_b32 s4, s12, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], s[2:3] ; GCN-IR-NEXT: s_and_b32 s4, s8, 1
; GCN-IR-NEXT: s_sub_u32 s10, s10, s12 ; GCN-IR-NEXT: s_and_b64 s[14:15], s[8:9], s[2:3]
; GCN-IR-NEXT: s_subb_u32 s11, s11, s13 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s14
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0 ; GCN-IR-NEXT: s_subb_u32 s11, s11, s15
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[4:5] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz .LBB6_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_3
; GCN-IR-NEXT: .LBB6_4: ; %Flow5 ; GCN-IR-NEXT: s_branch .LBB6_5
; GCN-IR-NEXT: .LBB6_4:
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: .LBB6_5: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: .LBB6_5: ; %udiv-end ; GCN-IR-NEXT: .LBB6_6: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0
; GCN-IR-NEXT: s_mov_b32 s8, s0 ; GCN-IR-NEXT: s_mov_b32 s8, s0
; GCN-IR-NEXT: s_mul_i32 s0, s2, s7 ; GCN-IR-NEXT: s_mul_i32 s0, s2, s5
; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GCN-IR-NEXT: s_mul_i32 s0, s3, s6 ; GCN-IR-NEXT: s_mul_i32 s0, s3, s4
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0
; GCN-IR-NEXT: s_mul_i32 s0, s2, s6 ; GCN-IR-NEXT: s_mul_i32 s0, s2, s4
; GCN-IR-NEXT: v_sub_i32_e64 v0, vcc, 24, s0 ; GCN-IR-NEXT: v_sub_i32_e64 v0, vcc, 24, s0
; GCN-IR-NEXT: s_mov_b32 s10, -1 ; GCN-IR-NEXT: s_mov_b32 s10, -1
; GCN-IR-NEXT: s_mov_b32 s9, s1 ; GCN-IR-NEXT: s_mov_b32 s9, s1
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
%result = urem i64 24, %x %result = urem i64 24, %x
store i64 %result, ptr addrspace(1) %out store i64 %result, ptr addrspace(1) %out
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem_k_den_i64: ; GCN-IR-LABEL: s_test_urem_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s4, s4, 32
; GCN-IR-NEXT: s_min_u32 s8, s6, s7 ; GCN-IR-NEXT: s_min_u32 s4, s4, s5
; GCN-IR-NEXT: s_sub_u32 s10, 59, s8 ; GCN-IR-NEXT: s_sub_u32 s8, 59, s4
; GCN-IR-NEXT: s_subb_u32 s11, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[6:7], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[8:9], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[8:9], 63
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[10:11], exec
; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s10, 1 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9
; GCN-IR-NEXT: s_addc_u32 s13, s11, 0 ; GCN-IR-NEXT: v_add_i32_e64 v1, vcc, s8, 1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[12:13], 0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc
; GCN-IR-NEXT: s_sub_i32 s9, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s6, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: v_readfirstlane_b32 s9, v1
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s9 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s6
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s12 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s9
; GCN-IR-NEXT: s_add_u32 s8, s8, 0xffffffc4 ; GCN-IR-NEXT: s_add_u32 s12, s4, 0xffffffc4
; GCN-IR-NEXT: s_addc_u32 s9, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s13, 0, -1
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s12
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, s13
; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s4, 23, s10 ; GCN-IR-NEXT: s_sub_u32 s4, 23, s10
; GCN-IR-NEXT: s_subb_u32 s4, 0, s11 ; GCN-IR-NEXT: s_subb_u32 s4, 0, s11
; GCN-IR-NEXT: s_ashr_i32 s12, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s8, s4, 31
; GCN-IR-NEXT: s_and_b32 s4, s12, 1 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: s_and_b32 s12, s12, 24 ; GCN-IR-NEXT: s_and_b32 s4, s8, 1
; GCN-IR-NEXT: s_sub_u32 s10, s10, s12 ; GCN-IR-NEXT: s_and_b32 s8, s8, 24
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_sub_u32 s10, s10, s8
; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5]
; GCN-IR-NEXT: s_subb_u32 s11, s11, 0 ; GCN-IR-NEXT: s_subb_u32 s11, s11, 0
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[8:9], 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[4:5]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
; GCN-IR-NEXT: .LBB7_4: ; %Flow5 ; GCN-IR-NEXT: s_branch .LBB7_5
; GCN-IR-NEXT: .LBB7_4:
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: .LBB7_5: ; %Flow5
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7]
; GCN-IR-NEXT: .LBB7_5: ; %udiv-end ; GCN-IR-NEXT: .LBB7_6: ; %udiv-end
; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, 24 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, 24
; GCN-IR-NEXT: s_mov_b32 s8, s0 ; GCN-IR-NEXT: s_mov_b32 s8, s0
; GCN-IR-NEXT: s_mul_i32 s0, s7, 24 ; GCN-IR-NEXT: s_mul_i32 s0, s7, 24
; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0
; GCN-IR-NEXT: s_mul_i32 s0, s6, 24 ; GCN-IR-NEXT: s_mul_i32 s0, s6, 24
; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
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; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4]
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0x8000 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0x8000
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0x8000
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[8:9], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[8:9]
; GCN-IR-NEXT: s_cbranch_execz .LBB8_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v3
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v4, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3 ; GCN-IR-NEXT: s_xor_b64 s[10:11], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v3
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB8_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[10:11], v7
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[10:11], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v8, v10
; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v9, v11, vcc
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB8_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB8_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB8_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB8_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7
; GCN-IR-NEXT: v_or_b32_e32 v5, v4, v6 ; GCN-IR-NEXT: v_or_b32_e32 v5, v4, v6
; GCN-IR-NEXT: .LBB8_6: ; %Flow4 ; GCN-IR-NEXT: .LBB8_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2
; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v5 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v5
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v5
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v5
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
Show All 21 Lines
; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
; GCN-IR-NEXT: s_cbranch_execz .LBB9_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: s_xor_b64 s[6:7], vcc, -1
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execz .LBB9_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7
; GCN-IR-NEXT: v_addc_u32_e64 v7, s[10:11], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s10, 0x7fff
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s10, v8
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v10, 0x8000, v10 ; GCN-IR-NEXT: v_and_b32_e32 v10, 0x8000, v10
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v8, v10
; GCN-IR-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB9_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: .LBB9_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
; GCN-IR-NEXT: .LBB9_6: ; %Flow4 ; GCN-IR-NEXT: .LBB9_6: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 15 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 15
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 %x, 32768 %result = urem i64 %x, 32768
ret i64 %result ret i64 %result
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/usubo.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,SICIVI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,SICIVI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,SICIVI,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,SICIVI,FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; FUNC-LABEL: {{^}}s_usubo_i64_zext: ; FUNC-LABEL: {{^}}s_usubo_i64_zext:
; GCN: s_sub_u32 ; SI: v_sub_i32_e32
; GCN: s_subb_u32 ; SI: v_subb_u32_e32
; GCN: v_cmp_gt_u64_e32 vcc
; VI: v_sub_u32_e32
; VI: v_subb_u32_e32
; GFX9: v_sub_co_u32_e32
; GFX9: v_subb_co_u32_e32
; GCN: v_cndmask_b32_e64
; EG: SUBB_UINT ; EG: SUBB_UINT
; EG: ADDC_UINT ; EG: ADDC_UINT
define amdgpu_kernel void @s_usubo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b) #0 { define amdgpu_kernel void @s_usubo_i64_zext(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
%usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) #0 %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) #0
%val = extractvalue { i64, i1 } %usub, 0 %val = extractvalue { i64, i1 } %usub, 0
%carry = extractvalue { i64, i1 } %usub, 1 %carry = extractvalue { i64, i1 } %usub, 1
%ext = zext i1 %carry to i64 %ext = zext i1 %carry to i64
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_usubo_i32_novcc(ptr addrspace(1) %out, ptr addrspace(1) %carryout, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
%carry = extractvalue { i32, i1 } %uadd, 1 %carry = extractvalue { i32, i1 } %uadd, 1
store volatile i32 %val, ptr addrspace(1) %out, align 4 store volatile i32 %val, ptr addrspace(1) %out, align 4
call void asm sideeffect "", "~{vcc}"() #0 call void asm sideeffect "", "~{vcc}"() #0
store volatile i1 %carry, ptr addrspace(1) %carryout store volatile i1 %carry, ptr addrspace(1) %carryout
ret void ret void
} }
; FUNC-LABEL: {{^}}s_usubo_i64: ; FUNC-LABEL: {{^}}s_usubo_i64:
; GCN: s_sub_u32 ; SI: v_sub_i32_e32
; GCN: s_subb_u32 ; SI: v_subb_u32_e32
; VI: v_sub_u32_e32
; VI: v_subb_u32_e32
; GFX9: v_sub_co_u32_e32
; GFX9: v_subb_co_u32_e32
; GCN: v_cndmask_b32_e64
; EG-DAG: SUBB_UINT ; EG-DAG: SUBB_UINT
; EG-DAG: SUB_INT ; EG-DAG: SUB_INT
; EG-DAG: SUB_INT ; EG-DAG: SUB_INT
; EG: SUB_INT ; EG: SUB_INT
define amdgpu_kernel void @s_usubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) #0 { define amdgpu_kernel void @s_usubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, i64 %a, i64 %b) #0 {
%usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue { i64, i1 } %usub, 0 %val = extractvalue { i64, i1 } %usub, 0
Show All 27 Linesdefine amdgpu_kernel void @v_usubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %carryout, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {
%val = extractvalue { i64, i1 } %usub, 0 %val = extractvalue { i64, i1 } %usub, 0
%carry = extractvalue { i64, i1 } %usub, 1 %carry = extractvalue { i64, i1 } %usub, 1
store i64 %val, ptr addrspace(1) %out, align 8 store i64 %val, ptr addrspace(1) %out, align 8
store i1 %carry, ptr addrspace(1) %carryout store i1 %carry, ptr addrspace(1) %carryout
ret void ret void
} }
; FUNC-LABEL: {{^}}v_usubo_i16: ; FUNC-LABEL: {{^}}v_usubo_i16:
; SI: v_sub_i32_e32 ; SI: v_subrev_i32_e32
; SI: v_and_b32 ; SI: v_and_b32
; SI: v_cmp_ne_u32_e32 ; SI: v_cmp_ne_u32_e32
; VI: v_sub_u16_e32 ; VI: v_sub_u16_e32
; VI: v_cmp_gt_u16_e32 ; VI: v_cmp_gt_u16_e32
; GFX9: v_sub_u16_e32 ; GFX9: v_sub_u16_e32
; GFX9: v_cmp_gt_u16_e32 ; GFX9: v_cmp_gt_u16_e32
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llvm/test/CodeGen/AMDGPU/usubsat.ll

Show First 20 Lines • Show All 675 Lines • ▼ Show 20 Lines; GFX11-NEXT: s_setpc_b64 s[30:31]
ret <16 x i32> %result ret <16 x i32> %result
} }
define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) { define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-LABEL: v_usubsat_i64: ; GFX6-LABEL: v_usubsat_i64:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
arsenmUnsubmitted
Not Done
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This is an improvement

arsenm: This is an improvement
; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_usubsat_i64: ; GFX8-LABEL: v_usubsat_i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v2 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc ; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_usubsat_i64: ; GFX9-LABEL: v_usubsat_i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v0, v2 ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10PLUS-LABEL: v_usubsat_i64: ; GFX10PLUS-LABEL: v_usubsat_i64:
; GFX10PLUS: ; %bb.0: ; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10PLUS-NEXT: v_sub_co_u32 v2, vcc_lo, v0, v2 ; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2
; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo ; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
; GFX10PLUS-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[0:1] ; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo ; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs) %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result ret i64 %result
} }
declare i8 @llvm.usub.sat.i8(i8, i8) #0 declare i8 @llvm.usub.sat.i8(i8, i8) #0
declare i16 @llvm.usub.sat.i16(i16, i16) #0 declare i16 @llvm.usub.sat.i16(i16, i16) #0
declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) #0 declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) #0
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