[AMDGPU][SDAG] attempt to custom legalize uaddo/usubo for long operands

[vikramRH]

Summary

The goal here was to eliminate the redundant compare instruction generated in addition to add/sub2. Tries to address the issue discussed here, https://github.com/RadeonOpenCompute/ROCm/issues/477

Im having to modify the instruction selection for uniform addcarry/subcarry node when one of the carry users have already been selected to VALU to avoid suboptimal pattern. I have some concerns here and would like to know if it could be done in a better way.

[arsenm]

Are there any new tests that demonstrate what you are trying to do?

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

893–894

Spaces after // and capitalize

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

5436

I don't see the point of this, you're just doing what the default legalization should do in 1 step instead of 2

llvm/test/CodeGen/AMDGPU/carryout-selection.ll

197

In a precommit can you convert this to generated checks? It's hard to see what's going on here

llvm/test/CodeGen/AMDGPU/udiv64.ll

352–354

This is a regression

llvm/test/CodeGen/AMDGPU/usubsat.ll

684–687

This is an improvement

[alex-t]

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

899

if (!RC) is "true" which means getOperandRegClass has returned NULL we've got to evaluate the second part of the condition and will call the SIRegisterInfo::isSGPRClass with nullptr? Shouldn't there be OR instead?

[alex-t]

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

906

What if N is not divergent but has just one user selected to VALU and has yet 10 SALU users? Would this still be optimal?

945

Does this really belong to this change?