[M68k][Disassembler] Use custom decoder for 32-bit immediates

[myhsu]

Summary

32-bit immediates require special cares because they go across the normal word (16 bits) boundaries.

This patch also fixes some incorrect disassembler test cases.

[barannikov88]

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

100

(nitpick) It would be more reliable to specify template argument (static_cast becomes unnecessary).

llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

24

[myhsu]

Addressed feedbacks

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

 }
 
 static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn,
                                             uint64_t Address,
                                             const void *Decoder) {
   llvm_unreachable("unimplemented");
 }
 
+static DecodeStatus DecodeImm32(MCInst &Inst, uint64_t Imm, uint64_t Address,
+                                const void *Decoder) {
+  Inst.addOperand(MCOperand::createImm(M68k::swapWord<uint32_t>(Imm)));
+  return DecodeStatus::Success;
+}
+
 #include "M68kGenDisassemblerTable.inc"
 
 /// A disassembler class for M68k.
 struct M68kDisassembler : public MCDisassembler {
   M68kDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
       : MCDisassembler(STI, Ctx) {}
   virtual ~M68kDisassembler() {}
 

llvm/lib/Target/M68k/M68kInstrFormats.td

let EA = (descend /*MODE*/0b111,
                     // the dag assigned to EA only has two arguments. Such
                     // that it's easier for MOV instructions to reverse
                     // on its destination part.
                     /*REGISTER*/(descend 0b00, size_w_l));
 
   // Absolute address
   let Supplement = !if(size_w_l,
     // abs.L
-    (operand "$"#opnd_name, 32, (encoder "encodeRelocImm<32>")),
+    (operand "$"#opnd_name, 32, (encoder "encodeRelocImm<32>"),
+                                (decoder "DecodeImm32")),
     // abs.W
     (operand "$"#opnd_name, 16, (encoder "encodeRelocImm<16>"))
   );
 }
 
 class MxEncAddrMode_o<string reg_opnd> : MxEncMemOp {
   let EA = (descend /*MODE*/0b011,
                     /*REGISTER*/(operand "$"#reg_opnd, 3));

llvm/lib/Target/M68k/MCTargetDesc/M68kBaseInfo.h

 
 #ifndef LLVM_LIB_TARGET_M68K_MCTARGETDESC_M68KBASEINFO_H
 #define LLVM_LIB_TARGET_M68K_MCTARGETDESC_M68KBASEINFO_H
 
 #include "M68kMCTargetDesc.h"
 
 #include "llvm/MC/MCExpr.h"
 #include "llvm/Support/DataTypes.h"
+#include "llvm/Support/Endian.h"
 #include "llvm/Support/ErrorHandling.h"
 
 #define GET_INSTRINFO_MI_OPS_INFO
 #define GET_INSTRINFO_OPERAND_TYPES_ENUM
 #define GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
 #include "M68kGenInstrInfo.inc"
 
 namespace llvm {

 enum { MemDisp = 0, MemBase = 1, MemIndex = 2, MemOuter = 3 };
 
 /// Enums for pc-relative memory operand decoding. Supports these forms:
 /// (d,PC)
 /// (d,PC,Xn)
 /// ([bd,PC],Xn,od)
 /// ([bd,PC,Xn],od)
 enum { PCRelDisp = 0, PCRelIndex = 1, PCRelOuter = 2 };
+
+// On a LE host:
+// MSB                   LSB    MSB                   LSB
+// | 0x12 0x34 | 0xAB 0xCD | -> | 0xAB 0xCD | 0x12 0x34 |
+// (On a BE host nothing changes)
+template <typename value_t> value_t swapWord(value_t Val) {
+  const unsigned NumWords = sizeof(Val) / 2;
+  if (NumWords <= 1)
+    return Val;
+  Val = support::endian::byte_swap(Val, support::big);
+  value_t NewVal = 0;
+  for (unsigned i = 0U; i != NumWords; ++i) {
+    uint16_t Part = (Val >> (i * 16)) & 0xFFFF;
+    Part = support::endian::byte_swap(Part, support::big);
+    NewVal |= (Part << (i * 16));
+  }
+  return NewVal;
+}
 } // namespace M68k
 
 namespace M68kBeads {
 enum {
   Ctrl = 0x0,
   Bits1 = 0x1,
   Bits2 = 0x2,
   Bits3 = 0x3,

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

template <unsigned Size> struct select_uint_t {
   using type = typename std::conditional<
       Size == 8, uint8_t,
       typename std::conditional<
           Size == 16, uint16_t,
           typename std::conditional<Size == 32, uint32_t,
                                     uint64_t>::type>::type>::type;
 };
 
-// On a LE host:
-// MSB                   LSB    MSB                   LSB
-// | 0x12 0x34 | 0xAB 0xCD | -> | 0xAB 0xCD | 0x12 0x34 |
-// (On a BE host nothing changes)
-template <typename value_t> static value_t swapWord(value_t Val) {
-  const unsigned NumWords = sizeof(Val) / 2;
-  if (NumWords <= 1)
-    return Val;
-  Val = support::endian::byte_swap(Val, support::big);
-  value_t NewVal = 0;
-  for (unsigned i = 0U; i != NumWords; ++i) {
-    uint16_t Part = (Val >> (i * 16)) & 0xFFFF;
-    Part = support::endian::byte_swap(Part, support::big);
-    NewVal |= (Part << (i * 16));
-  }
-  return NewVal;
-}
-
 // Figure out which byte we're at in big endian mode.
 template <unsigned Size> static unsigned getBytePosition(unsigned BitPos) {
   if (Size % 16) {
     return static_cast<unsigned>(BitPos / 8 + ((BitPos & 0b1111) < 8 ? 1 : -1));
   } else {
     assert(!(BitPos & 0b1111) && "Not aligned to word boundary?");
     return BitPos / 8;
   }

 template <unsigned Size>
 void M68kMCCodeEmitter::encodeRelocImm(const MCInst &MI, unsigned OpIdx,
                                        unsigned InsertPos, APInt &Value,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
   using value_t = typename select_uint_t<Size>::type;
   const MCOperand &MCO = MI.getOperand(OpIdx);
   if (MCO.isImm()) {
-    Value |= swapWord<value_t>(static_cast<value_t>(MCO.getImm()));
+    Value |= M68k::swapWord<value_t>(static_cast<value_t>(MCO.getImm()));
   } else if (MCO.isExpr()) {
     const MCExpr *Expr = MCO.getExpr();
 
     // Absolute address
     int64_t Addr;
     if (Expr->evaluateAsAbsolute(Addr)) {
-      Value |= swapWord<value_t>(static_cast<value_t>(Addr));
+      Value |= M68k::swapWord<value_t>(static_cast<value_t>(Addr));
       return;
     }
 
     // Relocatable address
     unsigned InsertByte = getBytePosition<Size>(InsertPos);
     Fixups.push_back(MCFixup::create(InsertByte, Expr,
                                      getFixupForSize(Size, /*IsPCRel=*/false),
                                      MI.getLoc()));
   }
 }
 
 template <unsigned Size>
 void M68kMCCodeEmitter::encodePCRelImm(const MCInst &MI, unsigned OpIdx,
                                        unsigned InsertPos, APInt &Value,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
   const MCOperand &MCO = MI.getOperand(OpIdx);
   if (MCO.isImm()) {
     using value_t = typename select_uint_t<Size>::type;
-    Value |= swapWord<value_t>(static_cast<value_t>(MCO.getImm()));
+    Value |= M68k::swapWord<value_t>(static_cast<value_t>(MCO.getImm()));
   } else if (MCO.isExpr()) {
     const MCExpr *Expr = MCO.getExpr();
     unsigned InsertByte = getBytePosition<Size>(InsertPos);
 
     // Special handlings for sizes smaller than a word.
     if (Size < 16) {
       int LabelOffset = 0;
       if (InsertPos < 16)

llvm/test/MC/Disassembler/M68k/arithmetic.txt

 0xdb 0xfa 0x15 0x19
 
 # CHECK: adda.l %a5, %a4
 0xd9 0xcd
 
 # CHECK: add.l    (4660,%sp), %d5
 0xda 0xaf 0x12 0x34
 
-# CHECK: cmpi.w  #769, $3012022
+# CHECK: cmpi.w  #769, $20220301
 0x0c 0x79 0x03 0x01 0x20 0x22 0x03 0x01
 
 # CHECK: cmpi.w  #5416, %d7
 0x0c 0x47 0x15 0x28
 
 # CHECK: cmp.w   (69,%a2,%a1), %d3
 0xb6 0x72 0x98 0x45
 
 # CHECK: cmpi.l  #50402614, (51,%a5,%d7)
 0x0c 0xb5 0x03 0x01 0x15 0x36 0x78 0x33
 
 # CHECK: cmpi.l  #50403411, $1
 0x0c 0xb9 0x03 0x01 0x18 0x53 0x00 0x01 0x00 0x00
 
-# CHECK: cmpi.b  #64, $15400301
+# CHECK: cmpi.b  #64, $3011540
 0x0c 0x39 0x00 0x40 0x03 0x01 0x15 0x40
 
 # CHECK: cmp.b   %d5, %d7
 0xbe 0x05
 
 # CHECK: cmp.w %d1, %d0
 0xb0 0x41
 

llvm/test/MC/Disassembler/M68k/data.txt

 
 # CHECK: move.l (32,%a0,%d1), %sp
 0x2e 0x70 0x18 0x20
 
 # CHECK: move.l (64,%sp,%a0), %d0
 0x20 0x37 0x88 0x40
 
 # CHECK: move.l $f0000000, %a5
-0x2a 0x79 0x00 0x00 0xf0 0x00
+0x2a 0x79 0xf0 0x00 0x00 0x00
 
-# CHECK: move.l $1, %d0
+# CHECK: move.l $10000, %d0
 0x20 0x39 0x00 0x01 0x00 0x00
 
 # CHECK: move.l (32768,%pc), %a2
 0x24 0x7a 0x80 0x00
 
 # CHECK: move.l (16384,%pc), %d1
 0x22 0x3a 0x40 0x00