[WebAssembly] Add passes for GEP lowering

[samparker]

Summary

At optimization level -O2 and above, add SeparateConstOffsetFromGEP, EarlyCSE, InstCombine and LICM to the addIRPasses phase.

These passes will also enable D139415.

[sbc100]

llvm/test/CodeGen/WebAssembly/fpclamptosat.ll

157

What happened here?

[samparker]

llvm/test/CodeGen/WebAssembly/fpclamptosat.ll

157

Yeah... I need to look at these clamping files. I'm assuming CSE is responsible, but the reasons for the changes are non-obvious to me.

[samparker]

llvm/test/CodeGen/WebAssembly/fpclamptosat.ll

157

Looks like DAGCombiner is now failing to produce fp_to_uint_sat, I will investigate more tomorrow.

[samparker]

Hopefully the FP clamping and min/max idiom misses have now been fixed in D142093, D142481, D142535, D143106 and D143256.

With my local benchmark suite, using wasi-sdk and running on node, this patch affects slightly less than half of the benchmarks and gives a geomean improvement of ~5%.

[tlively]

Impressive performance wins! How is code size affected?

[samparker]

How is code size affected?

Using wasi-sdk-19, the total code size of my suite is 7985 KB. With this patch it's reduced slightly to 7982 KB.

[dschuff]

Do those figures include using wasm-opt after linking?

[samparker]

Do those figures include using wasm-opt after linking?

I don't know... I just use wasi-sdk and I assumed it just uses clang, llvm and lld.

Though, after reporting the (small) code size changes, the reported performance numbers (large) didn't make sense. I'm still investigating what's going on.

[tlively]

The clang driver will automatically call wasm-opt if it finds it in your PATH, so it's worth checking whether wasm-opt is being run or not.

[junparser]

llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

464

have you ever test with createSeparateConstOffsetFromGEPPass(true)

[samparker]

Sorry for the delay in replying.

I found it impossible to reproduce my previously quoted numbers. I'm juggling an evolving benchmark suite, while modifying wasi-sdk and NodeJS, so I'm guessing I got something out-of-sync!

Below are my revised numbers, with the varying configuration options for completeness. I'm running on an Ampere Altra, with a modified version of NodeJS which uses trap handlers for OOB checks (the patch is currently in review for V8), and I'm only using the TurboFan compiler to reduce noise. wasm-opt is not on my PATH. The main takeaways are:

• LICM is no longer included.
• Running InstCombine increases code size a little, but I haven't included any of the patches to mitigate the known problems with running it late.
• Lowering GEPs, in SeparateConstOffsetFromGEP, increases code size and execution time.
• OptimizeGEPs still gives a useful improvement in size and execution time.

Pass Config	Total code size (KB)	Speedup (%)
vanilla wasi-sdk-16	7809.192	-
SeparateConstOffsetFromGEP(false), EarlyCSE	7805.771	0.1
SeparateConstOffsetFromGEP(false), EarlyCSE, InstCombine	7810.446	0.1
SeparateConstOffsetFromGEP(true), EarlyCSE	7819.303	-0.22
SeparateConstOffsetFromGEP(true), EarlyCSE, InstCombine	7819.988	-0.24
SeparateConstOffsetFromGEP(false), EarlyCSE, OptimizeGEPs	7798.139	1.78
SeparateConstOffsetFromGEP(false), EarlyCSE, OptimizeGEPs, InstCombine	7802.854	1.7

llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

void WebAssemblyPassConfig::addIRPasses() {
   // transformation algorithms with Emscripten SjLj, so we run
   // LowerEmscriptenEHSjLj pass also when Wasm SjLj is enabled.
   if (WasmEnableEmEH || WasmEnableEmSjLj || WasmEnableSjLj)
     addPass(createWebAssemblyLowerEmscriptenEHSjLj());
 
   // Expand indirectbr instructions to switches.
   addPass(createIndirectBrExpandPass());
 
+  if (getOptLevel() >= CodeGenOpt::Default) {
+    addPass(createSeparateConstOffsetFromGEPPass());
+    addPass(createEarlyCSEPass());
+    addPass(createLICMPass());
+  }
+
   TargetPassConfig::addIRPasses();
 }
 
 void WebAssemblyPassConfig::addISelPrepare() {
   // Lower atomics and TLS if necessary
   addPass(new CoalesceFeaturesAndStripAtomics(&getWebAssemblyTargetMachine()));
 
   // This is a no-op if atomics are not used in the module

llvm/test/CodeGen/WebAssembly/address-offsets.ll

 ; TODO: load_test1 - load_test8 are disabled because folding GA+reg is disabled
 ; (there are cases where the value in the reg can be negative).
 ; Likewise for stores.
 
 define i32 @load_test1(i32 %n) {
 ; CHECK-LABEL: load_test1:
 ; CHECK:         .functype load_test1 (i32) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    global.get $push2=, g@GOT
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $0, $pop0
-; CHECK-NEXT:    global.get $push2=, g@GOT
-; CHECK-NEXT:    i32.add $push3=, $pop1, $pop2
-; CHECK-NEXT:    i32.const $push4=, 40
-; CHECK-NEXT:    i32.add $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.load $push6=, 0($pop5)
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i32.add $push3=, $pop2, $pop1
+; CHECK-NEXT:    i32.load $push4=, 40($pop3)
+; CHECK-NEXT:    return $pop4
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds [0 x i32], ptr @g, i32 0, i32 %add
   %t = load i32, ptr %arrayidx, align 4
   ret i32 %t
 }
 
 define i32 @load_test2(i32 %n) {
 ; CHECK-LABEL: load_test2:
 ; CHECK:         .functype load_test2 (i32) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    global.get $push2=, g@GOT
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $0, $pop0
-; CHECK-NEXT:    global.get $push2=, g@GOT
-; CHECK-NEXT:    i32.add $push3=, $pop1, $pop2
-; CHECK-NEXT:    i32.const $push4=, 40
-; CHECK-NEXT:    i32.add $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.load $push6=, 0($pop5)
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i32.add $push3=, $pop2, $pop1
+; CHECK-NEXT:    i32.load $push4=, 40($pop3)
+; CHECK-NEXT:    return $pop4
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds [0 x i32], ptr @g, i32 0, i32 %add
   %t = load i32, ptr %arrayidx, align 4
   ret i32 %t
 }
 
 define i32 @load_test3(i32 %n) {
 ; CHECK-LABEL: load_test3:
; CHECK-NEXT:    return $pop6
   %t = load i32, ptr %add.ptr, align 4
   ret i32 %t
 }
 
 define i32 @load_test6(i32 %n) {
 ; CHECK-LABEL: load_test6:
 ; CHECK:         .functype load_test6 (i32) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    global.get $push2=, g@GOT
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $0, $pop0
-; CHECK-NEXT:    global.get $push2=, g@GOT
-; CHECK-NEXT:    i32.add $push3=, $pop1, $pop2
-; CHECK-NEXT:    i32.const $push4=, 40
-; CHECK-NEXT:    i32.add $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.load $push6=, 0($pop5)
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i32.add $push3=, $pop2, $pop1
+; CHECK-NEXT:    i32.load $push4=, 40($pop3)
+; CHECK-NEXT:    return $pop4
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds [0 x i32], ptr @g, i32 0, i32 %add
   %t = load i32, ptr %add.ptr, align 4
   ret i32 %t
 }
 
 define i32 @load_test7(i32 %n) {
 ; CHECK-LABEL: load_test7:
; CHECK-NEXT:    return $pop4
   %t = load i32, ptr %add.ptr1, align 4
   ret i32 %t
 }
 
 define i32 @load_test8(i32 %n) {
 ; CHECK-LABEL: load_test8:
 ; CHECK:         .functype load_test8 (i32) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    global.get $push2=, g@GOT
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $0, $pop0
-; CHECK-NEXT:    global.get $push2=, g@GOT
-; CHECK-NEXT:    i32.add $push3=, $pop1, $pop2
-; CHECK-NEXT:    i32.const $push4=, 40
-; CHECK-NEXT:    i32.add $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.load $push6=, 0($pop5)
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i32.add $push3=, $pop2, $pop1
+; CHECK-NEXT:    i32.load $push4=, 40($pop3)
+; CHECK-NEXT:    return $pop4
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds [0 x i32], ptr @g, i32 0, i32 %add
   %t = load i32, ptr %add.ptr, align 4
   ret i32 %t
 }
 
 define i32 @load_test9() {
 ; CHECK-LABEL: load_test9:

 }
 
 define i32 @load_test12(ptr %p, i32 %n) {
 ; CHECK-LABEL: load_test12:
 ; CHECK:         .functype load_test12 (i32, i32) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $1, $pop0
-; CHECK-NEXT:    i32.add $push2=, $pop1, $0
-; CHECK-NEXT:    i32.const $push3=, 40
-; CHECK-NEXT:    i32.add $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.load $push5=, 0($pop4)
-; CHECK-NEXT:    return $pop5
+; CHECK-NEXT:    i32.add $push2=, $0, $pop1
+; CHECK-NEXT:    i32.load $push3=, 40($pop2)
+; CHECK-NEXT:    return $pop3
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds i32, ptr %p, i32 %add
   %t = load i32, ptr %arrayidx, align 4
   ret i32 %t
 }
 
 define i32 @load_test13(ptr %p, i32 %n) {
 ; CHECK-LABEL: load_test13:
 ; CHECK:         .functype load_test13 (i32, i32) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $1, $pop0
-; CHECK-NEXT:    i32.add $push2=, $pop1, $0
-; CHECK-NEXT:    i32.const $push3=, 40
-; CHECK-NEXT:    i32.add $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.load $push5=, 0($pop4)
-; CHECK-NEXT:    return $pop5
+; CHECK-NEXT:    i32.add $push2=, $0, $pop1
+; CHECK-NEXT:    i32.load $push3=, 40($pop2)
+; CHECK-NEXT:    return $pop3
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds i32, ptr %p, i32 %add
   %t = load i32, ptr %arrayidx, align 4
   ret i32 %t
 }
 
 define i32 @load_test14(ptr %p, i32 %n) {
 ; CHECK-LABEL: load_test14:

 }
 
 define i32 @load_test17(ptr %p, i32 %n) {
 ; CHECK-LABEL: load_test17:
 ; CHECK:         .functype load_test17 (i32, i32) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $1, $pop0
-; CHECK-NEXT:    i32.add $push2=, $pop1, $0
-; CHECK-NEXT:    i32.const $push3=, 40
-; CHECK-NEXT:    i32.add $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.load $push5=, 0($pop4)
-; CHECK-NEXT:    return $pop5
+; CHECK-NEXT:    i32.add $push2=, $0, $pop1
+; CHECK-NEXT:    i32.load $push3=, 40($pop2)
+; CHECK-NEXT:    return $pop3
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds i32, ptr %p, i32 %add
   %t = load i32, ptr %add.ptr, align 4
   ret i32 %t
 }
 
 define i32 @load_test18(ptr %p, i32 %n) {
 ; CHECK-LABEL: load_test18:

 }
 
 define i32 @load_test19(ptr %p, i32 %n) {
 ; CHECK-LABEL: load_test19:
 ; CHECK:         .functype load_test19 (i32, i32) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $1, $pop0
-; CHECK-NEXT:    i32.add $push2=, $pop1, $0
-; CHECK-NEXT:    i32.const $push3=, 40
-; CHECK-NEXT:    i32.add $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.load $push5=, 0($pop4)
-; CHECK-NEXT:    return $pop5
+; CHECK-NEXT:    i32.add $push2=, $0, $pop1
+; CHECK-NEXT:    i32.load $push3=, 40($pop2)
+; CHECK-NEXT:    return $pop3
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds i32, ptr %p, i32 %add
   %t = load i32, ptr %add.ptr, align 4
   ret i32 %t
 }
 
 define i32 @load_test20(ptr %p) {
 ; CHECK-LABEL: load_test20:
; CHECK-NEXT:    return
   store i32 %i, ptr getelementptr ([0 x i32], ptr @g, i32 0, i32 10), align 4
   ret void
 }
 
 define void @store_test1(i32 %n, i32 %i) {
 ; CHECK-LABEL: store_test1:
 ; CHECK:         .functype store_test1 (i32, i32) -> ()
 ; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    global.get $push2=, g@GOT
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $0, $pop0
-; CHECK-NEXT:    global.get $push2=, g@GOT
-; CHECK-NEXT:    i32.add $push3=, $pop1, $pop2
-; CHECK-NEXT:    i32.const $push4=, 40
-; CHECK-NEXT:    i32.add $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.store 0($pop5), $1
+; CHECK-NEXT:    i32.add $push3=, $pop2, $pop1
+; CHECK-NEXT:    i32.store 40($pop3), $1
 ; CHECK-NEXT:    return
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds [0 x i32], ptr @g, i32 0, i32 %add
   store i32 %i, ptr %arrayidx, align 4
   ret void
 }
 
 define void @store_test2(i32 %n, i32 %i) {
 ; CHECK-LABEL: store_test2:
 ; CHECK:         .functype store_test2 (i32, i32) -> ()
 ; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    global.get $push2=, g@GOT
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $0, $pop0
-; CHECK-NEXT:    global.get $push2=, g@GOT
-; CHECK-NEXT:    i32.add $push3=, $pop1, $pop2
-; CHECK-NEXT:    i32.const $push4=, 40
-; CHECK-NEXT:    i32.add $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.store 0($pop5), $1
+; CHECK-NEXT:    i32.add $push3=, $pop2, $pop1
+; CHECK-NEXT:    i32.store 40($pop3), $1
 ; CHECK-NEXT:    return
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds [0 x i32], ptr @g, i32 0, i32 %add
   store i32 %i, ptr %arrayidx, align 4
   ret void
 }
 
 define void @store_test3(i32 %n, i32 %i) {
; CHECK-NEXT:    return
   store i32 %i, ptr %add.ptr, align 4
   ret void
 }
 
 define void @store_test6(i32 %n, i32 %i) {
 ; CHECK-LABEL: store_test6:
 ; CHECK:         .functype store_test6 (i32, i32) -> ()
 ; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    global.get $push2=, g@GOT
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $0, $pop0
-; CHECK-NEXT:    global.get $push2=, g@GOT
-; CHECK-NEXT:    i32.add $push3=, $pop1, $pop2
-; CHECK-NEXT:    i32.const $push4=, 40
-; CHECK-NEXT:    i32.add $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.store 0($pop5), $1
+; CHECK-NEXT:    i32.add $push3=, $pop2, $pop1
+; CHECK-NEXT:    i32.store 40($pop3), $1
 ; CHECK-NEXT:    return
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds [0 x i32], ptr @g, i32 0, i32 %add
   store i32 %i, ptr %add.ptr, align 4
   ret void
 }
 
 define void @store_test7(i32 %n, i32 %i) {
; CHECK-NEXT:    return
   store i32 %i, ptr %add.ptr1, align 4
   ret void
 }
 
 define void @store_test8(i32 %n, i32 %i) {
 ; CHECK-LABEL: store_test8:
 ; CHECK:         .functype store_test8 (i32, i32) -> ()
 ; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    global.get $push2=, g@GOT
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $0, $pop0
-; CHECK-NEXT:    global.get $push2=, g@GOT
-; CHECK-NEXT:    i32.add $push3=, $pop1, $pop2
-; CHECK-NEXT:    i32.const $push4=, 40
-; CHECK-NEXT:    i32.add $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.store 0($pop5), $1
+; CHECK-NEXT:    i32.add $push3=, $pop2, $pop1
+; CHECK-NEXT:    i32.store 40($pop3), $1
 ; CHECK-NEXT:    return
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds [0 x i32], ptr @g, i32 0, i32 %add
   store i32 %i, ptr %add.ptr, align 4
   ret void
 }
 
 define void @store_test9(i32 %i) {

 }
 
 define void @store_test12(ptr %p, i32 %n, i32 %i) {
 ; CHECK-LABEL: store_test12:
 ; CHECK:         .functype store_test12 (i32, i32, i32) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $1, $pop0
-; CHECK-NEXT:    i32.add $push2=, $pop1, $0
-; CHECK-NEXT:    i32.const $push3=, 40
-; CHECK-NEXT:    i32.add $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.store 0($pop4), $2
+; CHECK-NEXT:    i32.add $push2=, $0, $pop1
+; CHECK-NEXT:    i32.store 40($pop2), $2
 ; CHECK-NEXT:    return
   %add = add nsw i32 %n, 10
   %arrayidx = getelementptr inbounds i32, ptr %p, i32 %add
   store i32 %i, ptr %arrayidx, align 4
   ret void
 }
 
 define void @store_test13(ptr %p, i32 %n, i32 %i) {
 ; CHECK-LABEL: store_test13:
 ; CHECK:         .functype store_test13 (i32, i32, i32) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $1, $pop0
-; CHECK-NEXT:    i32.add $push2=, $pop1, $0
-; CHECK-NEXT:    i32.const $push3=, 40
-; CHECK-NEXT:    i32.add $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.store 0($pop4), $2
+; CHECK-NEXT:    i32.add $push2=, $0, $pop1
+; CHECK-NEXT:    i32.store 40($pop2), $2
 ; CHECK-NEXT:    return
   %add = add nsw i32 10, %n
   %arrayidx = getelementptr inbounds i32, ptr %p, i32 %add
   store i32 %i, ptr %arrayidx, align 4
   ret void
 }
 
 define void @store_test14(ptr %p, i32 %n, i32 %i) {

 }
 
 define void @store_test17(ptr %p, i32 %n, i32 %i) {
 ; CHECK-LABEL: store_test17:
 ; CHECK:         .functype store_test17 (i32, i32, i32) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $1, $pop0
-; CHECK-NEXT:    i32.add $push2=, $pop1, $0
-; CHECK-NEXT:    i32.const $push3=, 40
-; CHECK-NEXT:    i32.add $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.store 0($pop4), $2
+; CHECK-NEXT:    i32.add $push2=, $0, $pop1
+; CHECK-NEXT:    i32.store 40($pop2), $2
 ; CHECK-NEXT:    return
   %add = add nsw i32 %n, 10
   %add.ptr = getelementptr inbounds i32, ptr %p, i32 %add
   store i32 %i, ptr %add.ptr, align 4
   ret void
 }
 
 define void @store_test18(ptr %p, i32 %n, i32 %i) {

 }
 
 define void @store_test19(ptr %p, i32 %n, i32 %i) {
 ; CHECK-LABEL: store_test19:
 ; CHECK:         .functype store_test19 (i32, i32, i32) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const $push0=, 2
 ; CHECK-NEXT:    i32.shl $push1=, $1, $pop0
-; CHECK-NEXT:    i32.add $push2=, $pop1, $0
-; CHECK-NEXT:    i32.const $push3=, 40
-; CHECK-NEXT:    i32.add $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.store 0($pop4), $2
+; CHECK-NEXT:    i32.add $push2=, $0, $pop1
+; CHECK-NEXT:    i32.store 40($pop2), $2
 ; CHECK-NEXT:    return
   %add = add nsw i32 10, %n
   %add.ptr = getelementptr inbounds i32, ptr %p, i32 %add
   store i32 %i, ptr %add.ptr, align 4
   ret void
 }
 
 define void @store_test20(ptr %p, i32 %i) {

llvm/test/CodeGen/WebAssembly/cfg-stackify.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck %s
+; RUN: llc < %s -start-after=licm -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck %s
 
 ; Test the CFG stackifier pass.
 
 ; Explicitly disable fast-isel, since it gets implicitly enabled in the
 ; optnone test.
 
 target triple = "wasm32-unknown-unknown"
 

llvm/test/CodeGen/WebAssembly/debugtrap.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -start-after=licm -asm-verbose=false -verify-machineinstrs | FileCheck %s
 
 ; Test lowering of __builtin_debugtrap in cases where lowering it via
 ; the normal UNREACHABLE instruction would yield invalid
 ; MachineFunctions.
 
 target triple = "wasm32"
 
 declare void @llvm.debugtrap()

llvm/test/CodeGen/WebAssembly/fast-isel-br-i1.ll

-; RUN: llc < %s -fast-isel -asm-verbose=false -wasm-keep-registers | FileCheck %s
+; RUN: llc < %s -start-after=licm -fast-isel -asm-verbose=false -wasm-keep-registers | FileCheck %s
 
 target triple = "wasm32-unknown-unknown"
 
 ; Fast-isel uses a 32-bit xor with -1 to negate i1 values, because it doesn't
 ; make any guarantees about the contents of the high bits of a register holding
 ; an i1 value. Test that when we do a `br_if` or `br_unless` with what what an
 ; i1 value in LLVM IR, that we only test the low bit.
 

llvm/test/CodeGen/WebAssembly/fpclamptosat.ll

 
 define i32 @stest_f16i32(half %x) {
 ; CHECK-LABEL: stest_f16i32:
 ; CHECK:         .functype stest_f16i32 (f32) -> (i32)
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi half %x to i64
   %0 = icmp slt i64 %conv, 2147483647
   %spec.store.select = select i1 %0, i64 %conv, i64 2147483647
   %1 = icmp sgt i64 %spec.store.select, -2147483648
   %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 -2147483648
   %conv6 = trunc i64 %spec.store.select7 to i32
   ret i32 %conv6
 }
 
 define i32 @utesth_f16i32(half %x) {
 ; CHECK-LABEL: utesth_f16i32:
 ; CHECK:         .functype utesth_f16i32 (f32) -> (i32)
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui half %x to i64
   %0 = icmp ult i64 %conv, 4294967295
   %spec.store.select = select i1 %0, i64 %conv, i64 4294967295
   %conv6 = trunc i64 %spec.store.select to i32
   ret i32 %conv6
 }
 
 define i32 @ustest_f16i32(half %x) {
 ; CHECK-LABEL: ustest_f16i32:
 ; CHECK:         .functype ustest_f16i32 (f32) -> (i32)
+; CHECK-NEXT:    .local i64
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    local.tee 1
+; CHECK-NEXT:    i64.const 0
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    i64.const 0
+; CHECK-NEXT:    i64.gt_s
+; CHECK-NEXT:    i64.select
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi half %x to i64
   %0 = icmp slt i64 %conv, 4294967295
   %spec.store.select = select i1 %0, i64 %conv, i64 4294967295
   %1 = icmp sgt i64 %spec.store.select, 0
   %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 0
   %conv6 = trunc i64 %spec.store.select7 to i32
entry:
   %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 -32768
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @utesth_f16i16(half %x) {
 ; CHECK-LABEL: utesth_f16i16:
 ; CHECK:         .functype utesth_f16i16 (f32) -> (i32)
-; CHECK-NEXT:    .local i32
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    local.tee 1
-; CHECK-NEXT:    i32.const 65535
-; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.const 65535
-; CHECK-NEXT:    i32.lt_u
-; CHECK-NEXT:    i32.select
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui half %x to i32
   %0 = icmp ult i32 %conv, 65535
   %spec.store.select = select i1 %0, i32 %conv, i32 65535
   %conv6 = trunc i32 %spec.store.select to i16
   ret i16 %conv6
 }
 
 define i16 @ustest_f16i16(half %x) {
 ; CHECK-LABEL: ustest_f16i16:
 ; CHECK:         .functype ustest_f16i16 (f32) -> (i32)
 ; CHECK-NEXT:    .local i32
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    local.tee 1
-; CHECK-NEXT:    i32.const 65535
-; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.const 65535
-; CHECK-NEXT:    i32.lt_s
-; CHECK-NEXT:    i32.select
-; CHECK-NEXT:    local.tee 1
 ; CHECK-NEXT:    i32.const 0
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    i32.const 0
 ; CHECK-NEXT:    i32.gt_s
 ; CHECK-NEXT:    i32.select
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi half %x to i32
entry:
   %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 -9223372036854775808
   %conv6 = trunc i128 %spec.store.select7 to i64
   ret i64 %conv6
 }
 
 define i64 @utesth_f16i64(half %x) {
 ; CHECK-LABEL: utesth_f16i64:
 ; CHECK:         .functype utesth_f16i64 (f32) -> (i64)
-; CHECK-NEXT:    .local i32, i64, i64
+; CHECK-NEXT:    .local i32, i64
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    global.get __stack_pointer
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.sub
 ; CHECK-NEXT:    local.tee 1
 ; CHECK-NEXT:    global.set __stack_pointer
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    call __fixunssfti
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.const 8
-; CHECK-NEXT:    i32.add
 ; CHECK-NEXT:    i64.load 0
 ; CHECK-NEXT:    local.set 2
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i64.load 0
-; CHECK-NEXT:    local.set 3
-; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
 ; CHECK-NEXT:    global.set __stack_pointer
-; CHECK-NEXT:    local.get 3
-; CHECK-NEXT:    i64.const 0
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i64.eqz
-; CHECK-NEXT:    i64.select
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui half %x to i128
   %0 = icmp ult i128 %conv, 18446744073709551616
   %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616
   %conv6 = trunc i128 %spec.store.select to i64
   ret i64 %conv6
 }

 
 define i32 @stest_f16i32_mm(half %x) {
 ; CHECK-LABEL: stest_f16i32_mm:
 ; CHECK:         .functype stest_f16i32_mm (f32) -> (i32)
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi half %x to i64
   %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647)
   %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648)
   %conv6 = trunc i64 %spec.store.select7 to i32
   ret i32 %conv6
 }
 
 define i32 @utesth_f16i32_mm(half %x) {
 ; CHECK-LABEL: utesth_f16i32_mm:
 ; CHECK:         .functype utesth_f16i32_mm (f32) -> (i32)
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui half %x to i64
   %spec.store.select = call i64 @llvm.umin.i64(i64 %conv, i64 4294967295)
   %conv6 = trunc i64 %spec.store.select to i32
   ret i32 %conv6
 }
 
 define i32 @ustest_f16i32_mm(half %x) {
 ; CHECK-LABEL: ustest_f16i32_mm:
 ; CHECK:         .functype ustest_f16i32_mm (f32) -> (i32)
+; CHECK-NEXT:    .local i64
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    local.tee 1
+; CHECK-NEXT:    i64.const 0
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    i64.const 0
+; CHECK-NEXT:    i64.gt_s
+; CHECK-NEXT:    i64.select
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi half %x to i64
   %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 4294967295)
   %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 0)
   %conv6 = trunc i64 %spec.store.select7 to i32
   ret i32 %conv6
 }
entry:
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 
 define i16 @utesth_f16i16_mm(half %x) {
 ; CHECK-LABEL: utesth_f16i16_mm:
 ; CHECK:         .functype utesth_f16i16_mm (f32) -> (i32)
-; CHECK-NEXT:    .local i32
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    local.tee 1
-; CHECK-NEXT:    i32.const 65535
-; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.const 65535
-; CHECK-NEXT:    i32.lt_u
-; CHECK-NEXT:    i32.select
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui half %x to i32
   %spec.store.select = call i32 @llvm.umin.i32(i32 %conv, i32 65535)
   %conv6 = trunc i32 %spec.store.select to i16
   ret i16 %conv6
 }
 
 define i16 @ustest_f16i16_mm(half %x) {
 ; CHECK-LABEL: ustest_f16i16_mm:
 ; CHECK:         .functype ustest_f16i16_mm (f32) -> (i32)
 ; CHECK-NEXT:    .local i32
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    local.tee 1
-; CHECK-NEXT:    i32.const 65535
-; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.const 65535
-; CHECK-NEXT:    i32.lt_s
-; CHECK-NEXT:    i32.select
-; CHECK-NEXT:    local.tee 1
 ; CHECK-NEXT:    i32.const 0
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    i32.const 0
 ; CHECK-NEXT:    i32.gt_s
 ; CHECK-NEXT:    i32.select
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi half %x to i32
entry:
   %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)
   %conv6 = trunc i128 %spec.store.select7 to i64
   ret i64 %conv6
 }
 
 define i64 @utesth_f16i64_mm(half %x) {
 ; CHECK-LABEL: utesth_f16i64_mm:
 ; CHECK:         .functype utesth_f16i64_mm (f32) -> (i64)
-; CHECK-NEXT:    .local i32, i64, i64
+; CHECK-NEXT:    .local i32, i64
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    global.get __stack_pointer
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.sub
 ; CHECK-NEXT:    local.tee 1
 ; CHECK-NEXT:    global.set __stack_pointer
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    call __fixunssfti
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.const 8
-; CHECK-NEXT:    i32.add
 ; CHECK-NEXT:    i64.load 0
 ; CHECK-NEXT:    local.set 2
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i64.load 0
-; CHECK-NEXT:    local.set 3
-; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
 ; CHECK-NEXT:    global.set __stack_pointer
-; CHECK-NEXT:    i64.const 0
-; CHECK-NEXT:    local.get 3
-; CHECK-NEXT:    i64.const 0
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i64.eqz
-; CHECK-NEXT:    i64.select
-; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i64.const 1
-; CHECK-NEXT:    i64.eq
-; CHECK-NEXT:    i64.select
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui half %x to i128
   %spec.store.select = call i128 @llvm.umin.i128(i128 %conv, i128 18446744073709551616)
   %conv6 = trunc i128 %spec.store.select to i64
   ret i64 %conv6
 }
 

llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll

 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    local.set 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 3
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi <4 x half> %x to <4 x i64>
   %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
   %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
   %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
   %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
   %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
   ret <4 x i32> %conv6
 }
 
 define <4 x i32> @utesth_f16i32(<4 x half> %x) {
 ; CHECK-LABEL: utesth_f16i32:
 ; CHECK:         .functype utesth_f16i32 (f32, f32, f32, f32) -> (v128)
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    local.set 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 3
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui <4 x half> %x to <4 x i64>
   %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
   %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
   %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
   ret <4 x i32> %conv6
 }
 
 define <4 x i32> @ustest_f16i32(<4 x half> %x) {
 ; CHECK-LABEL: ustest_f16i32:
 ; CHECK:         .functype ustest_f16i32 (f32, f32, f32, f32) -> (v128)
+; CHECK-NEXT:    .local v128, v128
 ; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    local.get 3
+; CHECK-NEXT:    call __truncsfhf2
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    local.set 3
+; CHECK-NEXT:    local.get 2
+; CHECK-NEXT:    call __truncsfhf2
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    local.set 2
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    local.set 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    i32x4.splat
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i64x2.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    i32x4.replace_lane 1
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i64x2.replace_lane 1
+; CHECK-NEXT:    local.tee 4
+; CHECK-NEXT:    v128.const 0, 0
+; CHECK-NEXT:    local.tee 5
+; CHECK-NEXT:    local.get 4
+; CHECK-NEXT:    local.get 5
+; CHECK-NEXT:    i64x2.gt_s
+; CHECK-NEXT:    v128.bitselect
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    call __truncsfhf2
-; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    i32x4.replace_lane 2
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i64x2.splat
 ; CHECK-NEXT:    local.get 3
-; CHECK-NEXT:    call __truncsfhf2
-; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    i32x4.replace_lane 3
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i64x2.replace_lane 1
+; CHECK-NEXT:    local.tee 4
+; CHECK-NEXT:    local.get 5
+; CHECK-NEXT:    local.get 4
+; CHECK-NEXT:    local.get 5
+; CHECK-NEXT:    i64x2.gt_s
+; CHECK-NEXT:    v128.bitselect
+; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi <4 x half> %x to <4 x i64>
   %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
   %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
   %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer
   %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer
   %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>

 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 3
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    v128.const 65535, 65535, 65535, 65535
 ; CHECK-NEXT:    local.tee 8
-; CHECK-NEXT:    i32x4.min_u
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    local.get 4
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 5
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 6
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 7
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    local.get 8
-; CHECK-NEXT:    i32x4.min_u
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    i16x8.narrow_i32x4_u
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui <8 x half> %x to <8 x i32>
   %0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
   %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
   %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>
   ret <8 x i16> %conv6

 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 3
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 3
-; CHECK-NEXT:    v128.const 65535, 65535, 65535, 65535
-; CHECK-NEXT:    local.tee 8
-; CHECK-NEXT:    i32x4.min_s
 ; CHECK-NEXT:    v128.const 0, 0, 0, 0
-; CHECK-NEXT:    local.tee 9
+; CHECK-NEXT:    local.tee 8
 ; CHECK-NEXT:    i32x4.max_s
+; CHECK-NEXT:    v128.const 65535, 65535, 65535, 65535
+; CHECK-NEXT:    local.tee 9
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    local.get 4
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 5
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 6
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 7
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    local.get 8
-; CHECK-NEXT:    i32x4.min_s
-; CHECK-NEXT:    local.get 9
 ; CHECK-NEXT:    i32x4.max_s
+; CHECK-NEXT:    local.get 9
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    i16x8.narrow_i32x4_u
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi <8 x half> %x to <8 x i32>
   %0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
   %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
   %1 = icmp sgt <8 x i32> %spec.store.select, zeroinitializer
   %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> zeroinitializer
entry:
   %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
   %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
   ret <2 x i64> %conv6
 }
 
 define <2 x i64> @utesth_f16i64(<2 x half> %x) {
 ; CHECK-LABEL: utesth_f16i64:
 ; CHECK:         .functype utesth_f16i64 (f32, f32) -> (v128)
-; CHECK-NEXT:    .local i32, i64, i64, i64, i64
+; CHECK-NEXT:    .local i32, v128
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    global.get __stack_pointer
 ; CHECK-NEXT:    i32.const 32
 ; CHECK-NEXT:    i32.sub
 ; CHECK-NEXT:    local.tee 2
 ; CHECK-NEXT:    global.set __stack_pointer
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i32.const 16
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    call __truncsfhf2
-; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    call __fixunssfti
-; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    call __fixunssfti
 ; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i32.const 8
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i64.load 0
-; CHECK-NEXT:    local.set 3
-; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i64.load 16
-; CHECK-NEXT:    local.set 4
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    call __truncsfhf2
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    call __fixunssfti
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i32.const 8
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i64.load 0
-; CHECK-NEXT:    local.set 5
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i64.load 0
-; CHECK-NEXT:    local.set 6
+; CHECK-NEXT:    v128.load64_splat 0
+; CHECK-NEXT:    v128.load64_lane 16, 1
+; CHECK-NEXT:    local.set 3
 ; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    i32.const 32
 ; CHECK-NEXT:    i32.add
 ; CHECK-NEXT:    global.set __stack_pointer
-; CHECK-NEXT:    local.get 6
-; CHECK-NEXT:    i64.const 0
-; CHECK-NEXT:    local.get 5
-; CHECK-NEXT:    i64.eqz
-; CHECK-NEXT:    i64.select
-; CHECK-NEXT:    i64x2.splat
-; CHECK-NEXT:    local.get 4
-; CHECK-NEXT:    i64.const 0
 ; CHECK-NEXT:    local.get 3
-; CHECK-NEXT:    i64.eqz
-; CHECK-NEXT:    i64.select
-; CHECK-NEXT:    i64x2.replace_lane 1
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui <2 x half> %x to <2 x i128>
   %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
   %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
   %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
   ret <2 x i64> %conv6
 }

 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    local.set 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 3
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_s
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi <4 x half> %x to <4 x i64>
   %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
   %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)
   %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
   ret <4 x i32> %conv6
 }
 
 define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
 ; CHECK-LABEL: utesth_f16i32_mm:
 ; CHECK:         .functype utesth_f16i32_mm (f32, f32, f32, f32) -> (v128)
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    local.set 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 3
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
+; CHECK-NEXT:    i64.trunc_sat_f32_u
+; CHECK-NEXT:    i32.wrap_i64
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui <4 x half> %x to <4 x i64>
   %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
   %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
   ret <4 x i32> %conv6
 }
 
 define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
 ; CHECK-LABEL: ustest_f16i32_mm:
 ; CHECK:         .functype ustest_f16i32_mm (f32, f32, f32, f32) -> (v128)
+; CHECK-NEXT:    .local v128, v128
 ; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    local.get 3
+; CHECK-NEXT:    call __truncsfhf2
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    local.set 3
+; CHECK-NEXT:    local.get 2
+; CHECK-NEXT:    call __truncsfhf2
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    local.set 2
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    local.set 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    i32x4.splat
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i64x2.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    i32x4.replace_lane 1
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i64x2.replace_lane 1
+; CHECK-NEXT:    local.tee 4
+; CHECK-NEXT:    v128.const 0, 0
+; CHECK-NEXT:    local.tee 5
+; CHECK-NEXT:    local.get 4
+; CHECK-NEXT:    local.get 5
+; CHECK-NEXT:    i64x2.gt_s
+; CHECK-NEXT:    v128.bitselect
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    call __truncsfhf2
-; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    i32x4.replace_lane 2
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i64x2.splat
 ; CHECK-NEXT:    local.get 3
-; CHECK-NEXT:    call __truncsfhf2
-; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    i32.trunc_sat_f32_u
-; CHECK-NEXT:    i32x4.replace_lane 3
+; CHECK-NEXT:    i64.trunc_sat_f32_s
+; CHECK-NEXT:    i64x2.replace_lane 1
+; CHECK-NEXT:    local.tee 4
+; CHECK-NEXT:    local.get 5
+; CHECK-NEXT:    local.get 4
+; CHECK-NEXT:    local.get 5
+; CHECK-NEXT:    i64x2.gt_s
+; CHECK-NEXT:    v128.bitselect
+; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi <4 x half> %x to <4 x i64>
   %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
   %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)
   %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
   ret <4 x i32> %conv6
 }

 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 3
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    v128.const 65535, 65535, 65535, 65535
 ; CHECK-NEXT:    local.tee 8
-; CHECK-NEXT:    i32x4.min_u
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    local.get 4
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 5
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 6
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 7
 ; CHECK-NEXT:    i32.trunc_sat_f32_u
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    local.get 8
-; CHECK-NEXT:    i32x4.min_u
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    i16x8.narrow_i32x4_u
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui <8 x half> %x to <8 x i32>
   %spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
   %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>
   ret <8 x i16> %conv6
 }

 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 3
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 3
-; CHECK-NEXT:    v128.const 65535, 65535, 65535, 65535
-; CHECK-NEXT:    local.tee 8
-; CHECK-NEXT:    i32x4.min_s
 ; CHECK-NEXT:    v128.const 0, 0, 0, 0
-; CHECK-NEXT:    local.tee 9
+; CHECK-NEXT:    local.tee 8
 ; CHECK-NEXT:    i32x4.max_s
+; CHECK-NEXT:    v128.const 65535, 65535, 65535, 65535
+; CHECK-NEXT:    local.tee 9
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    local.get 4
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 5
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 6
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 7
 ; CHECK-NEXT:    i32.trunc_sat_f32_s
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    local.get 8
-; CHECK-NEXT:    i32x4.min_s
-; CHECK-NEXT:    local.get 9
 ; CHECK-NEXT:    i32x4.max_s
+; CHECK-NEXT:    local.get 9
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    i16x8.narrow_i32x4_u
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptosi <8 x half> %x to <8 x i32>
   %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
   %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> zeroinitializer)
   %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
   ret <8 x i16> %conv6
entry:
   %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
   %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
   ret <2 x i64> %conv6
 }
 
 define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
 ; CHECK-LABEL: utesth_f16i64_mm:
 ; CHECK:         .functype utesth_f16i64_mm (f32, f32) -> (v128)
-; CHECK-NEXT:    .local i32, i64, i64, i64, i64
+; CHECK-NEXT:    .local i32, v128
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    global.get __stack_pointer
 ; CHECK-NEXT:    i32.const 32
 ; CHECK-NEXT:    i32.sub
 ; CHECK-NEXT:    local.tee 2
 ; CHECK-NEXT:    global.set __stack_pointer
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i32.const 16
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    call __truncsfhf2
-; CHECK-NEXT:    call __extendhfsf2
-; CHECK-NEXT:    call __fixunssfti
-; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    call __truncsfhf2
 ; CHECK-NEXT:    call __extendhfsf2
 ; CHECK-NEXT:    call __fixunssfti
 ; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i32.const 8
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i64.load 0
-; CHECK-NEXT:    local.set 3
-; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i64.load 16
-; CHECK-NEXT:    local.set 4
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    call __truncsfhf2
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    call __fixunssfti
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i32.const 8
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i64.load 0
-; CHECK-NEXT:    local.set 5
 ; CHECK-NEXT:    local.get 2
-; CHECK-NEXT:    i64.load 0
-; CHECK-NEXT:    local.set 6
+; CHECK-NEXT:    v128.load64_splat 0
+; CHECK-NEXT:    v128.load64_lane 16, 1
+; CHECK-NEXT:    local.set 3
 ; CHECK-NEXT:    local.get 2
 ; CHECK-NEXT:    i32.const 32
 ; CHECK-NEXT:    i32.add
 ; CHECK-NEXT:    global.set __stack_pointer
-; CHECK-NEXT:    i64.const 0
-; CHECK-NEXT:    local.get 6
-; CHECK-NEXT:    i64.const 0
-; CHECK-NEXT:    local.get 5
-; CHECK-NEXT:    i64.eqz
-; CHECK-NEXT:    i64.select
-; CHECK-NEXT:    local.get 5
-; CHECK-NEXT:    i64.const 1
-; CHECK-NEXT:    i64.eq
-; CHECK-NEXT:    i64.select
-; CHECK-NEXT:    i64x2.splat
-; CHECK-NEXT:    i64.const 0
-; CHECK-NEXT:    local.get 4
-; CHECK-NEXT:    i64.const 0
 ; CHECK-NEXT:    local.get 3
-; CHECK-NEXT:    i64.eqz
-; CHECK-NEXT:    i64.select
-; CHECK-NEXT:    local.get 3
-; CHECK-NEXT:    i64.const 1
-; CHECK-NEXT:    i64.eq
-; CHECK-NEXT:    i64.select
-; CHECK-NEXT:    i64x2.replace_lane 1
 ; CHECK-NEXT:    # fallthrough-return
 entry:
   %conv = fptoui <2 x half> %x to <2 x i128>
   %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
   %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
   ret <2 x i64> %conv6
 }
 

llvm/test/CodeGen/WebAssembly/function-addr-offset.ll

-; RUN: llc < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -start-after=licm -verify-machineinstrs | FileCheck %s
 
 ; Wasm does not currently support function addresses with offsets, so we
 ; shouldn't try to create a folded SDNode like (function + offset). This is a
 ; regression test for the folding bug and this should not crash in MCInstLower.
 
 target triple = "wasm32-unknown-unknown"
 
 ; 'hidden' here should be present to reproduce the bug

llvm/test/CodeGen/WebAssembly/implicit-def.ll

-; RUN: llc -o - %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -mattr=+simd128 | FileCheck %s
+; RUN: llc -o - %s -start-after=licm -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -mattr=+simd128 | FileCheck %s
 
 target triple = "wasm32-unknown-unknown"
 
 ; Test that stackified IMPLICIT_DEF instructions are converted into
 ; CONST_XXX instructions to provide an explicit push.
 
 ; CHECK-LABEL: implicit_def_i32:
 ; CHECK:      i32.const $push{{[0-9]+}}=, 0{{$}}

llvm/test/CodeGen/WebAssembly/ir-locals.ll

-; RUN: llc < %s --mtriple=wasm32-unknown-unknown -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -start-after=licm --mtriple=wasm32-unknown-unknown -asm-verbose=false | FileCheck %s
 
 %i32_cell = type ptr addrspace(1)
 %i64_cell = type ptr addrspace(1)
 %f32_cell = type ptr addrspace(1)
 %f64_cell = type ptr addrspace(1)
 
 ; We have a set of tests in which we set a local and then reload the
 ; local.  If the load immediately follows the set, the DAG combiner will

llvm/test/CodeGen/WebAssembly/libcalls.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+; RUN: llc < %s -start-after=early-cse -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 
 ; Test a subset of compiler-rt/libm libcalls expected to be emitted by the wasm backend
 
 target triple = "wasm32-unknown-unknown"
 
 declare fp128 @llvm.sqrt.f128(fp128)
 declare fp128 @llvm.floor.f128(fp128)
 declare fp128 @llvm.trunc.f128(fp128)

llvm/test/CodeGen/WebAssembly/load-store-pic.ll

; CHECK-NEXT:    end_function
   ret i32 %1
 }
 
 define i32 @load_hidden_global_offset() {
 ; CHECK-LABEL: load_hidden_global_offset:
 ; PIC:         global.get $push[[L0:[0-9]+]]=, __memory_base{{$}}
 ; PIC-NEXT:    [[PTR]].const $push[[L1:[0-9]+]]=, hidden_global_array@MBREL{{$}}
 ; PIC-NEXT:    [[PTR]].add $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1:[0-9]+]]{{$}}
-; PIC-NEXT:    [[PTR]].const $push[[L3:[0-9]+]]=, 20{{$}}
-; PIC-NEXT:    [[PTR]].add $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
-; PIC-NEXT:    i32.load $push{{[0-9]+}}=, 0($pop[[L4]]){{$}}
+; PIC-NEXT:    i32.load $push{{[0-9]+}}=, 20($pop[[L2]]){{$}}
 ; CHECK-NEXT:  end_function
 
   %1 = getelementptr [10 x i32], ptr @hidden_global_array, i32 0, i32 5
   %2 = load i32, ptr %1
   ret i32 %2
 }
 
 ; Store to a hidden global
 
 define void @store_hidden_global(i32 %n) {
 ; CHECK-LABEL: store_hidden_global:
 ; PIC:         global.get $push[[L0:[0-9]+]]=, __memory_base{{$}}
-; PIC-NEXT:    [[PTR]].const $push[[L1:[0-9]+]]=, hidden_global@MBREL{{$}}
+; PIC-NEXT:    [[PTR]].const $push[[L1:[0-9]+]]=, hidden_global@MBREL
 ; PIC-NEXT:    [[PTR]].add $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; PIC-NEXT:    i32.store 0($pop[[L2]]), $0{{$}}
-; CHECK-NEXT:    end_function
+; CHECK-NEXT:   end_function
 
   store i32 %n, ptr @hidden_global
   ret void
 }
 
 define void @store_hidden_global_offset(i32 %n) {
 ; CHECK-LABEL: store_hidden_global_offset:
 ; PIC:         global.get $push[[L0:[0-9]+]]=, __memory_base{{$}}
 ; PIC-NEXT:    [[PTR]].const $push[[L1:[0-9]+]]=, hidden_global_array@MBREL{{$}}
 ; PIC-NEXT:    [[PTR]].add $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
-; PIC-NEXT:    [[PTR]].const $push[[L3:[0-9]+]]=, 20{{$}}
-; PIC-NEXT:    [[PTR]].add $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
-; PIC-NEXT:    i32.store 0($pop[[L4]]), $0{{$}}
+; PIC-NEXT:    i32.store 20($pop[[L2]]), $0{{$}}
 
 ; CHECK-NEXT:   end_function
 
   %1 = getelementptr [10 x i32], ptr @hidden_global_array, i32 0, i32 5
   store i32 %n, ptr %1
   ret void
 }
 
; CHECK-NEXT:   end_function
 
   %1 = load i32, ptr @external_global
   ret i32 %1
 }
 
 define i32 @load_external_global_offset() {
 ; CHECK-LABEL:  load_external_global_offset:
 ; PIC:          global.get $push[[L0:[0-9]+]]=, external_global_array@GOT{{$}}
-; PIC-NEXT:     [[PTR]].const $push[[L1:[0-9]+]]=, 20{{$}}
-; PIC-NEXT:     [[PTR]].add $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
-; PIC-NEXT:     i32.load $push{{[0-9]+}}=, 0($pop[[L2]]){{$}}
+; PIC-NEXT:     i32.load $push{{[0-9]+}}=, 20($pop[[L0]]){{$}}
 
 ; CHECK-NEXT:   end_function
 
   %1 = getelementptr [10 x i32], ptr @external_global_array, i32 0, i32 5
   %2 = load i32, ptr %1
   ret i32 %2
 }
 
 ; Store to a non-hidden global via the wasm global.
 
 define void @store_external_global(i32 %n) {
 ; CHECK-LABEL:  store_external_global:
 ; PIC:          global.get $push[[L0:[0-9]+]]=, external_global@GOT{{$}}
 ; PIC-NEXT:     i32.store 0($pop[[L0]]), $0{{$}}
 
 ; CHECK-NEXT:   end_function
 
   store i32 %n, ptr @external_global
   ret void
 }
 
 define void @store_external_global_offset(i32 %n) {
 ; CHECK-LABEL:  store_external_global_offset:
 ; PIC:          global.get $push[[L0:[0-9]+]]=, external_global_array@GOT{{$}}
-; PIC-NEXT:     [[PTR]].const $push[[L1:[0-9]+]]=, 20{{$}}
-; PIC-NEXT:     [[PTR]].add $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
-; PIC-NEXT:     i32.store 0($pop[[L2]]), $0{{$}}
+; PIC-NEXT:     i32.store 20($pop[[L0]]), $0{{$}}
 
 ; CHECK-NEXT:   end_function
 
   %1 = getelementptr [10 x i32], ptr @external_global_array, i32 0, i32 5
   store i32 %n, ptr %1
   ret void
 }

llvm/test/CodeGen/WebAssembly/pr59626.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=wasm32-- -mattr=+simd128 | FileCheck --check-prefix=CHECK-32 %s
 ; RUN: llc < %s -mtriple=wasm64-- -mattr=+simd128 | FileCheck --check-prefix=CHECK-64 %s
 
 define i8 @f(ptr %0, ptr %1) {
 ; CHECK-32-LABEL: f:
 ; CHECK-32:         .functype f (i32, i32) -> (i32)
 ; CHECK-32-NEXT:  # %bb.0: # %BB
 ; CHECK-32-NEXT:    local.get 0
 ; CHECK-32-NEXT:    i32.const 0
 ; CHECK-32-NEXT:    i32.store8 2
 ; CHECK-32-NEXT:    local.get 0
 ; CHECK-32-NEXT:    i32.const 0
 ; CHECK-32-NEXT:    i32.store16 0
 ; CHECK-32-NEXT:    local.get 1
-; CHECK-32-NEXT:    local.get 0
-; CHECK-32-NEXT:    i8x16.splat
-; CHECK-32-NEXT:    v128.store16_lane 0, 0
-; CHECK-32-NEXT:    v128.const 0, 0
-; CHECK-32-NEXT:    i32x4.extract_lane 0
+; CHECK-32-NEXT:    i32.const 5
+; CHECK-32-NEXT:    i32.store8 2
+; CHECK-32-NEXT:    local.get 1
+; CHECK-32-NEXT:    i32.const 769
+; CHECK-32-NEXT:    i32.store16 0
+; CHECK-32-NEXT:    i32.const 1
 ; CHECK-32-NEXT:    # fallthrough-return
 ;
 ; CHECK-64-LABEL: f:
 ; CHECK-64:         .functype f (i64, i64) -> (i32)
-; CHECK-64-NEXT:    .local i32
 ; CHECK-64-NEXT:  # %bb.0: # %BB
 ; CHECK-64-NEXT:    local.get 0
 ; CHECK-64-NEXT:    i32.const 0
 ; CHECK-64-NEXT:    i32.store8 2
 ; CHECK-64-NEXT:    local.get 0
 ; CHECK-64-NEXT:    i32.const 0
 ; CHECK-64-NEXT:    i32.store16 0
 ; CHECK-64-NEXT:    local.get 1
-; CHECK-64-NEXT:    local.get 2
-; CHECK-64-NEXT:    i8x16.splat
-; CHECK-64-NEXT:    v128.store16_lane 0, 0
-; CHECK-64-NEXT:    drop
-; CHECK-64-NEXT:    v128.const 0, 0
-; CHECK-64-NEXT:    i32x4.extract_lane 0
+; CHECK-64-NEXT:    i32.const 5
+; CHECK-64-NEXT:    i32.store8 2
+; CHECK-64-NEXT:    local.get 1
+; CHECK-64-NEXT:    i32.const 769
+; CHECK-64-NEXT:    i32.store16 0
+; CHECK-64-NEXT:    i32.const 1
 ; CHECK-64-NEXT:    # fallthrough-return
 BB:
   store <3 x i8> zeroinitializer, ptr %0
   %S = shufflevector <3 x i128> zeroinitializer, <3 x i128> <i128 0, i128 1, i128 2>, <3 x i32> undef
   %C = icmp ule <3 x i128> %S, zeroinitializer
   %C1 = zext <3 x i1> %C to <3 x i8>
   %E = extractelement <3 x i8> %C1, i32 0
   %B = sdiv <3 x i8> <i8 1, i8 3, i8 5>, %C1
   store <3 x i8> %B, ptr %1
   ret i8 %E
 }

llvm/test/CodeGen/WebAssembly/reg-stackify.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs | FileCheck %s --check-prefix=NOREGS
+; RUN: llc < %s -asm-verbose=false -start-after=licm -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -start-after=licm -disable-wasm-fallthrough-return-opt -verify-machineinstrs | FileCheck %s --check-prefix=NOREGS
 
 ; Test the register stackifier pass.
 
 ; We have two sets of tests, one with registers and implicit locals, and
 ; a stack / explicit locals based version (NOREGS).
 
 target triple = "wasm32-unknown-unknown"
 

llvm/test/CodeGen/WebAssembly/simd-comparisons.ll

 define <4 x i1> @compare_ord_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp ord <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ord_nnan_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .functype compare_ord_nnan_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
-; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
-; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
-; SIMD128-NEXT: return   $pop[[R]]{{$}}
+; SIMD128-NEXT: v128.const $push0=, 1, 1, 1, 1
+; SIMD128-NEXT: return   $pop0
 define <4 x i1> @compare_ord_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp nnan ord <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ord_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .functype compare_sext_ord_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_ord_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp ord <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_sext_ord_nnan_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .functype compare_sext_ord_nnan_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
-; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
-; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
-; SIMD128-NEXT: return   $pop[[R]]{{$}}
+; SIMD128-NEXT: v128.const      $push0=, -1, -1, -1, -1
+; SIMD128-NEXT: return   $pop0
 define <4 x i32> @compare_sext_ord_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp nnan ord <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_ueq_v4f32:
 ; NO-SIMD128-NOT: f32x4

 define <4 x i1> @compare_uno_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp uno <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_uno_nnan_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .functype compare_uno_nnan_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
-; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
-; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; SIMD128-NEXT: v128.const $push0=, 0, 0, 0, 0
+; SIMD128-NEXT: return $pop0
 define <4 x i1> @compare_uno_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
   %res = fcmp nnan uno <4 x float> %x, %y
   ret <4 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uno_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .functype compare_sext_uno_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @compare_sext_uno_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp uno <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_sext_uno_nnan_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .functype compare_sext_uno_nnan_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
-; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
-; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; SIMD128-NEXT: v128.const $push0=, 0, 0, 0, 0
+; SIMD128-NEXT: return $pop0
 define <4 x i32> @compare_sext_uno_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp nnan uno <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_oeq_v2f64:
 ; NO-SIMD128-NOT: f64x2

 define <2 x i1> @compare_ord_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ord <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ord_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ord_nnan_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
-; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
-; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
-; SIMD128-NEXT: return   $pop[[R]]{{$}}
+; SIMD128-NEXT: v128.const $push0=, 1, 1
+; SIMD128-NEXT: return $pop0
 define <2 x i1> @compare_ord_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan ord <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ord_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ord_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ord_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ord <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_ord_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ord_nnan_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
-; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
-; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
-; SIMD128-NEXT: return   $pop[[R]]{{$}}
+; SIMD128-NEXT: v128.const $push0=, -1, -1
+; SIMD128-NEXT: return $pop0
 define <2 x i64> @compare_sext_ord_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan ord <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ueq_v2f64:
 ; NO-SIMD128-NOT: f64x2

 define <2 x i1> @compare_uno_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp uno <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_uno_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uno_nnan_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
-; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
-; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; SIMD128-NEXT: v128.const $push0=, 0, 0
+; SIMD128-NEXT: return $pop0
 define <2 x i1> @compare_uno_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan uno <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uno_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uno_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_uno_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp uno <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_uno_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uno_nnan_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
-; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
-; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; SIMD128-NEXT: v128.const $push0=, 0, 0
+; SIMD128-NEXT: return $pop0
 define <2 x i64> @compare_sext_uno_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan uno <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }

llvm/test/CodeGen/WebAssembly/simd.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+; RUN: llc < %s -start-after=early-cse -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -start-after=early-cse -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 vector manipulation operations assemble as expected.
 
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================

llvm/test/CodeGen/WebAssembly/userstack.ll

-; RUN: llc < %s --mtriple=wasm32-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck -DPTR=32 %s
-; RUN: llc < %s --mtriple=wasm64-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck -DPTR=64 %s
+; RUN: llc < %s -start-after=early-cse --mtriple=wasm32-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck -DPTR=32 %s
+; RUN: llc < %s -start-after=early-cse --mtriple=wasm64-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck -DPTR=64 %s
 
 declare void @ext_func(ptr %ptr)
 declare void @ext_func_i32(ptr %ptr)
 
 ; CHECK: .globaltype  __stack_pointer, i[[PTR]]{{$}}
 
 ; CHECK-LABEL: alloca32:
 ; Check that there is an extra local for the stack pointer.

llvm/test/MC/WebAssembly/stack-ptr-mclower.ll

-; RUN: llc --mtriple=wasm32-unknown-unknown -asm-verbose=false %s -o - | FileCheck --check-prefixes CHECK -DPTR=i32 %s
-; RUN: llc --mtriple=wasm64-unknown-unknown -asm-verbose=false %s -o - | FileCheck --check-prefixes CHECK -DPTR=i64 %s
+; RUN: llc -start-after=early-cse --mtriple=wasm32-unknown-unknown -asm-verbose=false %s -o - | FileCheck --check-prefixes CHECK -DPTR=i32 %s
+; RUN: llc -start-after=early-cse --mtriple=wasm64-unknown-unknown -asm-verbose=false %s -o - | FileCheck --check-prefixes CHECK -DPTR=i64 %s
 
 ; empty function that does not use stack, to check WebAssemblyMCLowerPrePass
 ; works correctly.
 define hidden void @bar() #0 {
   ret void
 }
 
 ; Function that uses explict stack, and should generate a reference to

llvm/test/MC/WebAssembly/stack-ptr.ll

-; RUN: llc --mtriple=wasm32-unknown-unknown -filetype=obj %s -o - | obj2yaml | FileCheck --check-prefixes CHECK,CHK32 %s
-; RUN: llc --mtriple=wasm64-unknown-unknown -filetype=obj %s -o - | obj2yaml | FileCheck --check-prefixes CHECK,CHK64 %s
+; RUN: llc -start-after=early-cse --mtriple=wasm32-unknown-unknown -filetype=obj %s -o - | obj2yaml | FileCheck --check-prefixes CHECK,CHK32 %s
+; RUN: llc -start-after=early-cse --mtriple=wasm64-unknown-unknown -filetype=obj %s -o - | obj2yaml | FileCheck --check-prefixes CHECK,CHK64 %s
 
 ; Function that uses explict stack, and should generate a reference to
 ; __stack_pointer, along with the corresponding reloction entry.
 define hidden void @foo() #0 {
 entry:
   alloca i32, align 4
   ret void
 }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll

-; RUN: llc -enable-machine-outliner -mtriple=wasm32-unknown-linux < %s | FileCheck %s
+; RUN: llc -O1 -enable-machine-outliner -mtriple=wasm32-unknown-linux < %s | FileCheck %s
 
 ; NOTE: Machine outliner doesn't run.
 @x = global i32 0, align 4
 
 define dso_local i32 @check_boundaries() #0 {
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll.generated.expected

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
-; RUN: llc -enable-machine-outliner -mtriple=wasm32-unknown-linux < %s | FileCheck %s
+; RUN: llc -O1 -enable-machine-outliner -mtriple=wasm32-unknown-linux < %s | FileCheck %s
 
 ; NOTE: Machine outliner doesn't run.
 @x = global i32 0, align 4
 
 define dso_local i32 @check_boundaries() #0 {
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/wasm_generated_funcs.ll.nogenerated.expected

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -enable-machine-outliner -mtriple=wasm32-unknown-linux < %s | FileCheck %s
+; RUN: llc -O1 -enable-machine-outliner -mtriple=wasm32-unknown-linux < %s | FileCheck %s
 
 ; NOTE: Machine outliner doesn't run.
 @x = global i32 0, align 4
 
 define dso_local i32 @check_boundaries() #0 {
 ; CHECK-LABEL: check_boundaries:
 ; CHECK:         .functype check_boundaries () -> (i32)
 ; CHECK-NEXT:    .local i32