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[mlir][vector] Fix lowering of permutation maps for transfer_write op
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Authored by ThomasRaoux on Jan 15 2023, 11:12 AM.

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Summary

The lowering of transfer write permutation maps didn't match the op definition:
https://github.com/llvm/llvm-project/blob/93ccccb00d9717b58ba93f0942a243ba6dac4ef6/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td#L1476

Fix the lowering and add a case to the integration test in order to enforce the correct semantic.

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Event Timeline

ThomasRaoux created this revision.Jan 15 2023, 11:12 AM
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ThomasRaoux requested review of this revision.Jan 15 2023, 11:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2023, 11:12 AM

Good catch, thank you!

Could you please also improve the op doc / examples to be more explicit about the equivalence to vector.transpose ?
I.e. here:

 // Read the slice `%A[%i0, %i1:%i1+256, %i2:%i2+32]` into vector<32x256xf32>
...
// or equivalently (rewrite with vector.transpose)

and here:

 // write vector<16x32x64xf32> into the slice
 //   `%A[%i0, %i1:%i1+32, %i2:%i2+64, %i3:%i3+16]`:
...
// or equivalently (rewrite with vector.transpose)

address review comment

Good catch, thank you!

Could you please also improve the op doc / examples to be more explicit about the equivalence to vector.transpose ?
I.e. here:

 // Read the slice `%A[%i0, %i1:%i1+256, %i2:%i2+32]` into vector<32x256xf32>
...
// or equivalently (rewrite with vector.transpose)

and here:

 // write vector<16x32x64xf32> into the slice
 //   `%A[%i0, %i1:%i1+32, %i2:%i2+64, %i3:%i3+16]`:
...
// or equivalently (rewrite with vector.transpose)

Makes sense, added this to the doc.

This revision is now accepted and ready to land.Jan 16 2023, 11:54 PM