Graphcore, AMD, and Qualcomm have proposed two new FP8 formats, Float8E4M3FZN and Float8E5M2FZN. These formats are presented in this paper: https://arxiv.org/abs/2206.02915. They are implemented in commercially available hardware and the ISA for this hardware is available here: https://docs.graphcore.ai/projects/isa-mk2-with-fp8/en/latest/_static/TileVertexISA-IPU21-1.3.1.pdf.
This patch adds support for these two types in MLIR and APFloat, alongside the previously added types Float8E4M3FN and Float8E5M2 (D133823, D137760, RFC).
Following the naming scheme from those existing types, the suffix "FZN" here refers to the fact that these types support finite values, positive-only zero (no negative zero), and a NaN encoding. In both types NaN has exactly one encoding 0b10000000.
To support this behaviour I have added another value to the fltNonfiniteBehavior enum to represent this specific NaN encoding. I have also added a new field (fltSignedZeroSupport) to the fltSemantics struct to describe whether signed zero is supported.