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Differential D141400

[AArch64] Add missing system register for v8.9-A/v9.4-A Permission Indirection Extension
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Authored by pratlucas on Jan 10 2023, 9:09 AM.

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Reviewers
lenary
tmatheson
stuij
tyb0807
Commits
rG8ea4a4b0f47a: [AArch64] Add missing system register for v8.9-A/v9.4-A Permission Indirection…
Summary

This adds support for the missing PIRE0_EL12 system register, part of
v8.9-A/v9.4-A's Permission Indirection Extension.

Patch by Son Tuan Vu.

Diff Detail

Event Timeline

pratlucas created this revision.Jan 10 2023, 9:09 AM
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pratlucas requested review of this revision.Jan 10 2023, 9:09 AM
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pratlucas added reviewers: lenary, tmatheson, stuij, tyb0807.Jan 10 2023, 9:13 AM
tmatheson accepted this revision.Jan 10 2023, 9:20 AM
This revision is now accepted and ready to land.Jan 10 2023, 9:20 AM
Harbormaster completed remote builds in B206817: Diff 487833.Jan 10 2023, 10:03 AM
Closed by commit rG8ea4a4b0f47a: [AArch64] Add missing system register for v8.9-A/v9.4-A Permission Indirection… (authored by pratlucas). · Explain WhyJan 23 2023, 7:01 AM
This revision was automatically updated to reflect the committed changes.
pratlucas added a commit: rG8ea4a4b0f47a: [AArch64] Add missing system register for v8.9-A/v9.4-A Permission Indirection….

Revision Contents

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llvm/
lib/
Target/
AArch64/
1 line
test/
MC/
AArch64/
4 lines
4 lines
Disassembler/
AArch64/
4 lines

Diff 487833

llvm/lib/Target/AArch64/AArch64SystemOperands.td

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def : RWSysReg<"MAIR2_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b001>; def : RWSysReg<"MAIR2_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b001>;
def : RWSysReg<"MAIR2_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b001>; def : RWSysReg<"MAIR2_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b001>;
def : RWSysReg<"MAIR2_EL2", 0b11, 0b100, 0b1010, 0b0001, 0b001>; def : RWSysReg<"MAIR2_EL2", 0b11, 0b100, 0b1010, 0b0001, 0b001>;
def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>; def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>;
// v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE) // v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE)
// Op0 Op1 CRn CRm Op2 // Op0 Op1 CRn CRm Op2
def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>; def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>;
def : RWSysReg<"PIRE0_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b010>;
def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>; def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>;
def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>; def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>;
def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>; def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>;
def : RWSysReg<"PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b011>; def : RWSysReg<"PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b011>;
def : RWSysReg<"PIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b011>; def : RWSysReg<"PIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b011>;
// v8.9a/v9.4a Stage 2 Permission Indirection Extension (FEAT_S2PIE) // v8.9a/v9.4a Stage 2 Permission Indirection Extension (FEAT_S2PIE)
// Op0 Op1 CRn CRm Op2 // Op0 Op1 CRn CRm Op2
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llvm/test/MC/AArch64/arm64-system-encoding.s

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines;-----------------------------------------------------------------------------
msr AMAIR2_EL12, x3 msr AMAIR2_EL12, x3
msr AMAIR2_EL2, x3 msr AMAIR2_EL2, x3
msr AMAIR2_EL3, x3 msr AMAIR2_EL3, x3
msr MAIR2_EL1, x3 msr MAIR2_EL1, x3
msr MAIR2_EL12, x3 msr MAIR2_EL12, x3
msr MAIR2_EL2, x3 msr MAIR2_EL2, x3
msr MAIR2_EL3, x3 msr MAIR2_EL3, x3
msr PIRE0_EL1, x3 msr PIRE0_EL1, x3
msr PIRE0_EL12, x3
msr PIRE0_EL2, x3 msr PIRE0_EL2, x3
msr PIR_EL1, x3 msr PIR_EL1, x3
msr PIR_EL12, x3 msr PIR_EL12, x3
msr PIR_EL2, x3 msr PIR_EL2, x3
msr PIR_EL3, x3 msr PIR_EL3, x3
msr S2PIR_EL2, x3 msr S2PIR_EL2, x3
msr POR_EL0, x3 msr POR_EL0, x3
msr POR_EL1, x3 msr POR_EL1, x3
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; CHECK: msr AMAIR2_EL12, x3 ; encoding: [0x23,0xa3,0x1d,0xd5] ; CHECK: msr AMAIR2_EL12, x3 ; encoding: [0x23,0xa3,0x1d,0xd5]
; CHECK: msr AMAIR2_EL2, x3 ; encoding: [0x23,0xa3,0x1c,0xd5] ; CHECK: msr AMAIR2_EL2, x3 ; encoding: [0x23,0xa3,0x1c,0xd5]
; CHECK: msr AMAIR2_EL3, x3 ; encoding: [0x23,0xa3,0x1e,0xd5] ; CHECK: msr AMAIR2_EL3, x3 ; encoding: [0x23,0xa3,0x1e,0xd5]
; CHECK: msr MAIR2_EL1, x3 ; encoding: [0x23,0xa2,0x18,0xd5] ; CHECK: msr MAIR2_EL1, x3 ; encoding: [0x23,0xa2,0x18,0xd5]
; CHECK: msr MAIR2_EL12, x3 ; encoding: [0x23,0xa2,0x1d,0xd5] ; CHECK: msr MAIR2_EL12, x3 ; encoding: [0x23,0xa2,0x1d,0xd5]
; CHECK: msr MAIR2_EL2, x3 ; encoding: [0x23,0xa1,0x1c,0xd5] ; CHECK: msr MAIR2_EL2, x3 ; encoding: [0x23,0xa1,0x1c,0xd5]
; CHECK: msr MAIR2_EL3, x3 ; encoding: [0x23,0xa1,0x1e,0xd5] ; CHECK: msr MAIR2_EL3, x3 ; encoding: [0x23,0xa1,0x1e,0xd5]
; CHECK: msr PIRE0_EL1, x3 ; encoding: [0x43,0xa2,0x18,0xd5] ; CHECK: msr PIRE0_EL1, x3 ; encoding: [0x43,0xa2,0x18,0xd5]
; CHECK: msr PIRE0_EL12, x3 ; encoding: [0x43,0xa2,0x1d,0xd5]
; CHECK: msr PIRE0_EL2, x3 ; encoding: [0x43,0xa2,0x1c,0xd5] ; CHECK: msr PIRE0_EL2, x3 ; encoding: [0x43,0xa2,0x1c,0xd5]
; CHECK: msr PIR_EL1, x3 ; encoding: [0x63,0xa2,0x18,0xd5] ; CHECK: msr PIR_EL1, x3 ; encoding: [0x63,0xa2,0x18,0xd5]
; CHECK: msr PIR_EL12, x3 ; encoding: [0x63,0xa2,0x1d,0xd5] ; CHECK: msr PIR_EL12, x3 ; encoding: [0x63,0xa2,0x1d,0xd5]
; CHECK: msr PIR_EL2, x3 ; encoding: [0x63,0xa2,0x1c,0xd5] ; CHECK: msr PIR_EL2, x3 ; encoding: [0x63,0xa2,0x1c,0xd5]
; CHECK: msr PIR_EL3, x3 ; encoding: [0x63,0xa2,0x1e,0xd5] ; CHECK: msr PIR_EL3, x3 ; encoding: [0x63,0xa2,0x1e,0xd5]
; CHECK: msr S2PIR_EL2, x3 ; encoding: [0xa3,0xa2,0x1c,0xd5] ; CHECK: msr S2PIR_EL2, x3 ; encoding: [0xa3,0xa2,0x1c,0xd5]
; CHECK: msr POR_EL0, x3 ; encoding: [0x83,0xa2,0x1b,0xd5] ; CHECK: msr POR_EL0, x3 ; encoding: [0x83,0xa2,0x1b,0xd5]
; CHECK: msr POR_EL1, x3 ; encoding: [0x83,0xa2,0x18,0xd5] ; CHECK: msr POR_EL1, x3 ; encoding: [0x83,0xa2,0x18,0xd5]
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mrs x3, AMAIR2_EL12 mrs x3, AMAIR2_EL12
mrs x3, AMAIR2_EL2 mrs x3, AMAIR2_EL2
mrs x3, AMAIR2_EL3 mrs x3, AMAIR2_EL3
mrs x3, MAIR2_EL1 mrs x3, MAIR2_EL1
mrs x3, MAIR2_EL12 mrs x3, MAIR2_EL12
mrs x3, MAIR2_EL2 mrs x3, MAIR2_EL2
mrs x3, MAIR2_EL3 mrs x3, MAIR2_EL3
mrs x3, PIRE0_EL1 mrs x3, PIRE0_EL1
mrs x3, PIRE0_EL12
mrs x3, PIRE0_EL2 mrs x3, PIRE0_EL2
mrs x3, PIR_EL1 mrs x3, PIR_EL1
mrs x3, PIR_EL12 mrs x3, PIR_EL12
mrs x3, PIR_EL2 mrs x3, PIR_EL2
mrs x3, PIR_EL3 mrs x3, PIR_EL3
mrs x3, S2PIR_EL2 mrs x3, S2PIR_EL2
mrs x3, POR_EL0 mrs x3, POR_EL0
mrs x3, POR_EL1 mrs x3, POR_EL1
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; CHECK: mrs x3, AMAIR2_EL12 ; encoding: [0x23,0xa3,0x3d,0xd5] ; CHECK: mrs x3, AMAIR2_EL12 ; encoding: [0x23,0xa3,0x3d,0xd5]
; CHECK: mrs x3, AMAIR2_EL2 ; encoding: [0x23,0xa3,0x3c,0xd5] ; CHECK: mrs x3, AMAIR2_EL2 ; encoding: [0x23,0xa3,0x3c,0xd5]
; CHECK: mrs x3, AMAIR2_EL3 ; encoding: [0x23,0xa3,0x3e,0xd5] ; CHECK: mrs x3, AMAIR2_EL3 ; encoding: [0x23,0xa3,0x3e,0xd5]
; CHECK: mrs x3, MAIR2_EL1 ; encoding: [0x23,0xa2,0x38,0xd5] ; CHECK: mrs x3, MAIR2_EL1 ; encoding: [0x23,0xa2,0x38,0xd5]
; CHECK: mrs x3, MAIR2_EL12 ; encoding: [0x23,0xa2,0x3d,0xd5] ; CHECK: mrs x3, MAIR2_EL12 ; encoding: [0x23,0xa2,0x3d,0xd5]
; CHECK: mrs x3, MAIR2_EL2 ; encoding: [0x23,0xa1,0x3c,0xd5] ; CHECK: mrs x3, MAIR2_EL2 ; encoding: [0x23,0xa1,0x3c,0xd5]
; CHECK: mrs x3, MAIR2_EL3 ; encoding: [0x23,0xa1,0x3e,0xd5] ; CHECK: mrs x3, MAIR2_EL3 ; encoding: [0x23,0xa1,0x3e,0xd5]
; CHECK: mrs x3, PIRE0_EL1 ; encoding: [0x43,0xa2,0x38,0xd5] ; CHECK: mrs x3, PIRE0_EL1 ; encoding: [0x43,0xa2,0x38,0xd5]
; CHECK: mrs x3, PIRE0_EL12 ; encoding: [0x43,0xa2,0x3d,0xd5]
; CHECK: mrs x3, PIRE0_EL2 ; encoding: [0x43,0xa2,0x3c,0xd5] ; CHECK: mrs x3, PIRE0_EL2 ; encoding: [0x43,0xa2,0x3c,0xd5]
; CHECK: mrs x3, PIR_EL1 ; encoding: [0x63,0xa2,0x38,0xd5] ; CHECK: mrs x3, PIR_EL1 ; encoding: [0x63,0xa2,0x38,0xd5]
; CHECK: mrs x3, PIR_EL12 ; encoding: [0x63,0xa2,0x3d,0xd5] ; CHECK: mrs x3, PIR_EL12 ; encoding: [0x63,0xa2,0x3d,0xd5]
; CHECK: mrs x3, PIR_EL2 ; encoding: [0x63,0xa2,0x3c,0xd5] ; CHECK: mrs x3, PIR_EL2 ; encoding: [0x63,0xa2,0x3c,0xd5]
; CHECK: mrs x3, PIR_EL3 ; encoding: [0x63,0xa2,0x3e,0xd5] ; CHECK: mrs x3, PIR_EL3 ; encoding: [0x63,0xa2,0x3e,0xd5]
; CHECK: mrs x3, S2PIR_EL2 ; encoding: [0xa3,0xa2,0x3c,0xd5] ; CHECK: mrs x3, S2PIR_EL2 ; encoding: [0xa3,0xa2,0x3c,0xd5]
; CHECK: mrs x3, POR_EL0 ; encoding: [0x83,0xa2,0x3b,0xd5] ; CHECK: mrs x3, POR_EL0 ; encoding: [0x83,0xa2,0x3b,0xd5]
; CHECK: mrs x3, POR_EL1 ; encoding: [0x83,0xa2,0x38,0xd5] ; CHECK: mrs x3, POR_EL1 ; encoding: [0x83,0xa2,0x38,0xd5]
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llvm/test/MC/AArch64/basic-a64-instructions.s

Show First 20 Lines • Show All 3,942 Lines • ▼ Show 20 Lines msr PMEVTYPER30_EL0, x12
msr AMAIR2_EL12, x12 msr AMAIR2_EL12, x12
msr AMAIR2_EL2, x12 msr AMAIR2_EL2, x12
msr AMAIR2_EL3, x12 msr AMAIR2_EL3, x12
msr MAIR2_EL1, x12 msr MAIR2_EL1, x12
msr MAIR2_EL12, x12 msr MAIR2_EL12, x12
msr MAIR2_EL2, x12 msr MAIR2_EL2, x12
msr MAIR2_EL3, x12 msr MAIR2_EL3, x12
msr PIRE0_EL1, x12 msr PIRE0_EL1, x12
msr PIRE0_EL12, x12
msr PIRE0_EL2, x12 msr PIRE0_EL2, x12
msr PIR_EL1, x12 msr PIR_EL1, x12
msr PIR_EL12, x12 msr PIR_EL12, x12
msr PIR_EL2, x12 msr PIR_EL2, x12
msr PIR_EL3, x12 msr PIR_EL3, x12
msr S2PIR_EL2, x12 msr S2PIR_EL2, x12
msr POR_EL0, x12 msr POR_EL0, x12
msr POR_EL1, x12 msr POR_EL1, x12
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// CHECK: msr {{amair2_el12|AMAIR2_EL12}}, x12 // encoding: [0x2c,0xa3,0x1d,0xd5] // CHECK: msr {{amair2_el12|AMAIR2_EL12}}, x12 // encoding: [0x2c,0xa3,0x1d,0xd5]
// CHECK: msr {{amair2_el2|AMAIR2_EL2}}, x12 // encoding: [0x2c,0xa3,0x1c,0xd5] // CHECK: msr {{amair2_el2|AMAIR2_EL2}}, x12 // encoding: [0x2c,0xa3,0x1c,0xd5]
// CHECK: msr {{amair2_el3|AMAIR2_EL3}}, x12 // encoding: [0x2c,0xa3,0x1e,0xd5] // CHECK: msr {{amair2_el3|AMAIR2_EL3}}, x12 // encoding: [0x2c,0xa3,0x1e,0xd5]
// CHECK: msr {{mair2_el1|MAIR2_EL1}}, x12 // encoding: [0x2c,0xa2,0x18,0xd5] // CHECK: msr {{mair2_el1|MAIR2_EL1}}, x12 // encoding: [0x2c,0xa2,0x18,0xd5]
// CHECK: msr {{mair2_el12|MAIR2_EL12}}, x12 // encoding: [0x2c,0xa2,0x1d,0xd5] // CHECK: msr {{mair2_el12|MAIR2_EL12}}, x12 // encoding: [0x2c,0xa2,0x1d,0xd5]
// CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12 // encoding: [0x2c,0xa1,0x1c,0xd5] // CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12 // encoding: [0x2c,0xa1,0x1c,0xd5]
// CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12 // encoding: [0x2c,0xa1,0x1e,0xd5] // CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12 // encoding: [0x2c,0xa1,0x1e,0xd5]
// CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12 // encoding: [0x4c,0xa2,0x18,0xd5] // CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12 // encoding: [0x4c,0xa2,0x18,0xd5]
// CHECK: msr {{pire0_el12|PIRE0_EL12}}, x12 // encoding: [0x4c,0xa2,0x1d,0xd5]
// CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12 // encoding: [0x4c,0xa2,0x1c,0xd5] // CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12 // encoding: [0x4c,0xa2,0x1c,0xd5]
// CHECK: msr {{pir_el1|PIR_EL1}}, x12 // encoding: [0x6c,0xa2,0x18,0xd5] // CHECK: msr {{pir_el1|PIR_EL1}}, x12 // encoding: [0x6c,0xa2,0x18,0xd5]
// CHECK: msr {{pir_el12|PIR_EL12}}, x12 // encoding: [0x6c,0xa2,0x1d,0xd5] // CHECK: msr {{pir_el12|PIR_EL12}}, x12 // encoding: [0x6c,0xa2,0x1d,0xd5]
// CHECK: msr {{pir_el2|PIR_EL2}}, x12 // encoding: [0x6c,0xa2,0x1c,0xd5] // CHECK: msr {{pir_el2|PIR_EL2}}, x12 // encoding: [0x6c,0xa2,0x1c,0xd5]
// CHECK: msr {{pir_el3|PIR_EL3}}, x12 // encoding: [0x6c,0xa2,0x1e,0xd5] // CHECK: msr {{pir_el3|PIR_EL3}}, x12 // encoding: [0x6c,0xa2,0x1e,0xd5]
// CHECK: msr {{s2pir_el2|S2PIR_EL2}}, x12 // encoding: [0xac,0xa2,0x1c,0xd5] // CHECK: msr {{s2pir_el2|S2PIR_EL2}}, x12 // encoding: [0xac,0xa2,0x1c,0xd5]
// CHECK: msr {{por_el0|POR_EL0}}, x12 // encoding: [0x8c,0xa2,0x1b,0xd5] // CHECK: msr {{por_el0|POR_EL0}}, x12 // encoding: [0x8c,0xa2,0x1b,0xd5]
// CHECK: msr {{por_el1|POR_EL1}}, x12 // encoding: [0x8c,0xa2,0x18,0xd5] // CHECK: msr {{por_el1|POR_EL1}}, x12 // encoding: [0x8c,0xa2,0x18,0xd5]
▲ Show 20 Lines • Show All 321 Lines • ▼ Show 20 Lines mrs x9, PMEVTYPER30_EL0
mrs x9, AMAIR2_EL12 mrs x9, AMAIR2_EL12
mrs x9, AMAIR2_EL2 mrs x9, AMAIR2_EL2
mrs x9, AMAIR2_EL3 mrs x9, AMAIR2_EL3
mrs x9, MAIR2_EL1 mrs x9, MAIR2_EL1
mrs x9, MAIR2_EL12 mrs x9, MAIR2_EL12
mrs x9, MAIR2_EL2 mrs x9, MAIR2_EL2
mrs x9, MAIR2_EL3 mrs x9, MAIR2_EL3
mrs x9, PIRE0_EL1 mrs x9, PIRE0_EL1
mrs x9, PIRE0_EL12
mrs x9, PIRE0_EL2 mrs x9, PIRE0_EL2
mrs x9, PIR_EL1 mrs x9, PIR_EL1
mrs x9, PIR_EL12 mrs x9, PIR_EL12
mrs x9, PIR_EL2 mrs x9, PIR_EL2
mrs x9, PIR_EL3 mrs x9, PIR_EL3
mrs x9, S2PIR_EL2 mrs x9, S2PIR_EL2
mrs x9, POR_EL0 mrs x9, POR_EL0
mrs x9, POR_EL1 mrs x9, POR_EL1
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// CHECK: mrs x9, {{amair2_el12|AMAIR2_EL12}} // encoding: [0x29,0xa3,0x3d,0xd5] // CHECK: mrs x9, {{amair2_el12|AMAIR2_EL12}} // encoding: [0x29,0xa3,0x3d,0xd5]
// CHECK: mrs x9, {{amair2_el2|AMAIR2_EL2}} // encoding: [0x29,0xa3,0x3c,0xd5] // CHECK: mrs x9, {{amair2_el2|AMAIR2_EL2}} // encoding: [0x29,0xa3,0x3c,0xd5]
// CHECK: mrs x9, {{amair2_el3|AMAIR2_EL3}} // encoding: [0x29,0xa3,0x3e,0xd5] // CHECK: mrs x9, {{amair2_el3|AMAIR2_EL3}} // encoding: [0x29,0xa3,0x3e,0xd5]
// CHECK: mrs x9, {{mair2_el1|MAIR2_EL1}} // encoding: [0x29,0xa2,0x38,0xd5] // CHECK: mrs x9, {{mair2_el1|MAIR2_EL1}} // encoding: [0x29,0xa2,0x38,0xd5]
// CHECK: mrs x9, {{mair2_el12|MAIR2_EL12}} // encoding: [0x29,0xa2,0x3d,0xd5] // CHECK: mrs x9, {{mair2_el12|MAIR2_EL12}} // encoding: [0x29,0xa2,0x3d,0xd5]
// CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}} // encoding: [0x29,0xa1,0x3c,0xd5] // CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}} // encoding: [0x29,0xa1,0x3c,0xd5]
// CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}} // encoding: [0x29,0xa1,0x3e,0xd5] // CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}} // encoding: [0x29,0xa1,0x3e,0xd5]
// CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}} // encoding: [0x49,0xa2,0x38,0xd5] // CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}} // encoding: [0x49,0xa2,0x38,0xd5]
// CHECK: mrs x9, {{pire0_el12|PIRE0_EL12}} // encoding: [0x49,0xa2,0x3d,0xd5]
// CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}} // encoding: [0x49,0xa2,0x3c,0xd5] // CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}} // encoding: [0x49,0xa2,0x3c,0xd5]
// CHECK: mrs x9, {{pir_el1|PIR_EL1}} // encoding: [0x69,0xa2,0x38,0xd5] // CHECK: mrs x9, {{pir_el1|PIR_EL1}} // encoding: [0x69,0xa2,0x38,0xd5]
// CHECK: mrs x9, {{pir_el12|PIR_EL12}} // encoding: [0x69,0xa2,0x3d,0xd5] // CHECK: mrs x9, {{pir_el12|PIR_EL12}} // encoding: [0x69,0xa2,0x3d,0xd5]
// CHECK: mrs x9, {{pir_el2|PIR_EL2}} // encoding: [0x69,0xa2,0x3c,0xd5] // CHECK: mrs x9, {{pir_el2|PIR_EL2}} // encoding: [0x69,0xa2,0x3c,0xd5]
// CHECK: mrs x9, {{pir_el3|PIR_EL3}} // encoding: [0x69,0xa2,0x3e,0xd5] // CHECK: mrs x9, {{pir_el3|PIR_EL3}} // encoding: [0x69,0xa2,0x3e,0xd5]
// CHECK: mrs x9, {{s2pir_el2|S2PIR_EL2}} // encoding: [0xa9,0xa2,0x3c,0xd5] // CHECK: mrs x9, {{s2pir_el2|S2PIR_EL2}} // encoding: [0xa9,0xa2,0x3c,0xd5]
// CHECK: mrs x9, {{por_el0|POR_EL0}} // encoding: [0x89,0xa2,0x3b,0xd5] // CHECK: mrs x9, {{por_el0|POR_EL0}} // encoding: [0x89,0xa2,0x3b,0xd5]
// CHECK: mrs x9, {{por_el1|POR_EL1}} // encoding: [0x89,0xa2,0x38,0xd5] // CHECK: mrs x9, {{por_el1|POR_EL1}} // encoding: [0x89,0xa2,0x38,0xd5]
▲ Show 20 Lines • Show All 91 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

Show First 20 Lines • Show All 3,415 Lines • ▼ Show 20 Lines
# CHECK: msr {{amair2_el12|AMAIR2_EL12}}, x12 # CHECK: msr {{amair2_el12|AMAIR2_EL12}}, x12
# CHECK: msr {{amair2_el2|AMAIR2_EL2}}, x12 # CHECK: msr {{amair2_el2|AMAIR2_EL2}}, x12
# CHECK: msr {{amair2_el3|AMAIR2_EL3}}, x12 # CHECK: msr {{amair2_el3|AMAIR2_EL3}}, x12
# CHECK: msr {{mair2_el1|MAIR2_EL1}}, x12 # CHECK: msr {{mair2_el1|MAIR2_EL1}}, x12
# CHECK: msr {{mair2_el12|MAIR2_EL12}}, x12 # CHECK: msr {{mair2_el12|MAIR2_EL12}}, x12
# CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12 # CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12
# CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12 # CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12
# CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12 # CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12
# CHECK: msr {{pire0_el12|PIRE0_EL12}}, x12
# CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12 # CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12
# CHECK: msr {{pir_el1|PIR_EL1}}, x12 # CHECK: msr {{pir_el1|PIR_EL1}}, x12
# CHECK: msr {{pir_el12|PIR_EL12}}, x12 # CHECK: msr {{pir_el12|PIR_EL12}}, x12
# CHECK: msr {{pir_el2|PIR_EL2}}, x12 # CHECK: msr {{pir_el2|PIR_EL2}}, x12
# CHECK: msr {{pir_el3|PIR_EL3}}, x12 # CHECK: msr {{pir_el3|PIR_EL3}}, x12
# CHECK: msr {{s2pir_el2|S2PIR_EL2}}, x12 # CHECK: msr {{s2pir_el2|S2PIR_EL2}}, x12
# CHECK: msr {{por_el0|POR_EL0}}, x12 # CHECK: msr {{por_el0|POR_EL0}}, x12
# CHECK: msr {{por_el1|POR_EL1}}, x12 # CHECK: msr {{por_el1|POR_EL1}}, x12
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# CHECK: mrs x9, {{amair2_el12|AMAIR2_EL12}} # CHECK: mrs x9, {{amair2_el12|AMAIR2_EL12}}
# CHECK: mrs x9, {{amair2_el2|AMAIR2_EL2}} # CHECK: mrs x9, {{amair2_el2|AMAIR2_EL2}}
# CHECK: mrs x9, {{amair2_el3|AMAIR2_EL3}} # CHECK: mrs x9, {{amair2_el3|AMAIR2_EL3}}
# CHECK: mrs x9, {{mair2_el1|MAIR2_EL1}} # CHECK: mrs x9, {{mair2_el1|MAIR2_EL1}}
# CHECK: mrs x9, {{mair2_el12|MAIR2_EL12}} # CHECK: mrs x9, {{mair2_el12|MAIR2_EL12}}
# CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}} # CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}}
# CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}} # CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}}
# CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}} # CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}}
# CHECK: mrs x9, {{pire0_el12|PIRE0_EL12}}
# CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}} # CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}}
# CHECK: mrs x9, {{pir_el1|PIR_EL1}} # CHECK: mrs x9, {{pir_el1|PIR_EL1}}
# CHECK: mrs x9, {{pir_el12|PIR_EL12}} # CHECK: mrs x9, {{pir_el12|PIR_EL12}}
# CHECK: mrs x9, {{pir_el2|PIR_EL2}} # CHECK: mrs x9, {{pir_el2|PIR_EL2}}
# CHECK: mrs x9, {{pir_el3|PIR_EL3}} # CHECK: mrs x9, {{pir_el3|PIR_EL3}}
# CHECK: mrs x9, {{s2pir_el2|S2PIR_EL2}} # CHECK: mrs x9, {{s2pir_el2|S2PIR_EL2}}
# CHECK: mrs x9, {{por_el0|POR_EL0}} # CHECK: mrs x9, {{por_el0|POR_EL0}}
# CHECK: mrs x9, {{por_el1|POR_EL1}} # CHECK: mrs x9, {{por_el1|POR_EL1}}
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0x2c 0xa3 0x1d 0xd5 0x2c 0xa3 0x1d 0xd5
0x2c 0xa3 0x1c 0xd5 0x2c 0xa3 0x1c 0xd5
0x2c 0xa3 0x1e 0xd5 0x2c 0xa3 0x1e 0xd5
0x2c 0xa2 0x18 0xd5 0x2c 0xa2 0x18 0xd5
0x2c 0xa2 0x1d 0xd5 0x2c 0xa2 0x1d 0xd5
0x2c 0xa1 0x1c 0xd5 0x2c 0xa1 0x1c 0xd5
0x2c 0xa1 0x1e 0xd5 0x2c 0xa1 0x1e 0xd5
0x4c 0xa2 0x18 0xd5 0x4c 0xa2 0x18 0xd5
0x4c 0xa2 0x1d 0xd5
0x4c 0xa2 0x1c 0xd5 0x4c 0xa2 0x1c 0xd5
0x6c 0xa2 0x18 0xd5 0x6c 0xa2 0x18 0xd5
0x6c 0xa2 0x1d 0xd5 0x6c 0xa2 0x1d 0xd5
0x6c 0xa2 0x1c 0xd5 0x6c 0xa2 0x1c 0xd5
0x6c 0xa2 0x1e 0xd5 0x6c 0xa2 0x1e 0xd5
0xac 0xa2 0x1c 0xd5 0xac 0xa2 0x1c 0xd5
0x8c 0xa2 0x1b 0xd5 0x8c 0xa2 0x1b 0xd5
0x8c 0xa2 0x18 0xd5 0x8c 0xa2 0x18 0xd5
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0x29 0xa3 0x3d 0xd5 0x29 0xa3 0x3d 0xd5
0x29 0xa3 0x3c 0xd5 0x29 0xa3 0x3c 0xd5
0x29 0xa3 0x3e 0xd5 0x29 0xa3 0x3e 0xd5
0x29 0xa2 0x38 0xd5 0x29 0xa2 0x38 0xd5
0x29 0xa2 0x3d 0xd5 0x29 0xa2 0x3d 0xd5
0x29 0xa1 0x3c 0xd5 0x29 0xa1 0x3c 0xd5
0x29 0xa1 0x3e 0xd5 0x29 0xa1 0x3e 0xd5
0x49 0xa2 0x38 0xd5 0x49 0xa2 0x38 0xd5
0x49 0xa2 0x3d 0xd5
0x49 0xa2 0x3c 0xd5 0x49 0xa2 0x3c 0xd5
0x69 0xa2 0x38 0xd5 0x69 0xa2 0x38 0xd5
0x69 0xa2 0x3d 0xd5 0x69 0xa2 0x3d 0xd5
0x69 0xa2 0x3c 0xd5 0x69 0xa2 0x3c 0xd5
0x69 0xa2 0x3e 0xd5 0x69 0xa2 0x3e 0xd5
0xa9 0xa2 0x3c 0xd5 0xa9 0xa2 0x3c 0xd5
0x89 0xa2 0x3b 0xd5 0x89 0xa2 0x3b 0xd5
0x89 0xa2 0x38 0xd5 0x89 0xa2 0x38 0xd5
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines