MachineIRBuilder: Add buildMergeValues. NFC

[rovka]

Summary

Add a buildMergeValues method that unconditionally builds a
G_MERGE_VALUES instruction, as opposed to buildMergeLikeOp which may
decide on a different opcode based on the input types.

I haven't audited all the uses of buildMergeLikeOp to see if they can
be replaced with buildMergeValues, but I did find a couple of obvious
ones where we check that we're merging scalars right before calling
buildMerge.

This is a follow-up suggested in https://reviews.llvm.org/D140964

[foad]

LGTM, thanks!

llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

366

Call it BuildMergeValues?

[rovka]

llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

366

Of course, good catch :)

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

if (auto *SrcMerge = dyn_cast<GMerge>(SrcMI)) {
 
         const unsigned NumSrcs = DstSize / MergeSrcSize;
         assert(NumSrcs < SrcMI->getNumOperands() - 1 &&
                "trunc(merge) should require less inputs than merge");
         SmallVector<Register, 8> SrcRegs(NumSrcs);
         for (unsigned i = 0; i < NumSrcs; ++i)
           SrcRegs[i] = SrcMerge->getSourceReg(i);
 
-        Builder.buildMergeLikeOp(DstReg, SrcRegs);
+        Builder.buildMergeValues(DstReg, SrcRegs);
         UpdatedDefs.push_back(DstReg);
       } else {
         // Unable to combine
         return false;
       }
 
       markInstAndDefDead(MI, *SrcMerge, DeadInsts);
       return true;

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

public:
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
 
   /// Build and insert \p Res = IMPLICIT_DEF.
   MachineInstrBuilder buildUndef(const DstOp &Res);
 
   /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
+  ///
+  /// G_MERGE_VALUES combines the input elements contiguously into a larger
+  /// register. It should only be used when the destination register is not a
+  /// vector.
+  ///
+  /// \pre setBasicBlock or setMI must have been called.
+  /// \pre The entire register \p Res (and no more) must be covered by the input
+  ///      registers.
+  /// \pre The type of all \p Ops registers must be identical.
+  ///
+  /// \return a MachineInstrBuilder for the newly created instruction.
+  MachineInstrBuilder buildMergeValues(const DstOp &Res,
+                                       ArrayRef<Register> Ops);
+
+  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
   ///               or \p Res = G_BUILD_VECTOR \p Op0, ...
   ///               or \p Res = G_CONCAT_VECTORS \p Op0, ...
   ///
   /// G_MERGE_VALUES combines the input elements contiguously into a larger
   /// register. It is used when the destination register is not a vector.
   /// G_BUILD_VECTOR combines scalar inputs into a vector register.
   /// G_CONCAT_VECTORS combines vector inputs into a vector register.
   ///

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
   }
 
   if (!LLTy.isVector() && !PartLLT.isVector()) {
     assert(OrigRegs.size() == 1);
     LLT OrigTy = MRI.getType(OrigRegs[0]);
 
     unsigned SrcSize = PartLLT.getSizeInBits().getFixedSize() * Regs.size();
     if (SrcSize == OrigTy.getSizeInBits())
-      B.buildMergeLikeOp(OrigRegs[0], Regs);
+      B.buildMergeValues(OrigRegs[0], Regs);
     else {
       auto Widened = B.buildMergeLikeOp(LLT::scalar(SrcSize), Regs);
       B.buildTrunc(OrigRegs[0], Widened);
     }
 
     return;
   }
 

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

#endif
   Extract.addImm(Index);
   return Extract;
 }
 
 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
   return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
 }
 
+MachineInstrBuilder MachineIRBuilder::buildMergeValues(const DstOp &Res,
+                                                       ArrayRef<Register> Ops) {
+  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
+  // we need some temporary storage for the DstOp objects. Here we use a
+  // sufficiently large SmallVector to not go through the heap.
+  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
+  assert(TmpVec.size() > 1);
+  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
+}
+
 MachineInstrBuilder MachineIRBuilder::buildMergeLikeOp(const DstOp &Res,
                                                        ArrayRef<Register> Ops) {
   // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
   // we need some temporary storage for the DstOp objects. Here we use a
   // sufficiently large SmallVector to not go through the heap.
   SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
   assert(TmpVec.size() > 1);
   return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);

llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

TEST_F(AArch64GISelMITest, BuildMergeLikeOp) {
   ; CHECK: [[LOW2x32:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C0]]:_(s32), [[C1]]:_(s32)
   ; CHECK: [[HIGH2x32:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C2]]:_(s32), [[C3]]:_(s32)
   ; CHECK: {{%[0-9]+}}:_(<4 x s32>) = G_CONCAT_VECTORS [[LOW2x32]]:_(<2 x s32>), [[HIGH2x32]]:_(<2 x s32>)
   )";
 
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
+using MachineIRBuilderDeathTest = AArch64GISelMITest;
+
+TEST_F(MachineIRBuilderDeathTest, BuildMerge) {
+  setUp();
+  if (!TM)
+    return;
+
+  LLT S32 = LLT::scalar(32);
+  Register RegC0 = B.buildConstant(S32, 0).getReg(0);
+  Register RegC1 = B.buildConstant(S32, 1).getReg(0);
+  Register RegC2 = B.buildConstant(S32, 2).getReg(0);
+  Register RegC3 = B.buildConstant(S32, 3).getReg(0);
+
+  // Merging scalar constants should produce a G_MERGE_VALUES.
+  B.buildMergeValues(LLT::scalar(128), {RegC0, RegC1, RegC2, RegC3});
+
+  // Using a vector destination type should assert.
+  LLT V2x32 = LLT::fixed_vector(2, 32);
+  EXPECT_DEBUG_DEATH(
+      B.buildMergeValues(V2x32, {RegC0, RegC1}),
+      "vectors should be built with G_CONCAT_VECTOR or G_BUILD_VECTOR");
+
+  auto CheckStr = R"(
+  ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+  ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+  ; CHECK: {{%[0-9]+}}:_(s128) = G_MERGE_VALUES [[C0]]:_(s32), [[C1]]:_(s32), [[C2]]:_(s32), [[C3]]:_(s32)
+  )";
+
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
 TEST_F(AArch64GISelMITest, BuildAddoSubo) {
   setUp();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S64 = LLT::scalar(64);
   SmallVector<Register, 4> Copies;