Add an AArch64 DAG combine to eliminate unnecessary XTN operations when truncating v1i64 to v1i32.

[HsiangKai]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

17477

Put SDLoc(N) into the argument list.

[resistor]

Update for comment

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (VT.isFixedLengthVector() && VT.is64BitVector() && N0.hasOneUse() &&
       N0.getOpcode() == AArch64ISD::DUP) {
     SDValue Op = N0.getOperand(0);
     if (VT.getScalarType() == MVT::i32 &&
         N0.getOperand(0).getValueType().getScalarType() == MVT::i64)
       Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), MVT::i32, Op);
     return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Op);
   }
 
+  // (v2i32 trunc (v2i64 concat_vectors x, undef)) -> (bitcast x, v2i32)
+  if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.getValueType() == MVT::v2i64) {
+    bool AllButFirstUndef = true;
+    for (unsigned i = 1, e = N0.getNumOperands(); i < e; ++i) {
+      if (!N0.getOperand(i).isUndef()) {
+        AllButFirstUndef = false;
+        break;
+      }
+    }
+
+    if (AllButFirstUndef) {
+      return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0.getOperand(0));
+    }
+  }
+
   return SDValue();
 }
 
 // Check an node is an extend or shift operand
 static bool isExtendOrShiftOperand(SDValue N) {
   unsigned Opcode = N.getOpcode();
   if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_INREG ||
       Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND) {

llvm/test/CodeGen/AArch64/trunc-v1i64.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -verify-machineinstrs < %s | FileCheck %s
 
 ; An optimization in DAG Combiner to fold
 ; (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...))
 ; will generate nodes like:
 ;     v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
 ; And such nodes will be defaultly scalarized in type legalization. But such
 ; scalarization will cause an assertion failure, as v1i64 is a legal type in
 ; AArch64. We change the default behaviour from be scalarized to be widen.
 
-; FIXME: Currently XTN is generated for v1i32, but it can be optimized.
-; Just like v1i16 and v1i8, there is no XTN generated.
-
 define <2 x i32> @test_v1i32_0(<1 x i64> %in0) {
 ; CHECK-LABEL: test_v1i32_0:
-; CHECK: xtn v0.2s, v0.2d
+; CHECK-NOT: xtn
   %1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <2 x i32> <i32 0, i32 undef>
   %2 = trunc <2 x i64> %1 to <2 x i32>
   ret <2 x i32> %2
 }
 
 define <2 x i32> @test_v1i32_1(<1 x i64> %in0) {
 ; CHECK-LABEL: test_v1i32_1:
 ; CHECK-NOT: xtn