Add an AArch64 DAG combine to eliminate redundant truncates feeding into DUPLANE32 operations.

[resistor]

Fix testcase.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue performBSPExpandForSVE(SDNode *N, SelectionDAG &DAG,
   SDValue In2 = N->getOperand(2);
 
   SDValue InvMask = DAG.getNOT(DL, Mask, VT);
   SDValue Sel = DAG.getNode(ISD::AND, DL, VT, Mask, In1);
   SDValue SelInv = DAG.getNode(ISD::AND, DL, VT, InvMask, In2);
   return DAG.getNode(ISD::OR, DL, VT, Sel, SelInv);
 }
 
+static SDValue performDupLane32Combine(SDNode *N, SelectionDAG &DAG) {
+  SDValue Insert = N->getOperand(0);
+  if (Insert.getOpcode() != ISD::INSERT_SUBVECTOR) return SDValue();
+  if (!Insert.getOperand(0).isUndef()) return SDValue();
+
+  uint64_t IdxDupLane = N->getConstantOperandVal(1);
+  uint64_t IdxInsert = Insert.getConstantOperandVal(2);
+  if (IdxInsert != 0 || IdxDupLane != 0) return SDValue();
+
+  SDValue Truncate = Insert.getOperand(1);
+  if (Truncate.getOpcode() != ISD::TRUNCATE) return SDValue();
+
+  EVT InsertVT = Insert.getValueType();
+  EVT WideVT = Truncate.getOperand(0).getValueType();
+  if (InsertVT.getSizeInBits() != WideVT.getSizeInBits()) return SDValue();
+
+  SDLoc DL(N);
+  SDValue Bitcast =
+      DAG.getNode(ISD::BITCAST, DL, InsertVT, Truncate.getOperand(0));
+  return DAG.getNode(AArch64ISD::DUPLANE32, DL, N->getValueType(0), Bitcast,
+                     N->getOperand(1));
+}
+
 static SDValue performDupLane128Combine(SDNode *N, SelectionDAG &DAG) {
   EVT VT = N->getValueType(0);
 
   SDValue Insert = N->getOperand(0);
   if (Insert.getOpcode() != ISD::INSERT_SUBVECTOR)
     return SDValue();
 
   if (!Insert.getOperand(0).isUndef())
case AArch64ISD::BRCOND:
     return performBRCONDCombine(N, DCI, DAG);
   case AArch64ISD::TBNZ:
   case AArch64ISD::TBZ:
     return performTBZCombine(N, DCI, DAG);
   case AArch64ISD::CSEL:
     return performCSELCombine(N, DCI, DAG);
   case AArch64ISD::DUP:
     return performDUPCombine(N, DCI);
+  case AArch64ISD::DUPLANE32:
+    return performDupLane32Combine(N, DAG);
   case AArch64ISD::DUPLANE128:
     return performDupLane128Combine(N, DAG);
   case AArch64ISD::NVCAST:
     return performNVCASTCombine(N);
   case AArch64ISD::SPLICE:
     return performSpliceCombine(N, DAG);
   case AArch64ISD::UUNPKLO:
   case AArch64ISD::UUNPKHI:

llvm/test/CodeGen/AArch64/trunc-v1i64.ll

 ; CHECK: xtn v0.2s, v0.2d
   %1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <2 x i32> <i32 0, i32 undef>
   %2 = trunc <2 x i64> %1 to <2 x i32>
   ret <2 x i32> %2
 }
 
 define <2 x i32> @test_v1i32_1(<1 x i64> %in0) {
 ; CHECK-LABEL: test_v1i32_1:
-; CHECK: xtn v0.2s, v0.2d
-; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NOT: xtn
+; CHECK: dup v0.2s, v0.s[0]
   %1 = shufflevector <1 x i64> %in0, <1 x i64> undef, <2 x i32> <i32 undef, i32 0>
   %2 = trunc <2 x i64> %1 to <2 x i32>
   ret <2 x i32> %2
 }
 
 define <4 x i16> @test_v1i16_0(<1 x i64> %in0) {
 ; CHECK-LABEL: test_v1i16_0:
 ; CHECK-NOT: xtn