[LLDB][RISCV] Add RVDC instruction support for EmulateInstructionRISCV

[Emmmer]

Summary

RVC is the RISC-V standard compressed instruction-set extension, named "C", which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations, and RVCD is the compressed "D extension".

And "D extension" is a double-precision floating-point instruction-set extension, which adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard.

[DavidSpickett]

RVC is the RISC-V standard compressed instruction-set extension, named "C", which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations, and RVCD is the compressed "D extension".

...and the D extension is? So many names :)

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

321

What's the significance of FLDSP vs FLD? Is one implicitly using the stack pointer?

I guess what you're saying is both versions decode the same way which makes sense to me.

[Emmmer]

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

321

Yes, FLDSP uses the stack pointer to calculate the offset, C.FLD expands to fld rd, offset(rs1) and C.FSDSP expands to fsd rs2, offset(sp).

[DavidSpickett]

LGTM

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

static const InstrPattern PATTERNS[] = {
     {"C_SUB", 0xFC63, 0x8C01, DecodeC_SUB},
     {"C_SUBW", 0xFC63, 0x9C01, DecodeC_SUBW, RV64 | RV128},
     {"C_ADDW", 0xFC63, 0x9C21, DecodeC_ADDW, RV64 | RV128},
     // RV32FC //
     {"FLW", 0xE003, 0x6000, DecodeC_FLW, RV32},
     {"FSW", 0xE003, 0xE000, DecodeC_FSW, RV32},
     {"FLWSP", 0xE003, 0x6002, DecodeC_FLWSP, RV32},
     {"FSWSP", 0xE003, 0xE002, DecodeC_FSWSP, RV32},
+    // RVDC //
+    {"FLDSP", 0xE003, 0x2002, DecodeC_FLDSP, RV32 | RV64},
+    {"FSDSP", 0xE003, 0xA002, DecodeC_FSDSP, RV32 | RV64},
+    {"FLD", 0xE003, 0x2000, DecodeC_FLD, RV32 | RV64},
+    {"FSD", 0xE003, 0xA000, DecodeC_FSD, RV32 | RV64},
 
     // RV32F (Extension for Single-Precision Floating-Point) //
     {"FLW", 0x707F, 0x2007, DecodeIType<FLW>},
     {"FSW", 0x707F, 0x2027, DecodeSType<FSW>},
     {"FMADD_S", 0x600007F, 0x43, DecodeR4Type<FMADD_S>},
     {"FMSUB_S", 0x600007F, 0x47, DecodeR4Type<FMSUB_S>},
     {"FNMSUB_S", 0x600007F, 0x4B, DecodeR4Type<FNMSUB_S>},
     {"FNMADD_S", 0x600007F, 0x4F, DecodeR4Type<FNMADD_S>},

lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h

 }
 
 RISCVInst DecodeC_FSWSP(uint32_t inst) {
   uint16_t offset = ((inst >> 1) & 0xc0)    // offset[7:6]
                     | ((inst >> 7) & 0x3c); // offset[5:2]
   return FSW{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
 }
 
+RISCVInst DecodeC_FLDSP(uint32_t inst) {
+  auto rd = DecodeCI_RD(inst);
+  uint16_t offset = ((inst << 4) & 0x1c0)   // offset[8:6]
+                    | ((inst >> 7) & 0x20)  // offset[5]
+                    | ((inst >> 2) & 0x18); // offset[4:3]
+  return FLD{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
+}
+
+RISCVInst DecodeC_FSDSP(uint32_t inst) {
+  uint16_t offset = ((inst >> 1) & 0x1c0)   // offset[8:6]
+                    | ((inst >> 7) & 0x38); // offset[5:3]
+  return FSD{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
+}
+
+RISCVInst DecodeC_FLD(uint32_t inst) {
+  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
+                    | ((inst >> 7) & 0x38); // imm[5:3]
+  return FLD{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
+}
+
+RISCVInst DecodeC_FSD(uint32_t inst) {
+  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
+                    | ((inst >> 7) & 0x38); // imm[5:3]
+  return FSD{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
+}
+
 } // namespace lldb_private
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVCINSTRUCTION_H

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

 };
 
 TEST_F(RISCVEmulatorTester, TestCDecode) {
   std::vector<TestDecode> tests = {
       {0x0000, INVALID{0x0000}},
       {0x0010, RESERVED{0x0010}},
       // ADDI4SPN here, decode as ADDI
       {0x0024, ADDI{Rd{9}, Rs{2}, 8}},
+      {0x2084, FLD{Rd{9}, Rs{9}, 0}},
       {0x4488, LW{Rd{10}, Rs{9}, 8}},
       {0x6488, LD{Rd{10}, Rs{9}, 8}},
+      {0xA084, FSD{Rs{9}, Rs{9}, 0}},
       {0xC488, SW{Rs{9}, Rs{10}, 8}},
       {0xE488, SD{Rs{9}, Rs{10}, 8}},
       {0x1001, NOP{0x1001}},
       {0x1085, ADDI{Rd{1}, Rs{1}, uint32_t(-31)}},
       {0x2081, ADDIW{Rd{1}, Rs{1}, 0}},
       // ADDI16SP here, decode as ADDI
       {0x7101, ADDI{Rd{2}, Rs{2}, uint32_t(-512)}},
       {0x4081, ADDI{Rd{1}, Rs{0}, 0}},
std::vector<TestDecode> tests = {
       // C.J here, decoded as JAL
       {0xA001, JAL{Rd{0}, 0}},
       {0xC081, B{Rs{9}, Rs{0}, 0, 0b000}},
       {0xE081, B{Rs{9}, Rs{0}, 0, 0b001}},
       {0x1082, SLLI{Rd{1}, Rs{1}, 32}},
       {0x1002, HINT{0x1002}},
       // SLLI64 here, decoded as HINT if not in RV128
       {0x0082, HINT{0x0082}},
+      // FLDSP here, decoded as FLD
+      {0x2082, FLD{Rd{1}, Rs{2}, 0}},
       // LWSP here, decoded as LW
       {0x4082, LW{Rd{1}, Rs{2}, 0}},
       // LDSP here, decoded as LD
       {0x6082, LD{Rd{1}, Rs{2}, 0}},
       // C.JR here, decoded as JALR
       {0x8082, JALR{Rd{0}, Rs{1}, 0}},
       // C.MV here, decoded as ADD
       {0x8086, ADD{Rd{1}, Rs{0}, Rs{1}}},
       {0x9002, EBREAK{0x9002}},
       {0x9082, JALR{Rd{1}, Rs{1}, 0}},
       {0x9086, ADD{Rd{1}, Rs{1}, Rs{1}}},
+      // C.FSDSP here, decoded as FSD
+      {0xA006, FSD{Rs{2}, Rs{1}, 0}},
       // C.SWSP here, decoded as SW
       {0xC006, SW{Rs{2}, Rs{1}, 0}},
       // C.SDSP here, decoded as SD
       {0xE006, SD{Rs{2}, Rs{1}, 0}},
   };
 
   for (auto i : tests) {
     auto decode = this->Decode(i.inst);
     ASSERT_TRUE(decode.has_value());
     ASSERT_EQ(decode->decoded, i.inst_type);
   }
 }
 
 class RISCVEmulatorTester32 : public RISCVEmulatorTester {
 public:
   RISCVEmulatorTester32() : RISCVEmulatorTester("riscv32-unknown-linux-gnu") {}
 };
 
 TEST_F(RISCVEmulatorTester32, TestCDecodeRV32) {
   std::vector<TestDecode> tests = {
       {0x6002, FLW{Rd{0}, Rs{2}, 0}},
       {0xE006, FSW{Rs{2}, Rs{1}, 0}},
       {0x6000, FLW{Rd{8}, Rs{8}, 0}},
       {0xE000, FSW{Rs{8}, Rs{8}, 0}},
+
+      {0x2084, FLD{Rd{9}, Rs{9}, 0}},
+      {0xA084, FSD{Rs{9}, Rs{9}, 0}},
+      {0x2082, FLD{Rd{1}, Rs{2}, 0}},
+      {0xA006, FSD{Rs{2}, Rs{1}, 0}},
   };
 
   for (auto i : tests) {
     auto decode = this->Decode(i.inst);
     ASSERT_TRUE(decode.has_value());
     ASSERT_EQ(decode->decoded, i.inst_type);
   }
 }