[PowerPC][GISel]fcmp support

[shchenz]

Summary

This patch includes:
1: CRRegBank support
2: Some workarounds in PPC table gen for anyext/setcc patterns selection. (Will address this issue in utils/TableGen/GlobalISelEmitter.cpp later)

[shchenz]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3314

Some workarounds for GlobalISelEmitter to handle this anyext pattern. This looks like an issue in GlobalISelEmitter, otherwise there will be many same manual modifications.

3720

Some workarounds for GlobalISelEmitter to handle this setcc pattern

[arsenm]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3314

I think output patterns should really specify the class, not the type. The 1:1 mapping of type to class is one of the conceptual issues with the DAG and its patterns

3720

As above, I think output patterns should use classes

[shchenz]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3720

Ty can be f32/f64/f128, it may need another parameter for the low level register class. Let me just use MVT for now since I am working on addressing this issue in GlobalISelEmitter.cpp.

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

 #undef GET_GLOBALISEL_TEMPORARIES_INIT
 {
 }
 
 static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
   if (RB->getID() == PPC::GPRRegBankID) {
     if (Ty.getSizeInBits() == 64)
       return &PPC::G8RCRegClass;
-    if (Ty.getSizeInBits() == 32)
+    if (Ty.getSizeInBits() <= 32)
       return &PPC::GPRCRegClass;
   }
   if (RB->getID() == PPC::FPRRegBankID) {
     if (Ty.getSizeInBits() == 32)
       return &PPC::F4RCRegClass;
     if (Ty.getSizeInBits() == 64)
       return &PPC::F8RCRegClass;
   }
+  if (RB->getID() == PPC::CRRegBankID) {
+    if (Ty.getSizeInBits() == 1)
+      return &PPC::CRBITRCRegClass;
+    if (Ty.getSizeInBits() == 4)
+      return &PPC::CRRCRegClass;
+  }
 
   llvm_unreachable("Unknown RegBank!");
 }
 
 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
                        MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
                        const RegisterBankInfo &RBI) {
   Register DstReg = I.getOperand(0).getReg();

llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp

 #define DEBUG_TYPE "ppc-legalinfo"
 
 using namespace llvm;
 using namespace LegalizeActions;
 
 PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
   using namespace TargetOpcode;
   const LLT P0 = LLT::pointer(0, 64);
+  const LLT S1 = LLT::scalar(1);
   const LLT S8 = LLT::scalar(8);
   const LLT S16 = LLT::scalar(16);
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({S64});
   getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({S32, S64})
       .clampScalar(0, S64, S64);
-  getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
-      .legalForCartesianProduct({S64}, {S8, S16, S32})
+  getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
+      .legalForCartesianProduct({S64}, {S1, S8, S16, S32})
       .clampScalar(0, S64, S64);
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
   getActionDefinitionsBuilder({G_ADD, G_SUB})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
 
   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
       .legalFor({S32, S64});
 
+  getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({S1},
+                                                               {S32, S64});
+
   getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
       .legalForCartesianProduct({S64}, {S32, S64});
 
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
       .legalForCartesianProduct({S32, S64}, {S64});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
       .legalForTypesWithMemDesc({{S64, P0, S64, 8}, {S32, P0, S32, 4}});
 
   getActionDefinitionsBuilder(G_FCONSTANT).lowerFor({S32, S64});
   getActionDefinitionsBuilder(G_CONSTANT_POOL).legalFor({P0});
 
   getLegacyLegalizerInfo().computeTables();
 }

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h

 class PPCGenRegisterBankInfo : public RegisterBankInfo {
 protected:
   enum PartialMappingIdx {
     PMI_None = -1,
     PMI_GPR32 = 1,
     PMI_GPR64 = 2,
     PMI_FPR32 = 3,
     PMI_FPR64 = 4,
+    PMI_CR = 5,
     PMI_Min = PMI_GPR32,
   };
 
   static RegisterBankInfo::PartialMapping PartMappings[];
   static RegisterBankInfo::ValueMapping ValMappings[];
   static PartialMappingIdx BankIDToCopyMapIdx[];
 
   /// Get the pointer to the ValueMapping representing the RegisterBank

llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
   case PPC::SPILLTOVSRRC_and_VSFRCRegClassID:
   case PPC::SPILLTOVSRRC_and_VFRCRegClassID:
   case PPC::SPILLTOVSRRC_and_F4RCRegClassID:
   case PPC::F8RCRegClassID:
   case PPC::VFRCRegClassID:
   case PPC::VSSRCRegClassID:
   case PPC::F4RCRegClassID:
     return getRegBank(PPC::FPRRegBankID);
+  case PPC::CRRCRegClassID:
+  case PPC::CRBITRCRegClassID:
+    return getRegBank(PPC::CRRegBankID);
   default:
     llvm_unreachable("Unexpected register class");
   }
 }
 
 const RegisterBankInfo::InstructionMapping &
 PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   const unsigned Opc = MI.getOpcode();
PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_SUB:
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:
   case TargetOpcode::G_XOR:
     // Extension ops.
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
+  case TargetOpcode::G_ANYEXT:
     assert(NumOperands <= 3 &&
            "This code is for instructions with 3 or less operands");
     OperandsMapping = getValueMapping(PMI_GPR64);
     break;
   case TargetOpcode::G_FADD:
   case TargetOpcode::G_FSUB:
   case TargetOpcode::G_FMUL:
   case TargetOpcode::G_FDIV: {
     Register SrcReg = MI.getOperand(1).getReg();
     unsigned Size = getSizeInBits(SrcReg, MRI, TRI);
 
     assert((Size == 32 || Size == 64) && "Unsupported floating point types!\n");
     OperandsMapping = getValueMapping(Size == 32 ? PMI_FPR32 : PMI_FPR64);
     break;
   }
+  case TargetOpcode::G_FCMP: {
+    unsigned CmpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
+
+    OperandsMapping = getOperandsMapping(
+        {getValueMapping(PMI_CR), nullptr,
+         getValueMapping(CmpSize == 32 ? PMI_FPR32 : PMI_FPR64),
+         getValueMapping(CmpSize == 32 ? PMI_FPR32 : PMI_FPR64)});
+    break;
+  }
   case TargetOpcode::G_CONSTANT:
     OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
     break;
   case TargetOpcode::G_CONSTANT_POOL:
     OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
     break;
   case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_FPTOSI: {

llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td

 /// Define the PPC register banks used for GlobalISel.
 ///
 //===----------------------------------------------------------------------===//
 
 /// General Purpose Registers
 def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
 /// Floating point Registers
 def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
+/// Condition Registers
+def CRRegBank : RegisterBank<"CR", [CRRC]>;

llvm/lib/Target/PowerPC/PPCGenRegisterBankInfo.def

RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
     // 0: GPR 32-bit value.
     {0, 32, PPC::GPRRegBank},
     // 1: GPR 64-bit value.
     {0, 64, PPC::GPRRegBank},
     // 2: FPR 32-bit value
     {0, 32, PPC::FPRRegBank},
     // 3: FPR 64-bit value
     {0, 64, PPC::FPRRegBank},
+    // 4: CR 4-bit value
+    {0, 4, PPC::CRRegBank},
 };
 
 // ValueMappings.
 // Pointers to the entries in this array are returned by getValueMapping() and
 // getCopyMapping().
 //
 // The array has the following structure:
 // - At index 0 is the invalid entry.
RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
     // 7: FPR 32-bit value.
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     // 10: FPR 64-bit value.
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+    // 13: CR 4-bit value.
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_CR - PMI_Min], 1},
 };
 
 // TODO Too simple!
 const RegisterBankInfo::ValueMapping *
 PPCGenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx) {
   assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
 
   unsigned ValMappingIdx = RBIdx - PMI_Min;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def : Pat<(i64 (zext i1:$in)),
           (SELECT_I8 $in, (LI8 1), (LI8 0))>;
 def : Pat<(i64 (sext i1:$in)),
           (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
 
 // FIXME: We should choose either a zext or a sext based on other constants
 // already around.
 def : Pat<(i32 (anyext i1:$in)),
-          (SELECT_I4 $in, (LI 1), (LI 0))>;
+          (SELECT_I4 i1:$in, (LI 1), (LI 0))>;
 def : Pat<(i64 (anyext i1:$in)),
-          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
+          (SELECT_I8 i1:$in, (LI8 1), (LI8 0))>;
 
 // match setcc on i1 variables.
 // CRANDC is:
 //   1 1 : F
 //   1 0 : T
 //   0 1 : F
 //   0 0 : F
 //

 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
                 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
                 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
 }
 
 multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> {
   defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
-                  (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
+                  (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_lt)>;
   defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
-                  (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
+                  (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_lt)>;
   defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
-                  (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
+                  (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_gt)>;
   defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
-                  (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
+                  (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_gt)>;
   defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
-                  (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
+                  (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_eq)>;
   defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
-                  (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
+                  (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_eq)>;
   defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
-                  (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
+                  (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_un)>;
 
   def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
-            (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
+            (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_lt)>;
   def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
-            (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
+            (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_lt)>;
   def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)),
-            (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
+            (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_gt)>;
   def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)),
-            (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
+            (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_gt)>;
   def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)),
-            (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
+            (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_eq)>;
   def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)),
-            (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
+            (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_eq)>;
   def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)),
-            (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
+            (EXTRACT_SUBREG (FCmp Ty:$s1, Ty:$s2), sub_un)>;
 }
 
 let Predicates = [HasFPU] in {
 // FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set.
 // SETCC for f32.
 defm : FSetCCPat<any_fsetcc, f32, FCMPUS>;
 
 // SETCC for f64.

llvm/test/CodeGen/PowerPC/GlobalISel/fcmp.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+
+;; Note that SETUEQ, SETOGE, SETOLE, SETONE, SETULT and SETUGT should be
+;; expanded by legalize for floating-point types f32 and f64, so there are no.
+;; patterns defined in PPCInstrInfo.td file for these setcc patterns.
+
+define i1 @fcmp_false(float %a, float %b) {
+; CHECK-LABEL: fcmp_false:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+  %cmp = fcmp false float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_oeq(float %a, float %b) {
+; CHECK-LABEL: fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    iseleq r3, r4, r3
+; CHECK-NEXT:    blr
+  %cmp = fcmp oeq float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_ogt(float %a, float %b) {
+; CHECK-LABEL: fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    iselgt r3, r4, r3
+; CHECK-NEXT:    blr
+  %cmp = fcmp ogt float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_olt(float %a, float %b) {
+; CHECK-LABEL: fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    isellt r3, r4, r3
+; CHECK-NEXT:    blr
+  %cmp = fcmp olt float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_ord(float %a, float %b) {
+; CHECK-LABEL: fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    crnot 4*cr5+lt, un
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+  %cmp = fcmp ord float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_uge(float %a, float %b) {
+; CHECK-LABEL: fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    crnot 4*cr5+lt, lt
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+  %cmp = fcmp uge float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_ule(float %a, float %b) {
+; CHECK-LABEL: fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    crnot 4*cr5+lt, gt
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+  %cmp = fcmp ule float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_une(float %a, float %b) {
+; CHECK-LABEL: fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    crnot 4*cr5+lt, eq
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+  %cmp = fcmp une float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_uno(float %a, float %b) {
+; CHECK-LABEL: fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    isel r3, r4, r3, un
+; CHECK-NEXT:    blr
+  %cmp = fcmp uno float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_true(float %a, float %b) {
+; CHECK-LABEL: fcmp_true:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
+  %cmp = fcmp true float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_false_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_false_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+  %cmp = fcmp false double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_oeq_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_oeq_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    iseleq r3, r4, r3
+; CHECK-NEXT:    blr
+  %cmp = fcmp oeq double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_ogt_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_ogt_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    iselgt r3, r4, r3
+; CHECK-NEXT:    blr
+  %cmp = fcmp ogt double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_olt_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_olt_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    isellt r3, r4, r3
+; CHECK-NEXT:    blr
+  %cmp = fcmp olt double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_ord_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_ord_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    crnot 4*cr5+lt, un
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+  %cmp = fcmp ord double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_uge_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_uge_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    crnot 4*cr5+lt, lt
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+  %cmp = fcmp uge double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_ule_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_ule_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    crnot 4*cr5+lt, gt
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+  %cmp = fcmp ule double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_une_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_une_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    crnot 4*cr5+lt, eq
+; CHECK-NEXT:    isel r3, r4, r3, 4*cr5+lt
+; CHECK-NEXT:    blr
+  %cmp = fcmp une double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_uno_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_uno_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcmpu cr0, f1, f2
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    isel r3, r4, r3, un
+; CHECK-NEXT:    blr
+  %cmp = fcmp uno double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @fcmp_true_double(double %a, double %b) {
+; CHECK-LABEL: fcmp_true_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
+  %cmp = fcmp true double %a, %b
+  ret i1 %cmp
+}