[NFC][LLDB] Using namespace llvm in EmulateInstructionRISCV

[Emmmer]

Summary

The EmulateInstructionRISCV uses a lot of types and functions in llvm and lldb, this change is to make the code look cleaner.

PS: This patch should be merged before D140032.

[Emmmer]

Updating D140092: [NFC] Using namespace llvm in EmulateInstructionRISCV

[DavidSpickett]

LGTM

[DavidSpickett]

Please tag [LLDB] in the commit title.

[Emmmer]

rebase main

[labath]

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h

21–22

You cannot use using namespace in a header file. That pollutes the lldb_private namespace for everyone who includes this file. Please revert this immediately.

[Emmmer]

@labath Fixed in rGd850b340a9dd91fdb3c4dddc8328524c721576be

[labath]

In D140092#3998835, @Emmmer wrote:

@labath Fixed in rGd850b340a9dd91fdb3c4dddc8328524c721576be

Thanks!

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h

 
 #include "lldb/Core/EmulateInstruction.h"
 #include "lldb/Interpreter/OptionValue.h"
 #include "lldb/Utility/Log.h"
 #include "lldb/Utility/RegisterValue.h"
 #include "lldb/Utility/Status.h"
 
 namespace lldb_private {
+using namespace llvm;
+using namespace lldb;
 
 class EmulateInstructionRISCV : public EmulateInstruction {
 public:
-  static llvm::StringRef GetPluginNameStatic() { return "riscv"; }
+  static StringRef GetPluginNameStatic() { return "riscv"; }
 
-  static llvm::StringRef GetPluginDescriptionStatic() {
+  static StringRef GetPluginDescriptionStatic() {
     return "Emulate instructions for the RISC-V architecture.";
   }
 
   static bool SupportsThisInstructionType(InstructionType inst_type) {
     switch (inst_type) {
     case eInstructionTypeAny:
     case eInstructionTypePCModifying:
       return true;
public:
 
   static void Initialize();
 
   static void Terminate();
 
 public:
   EmulateInstructionRISCV(const ArchSpec &arch) : EmulateInstruction(arch) {}
 
-  llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
+  StringRef GetPluginName() override { return GetPluginNameStatic(); }
 
   bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override {
     return SupportsThisInstructionType(inst_type);
   }
 
   bool SetTargetTriple(const ArchSpec &arch) override;
   bool ReadInstruction() override;
   bool EvaluateInstruction(uint32_t options) override;
   bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                      OptionValueDictionary *test_data) override;
-  llvm::Optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
-                                               uint32_t reg_num) override;
+  Optional<RegisterInfo> GetRegisterInfo(RegisterKind reg_kind,
 
-  llvm::Optional<lldb::addr_t> ReadPC();
-  bool WritePC(lldb::addr_t pc);
+  Optional<addr_t> ReadPC();
+  bool WritePC(addr_t pc);
 
-  llvm::Optional<DecodeResult> ReadInstructionAt(lldb::addr_t addr);
-  llvm::Optional<DecodeResult> Decode(uint32_t inst);
+  Optional<DecodeResult> ReadInstructionAt(addr_t addr);
+  Optional<DecodeResult> Decode(uint32_t inst);
   bool Execute(DecodeResult inst, bool ignore_cond);
 
   template <typename T>
-  std::enable_if_t<std::is_integral_v<T>, llvm::Optional<T>>
-  ReadMem(uint64_t addr) {
+  std::enable_if_t<std::is_integral_v<T>, Optional<T>> ReadMem(uint64_t addr) {
     EmulateInstructionRISCV::Context ctx;
     ctx.type = EmulateInstruction::eContextRegisterLoad;
     ctx.SetNoArgs();
     bool success = false;
     T result = ReadMemoryUnsigned(ctx, addr, sizeof(T), T(), &success);
     if (!success)
       return {}; // aka return false
     return result;
   }
 
   template <typename T> bool WriteMem(uint64_t addr, uint64_t value) {
     EmulateInstructionRISCV::Context ctx;
     ctx.type = EmulateInstruction::eContextRegisterStore;
     ctx.SetNoArgs();
     return WriteMemoryUnsigned(ctx, addr, value, sizeof(T));
   }
 
-  llvm::RoundingMode GetRoundingMode();
-  bool SetAccruedExceptions(llvm::APFloatBase::opStatus);
+  RoundingMode GetRoundingMode();
+  bool SetAccruedExceptions(APFloatBase::opStatus);
 
 private:
   /// Last decoded instruction from m_opcode
   DecodeResult m_decoded;
 };
 
 } // namespace lldb_private
 
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

 #include "lldb/Symbol/UnwindPlan.h"
 #include "lldb/Utility/ArchSpec.h"
 #include "lldb/Utility/LLDBLog.h"
 #include "lldb/Utility/Stream.h"
 
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/MathExtras.h"
 
+using namespace llvm;
 using namespace lldb;
 using namespace lldb_private;
 
 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionRISCV, InstructionRISCV)
 
 namespace lldb_private {
 
 /// Returns all values wrapped in Optional, or std::nullopt if any of the values
 /// is std::nullopt.
 template <typename... Ts>
-static llvm::Optional<std::tuple<Ts...>> zipOpt(llvm::Optional<Ts> &&...ts) {
+static Optional<std::tuple<Ts...>> zipOpt(Optional<Ts> &&...ts) {
   if ((ts.has_value() && ...))
-    return llvm::Optional<std::tuple<Ts...>>(
-        std::make_tuple(std::move(*ts)...));
+    return Optional<std::tuple<Ts...>>(std::make_tuple(std::move(*ts)...));
   else
     return std::nullopt;
 }
 
 // The funct3 is the type of compare in B<CMP> instructions.
 // funct3 means "3-bits function selector", which RISC-V ISA uses as minor
 // opcode. It reuses the major opcode encoding space.
 constexpr uint32_t BEQ = 0b000;
bool Rd::Write(EmulateInstructionRISCV &emulator, uint64_t value) {
   ctx.type = EmulateInstruction::eContextRegisterStore;
   ctx.SetNoArgs();
   RegisterValue registerValue;
   registerValue.SetUInt64(value);
   return emulator.WriteRegister(ctx, eRegisterKindLLDB, lldb_reg,
                                 registerValue);
 }
 
-bool Rd::WriteAPFloat(EmulateInstructionRISCV &emulator, llvm::APFloat value) {
+bool Rd::WriteAPFloat(EmulateInstructionRISCV &emulator, APFloat value) {
   uint32_t lldb_reg = FPREncodingToLLDB(rd);
   EmulateInstruction::Context ctx;
   ctx.type = EmulateInstruction::eContextRegisterStore;
   ctx.SetNoArgs();
   RegisterValue registerValue;
   registerValue.SetUInt64(value.bitcastToAPInt().getZExtValue());
   return emulator.WriteRegister(ctx, eRegisterKindLLDB, lldb_reg,
                                 registerValue);
 }
 
-llvm::Optional<uint64_t> Rs::Read(EmulateInstructionRISCV &emulator) {
+Optional<uint64_t> Rs::Read(EmulateInstructionRISCV &emulator) {
   uint32_t lldbReg = GPREncodingToLLDB(rs);
   RegisterValue value;
   return emulator.ReadRegister(eRegisterKindLLDB, lldbReg, value)
-             ? llvm::Optional<uint64_t>(value.GetAsUInt64())
+             ? Optional<uint64_t>(value.GetAsUInt64())
              : std::nullopt;
 }
 
-llvm::Optional<int32_t> Rs::ReadI32(EmulateInstructionRISCV &emulator) {
-  return llvm::transformOptional(
+Optional<int32_t> Rs::ReadI32(EmulateInstructionRISCV &emulator) {
+  return transformOptional(
       Read(emulator), [](uint64_t value) { return int32_t(uint32_t(value)); });
 }
 
-llvm::Optional<int64_t> Rs::ReadI64(EmulateInstructionRISCV &emulator) {
-  return llvm::transformOptional(Read(emulator),
-                                 [](uint64_t value) { return int64_t(value); });
+Optional<int64_t> Rs::ReadI64(EmulateInstructionRISCV &emulator) {
+  return transformOptional(Read(emulator),
 }
 
-llvm::Optional<uint32_t> Rs::ReadU32(EmulateInstructionRISCV &emulator) {
-  return llvm::transformOptional(
-      Read(emulator), [](uint64_t value) { return uint32_t(value); });
+Optional<uint32_t> Rs::ReadU32(EmulateInstructionRISCV &emulator) {
+  return transformOptional(Read(emulator),
+                           [](uint64_t value) { return uint32_t(value); });
 }
 
-llvm::Optional<llvm::APFloat> Rs::ReadAPFloat(EmulateInstructionRISCV &emulator,
-                                              bool isDouble) {
+Optional<APFloat> Rs::ReadAPFloat(EmulateInstructionRISCV &emulator,
   uint32_t lldbReg = FPREncodingToLLDB(rs);
   RegisterValue value;
   if (!emulator.ReadRegister(eRegisterKindLLDB, lldbReg, value))
     return std::nullopt;
   uint64_t bits = value.GetAsUInt64();
-  llvm::APInt api(64, bits, false);
-  return llvm::APFloat(isDouble ? llvm::APFloat(api.bitsToDouble())
-                                : llvm::APFloat(api.bitsToFloat()));
+  APInt api(64, bits, false);
+  return APFloat(isDouble ? APFloat(api.bitsToDouble())
+                          : APFloat(api.bitsToFloat()));
 }
 
 static bool CompareB(uint64_t rs1, uint64_t rs2, uint32_t funct3) {
   switch (funct3) {
   case BEQ:
     return rs1 == rs2;
   case BNE:
     return rs1 != rs2;

 template <typename T>
 constexpr bool is_amo_cmp =
     std::is_same_v<T, AMOMIN_W> || std::is_same_v<T, AMOMIN_D> ||
     std::is_same_v<T, AMOMAX_W> || std::is_same_v<T, AMOMAX_D> ||
     std::is_same_v<T, AMOMINU_W> || std::is_same_v<T, AMOMINU_D> ||
     std::is_same_v<T, AMOMAXU_W> || std::is_same_v<T, AMOMAXU_D>;
 
 template <typename I>
-static std::enable_if_t<is_load<I> || is_store<I>, llvm::Optional<uint64_t>>
+static std::enable_if_t<is_load<I> || is_store<I>, Optional<uint64_t>>
 LoadStoreAddr(EmulateInstructionRISCV &emulator, I inst) {
-  return llvm::transformOptional(inst.rs1.Read(emulator), [&](uint64_t rs1) {
+  return transformOptional(inst.rs1.Read(emulator), [&](uint64_t rs1) {
     return rs1 + uint64_t(SignExt(inst.imm));
   });
 }
 
 // Read T from memory, then load its sign-extended value m_emu to register.
 template <typename I, typename T, typename E>
 static std::enable_if_t<is_load<I>, bool>
 Load(EmulateInstructionRISCV &emulator, I inst, uint64_t (*extend)(E)) {
   auto addr = LoadStoreAddr(emulator, inst);
   if (!addr)
     return false;
-  return llvm::transformOptional(
+  return transformOptional(
              emulator.ReadMem<T>(*addr),
              [&](T t) { return inst.rd.Write(emulator, extend(E(t))); })
       .value_or(false);
 }
 
 template <typename I, typename T>
 static std::enable_if_t<is_store<I>, bool>
 Store(EmulateInstructionRISCV &emulator, I inst) {
   auto addr = LoadStoreAddr(emulator, inst);
   if (!addr)
     return false;
-  return llvm::transformOptional(
+  return transformOptional(
              inst.rs2.Read(emulator),
              [&](uint64_t rs2) { return emulator.WriteMem<T>(*addr, rs2); })
       .value_or(false);
 }
 
 template <typename I>
 static std::enable_if_t<is_amo_add<I> || is_amo_bit_op<I> || is_amo_swap<I> ||
                             is_amo_cmp<I>,
-                        llvm::Optional<uint64_t>>
+                        Optional<uint64_t>>
 AtomicAddr(EmulateInstructionRISCV &emulator, I inst, unsigned int align) {
-  return llvm::transformOptional(inst.rs1.Read(emulator),
-                                 [&](uint64_t rs1) {
-                                   return rs1 % align == 0
-                                              ? llvm::Optional<uint64_t>(rs1)
+  return transformOptional(inst.rs1.Read(emulator),
+                             return rs1 % align == 0 ? Optional<uint64_t>(rs1)
                                                      : std::nullopt;
-                                 })
       .value_or(std::nullopt);
 }
 
 template <typename I, typename T>
 static std::enable_if_t<is_amo_swap<I>, bool>
 AtomicSwap(EmulateInstructionRISCV &emulator, I inst, int align,
            uint64_t (*extend)(T)) {
   auto addr = AtomicAddr(emulator, inst, align);
   if (!addr)
     return false;
-  return llvm::transformOptional(
+  return transformOptional(
              zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)),
              [&](auto &&tup) {
                auto [tmp, rs2] = tup;
                return emulator.WriteMem<T>(*addr, T(rs2)) &&
                       inst.rd.Write(emulator, extend(tmp));
              })
       .value_or(false);
 }
 
 template <typename I, typename T>
 static std::enable_if_t<is_amo_add<I>, bool>
 AtomicADD(EmulateInstructionRISCV &emulator, I inst, int align,
           uint64_t (*extend)(T)) {
   auto addr = AtomicAddr(emulator, inst, align);
   if (!addr)
     return false;
-  return llvm::transformOptional(
+  return transformOptional(
              zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)),
              [&](auto &&tup) {
                auto [tmp, rs2] = tup;
                return emulator.WriteMem<T>(*addr, T(tmp + rs2)) &&
                       inst.rd.Write(emulator, extend(tmp));
              })
       .value_or(false);
 }
 
 template <typename I, typename T>
 static std::enable_if_t<is_amo_bit_op<I>, bool>
 AtomicBitOperate(EmulateInstructionRISCV &emulator, I inst, int align,
                  uint64_t (*extend)(T), T (*operate)(T, T)) {
   auto addr = AtomicAddr(emulator, inst, align);
   if (!addr)
     return false;
-  return llvm::transformOptional(
+  return transformOptional(
              zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)),
              [&](auto &&tup) {
                auto [value, rs2] = tup;
                return emulator.WriteMem<T>(*addr, operate(value, T(rs2))) &&
                       inst.rd.Write(emulator, extend(value));
              })
       .value_or(false);
 }
 
 template <typename I, typename T>
 static std::enable_if_t<is_amo_cmp<I>, bool>
 AtomicCmp(EmulateInstructionRISCV &emulator, I inst, int align,
           uint64_t (*extend)(T), T (*cmp)(T, T)) {
   auto addr = AtomicAddr(emulator, inst, align);
   if (!addr)
     return false;
-  return llvm::transformOptional(
+  return transformOptional(
              zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)),
              [&](auto &&tup) {
                auto [value, rs2] = tup;
                return emulator.WriteMem<T>(*addr, cmp(value, T(rs2))) &&
                       inst.rd.Write(emulator, extend(value));
              })
       .value_or(false);
 }
static const InstrPattern PATTERNS[] = {
 
     // RV64F (Extension for Single-Precision Floating-Point) //
     {"FCVT_L_S", 0xFFF0007F, 0xC0200053, DecodeIType<FCVT_L_S>},
     {"FCVT_LU_S", 0xFFF0007F, 0xC0300053, DecodeIType<FCVT_LU_S>},
     {"FCVT_S_L", 0xFFF0007F, 0xD0200053, DecodeIType<FCVT_S_L>},
     {"FCVT_S_LU", 0xFFF0007F, 0xD0300053, DecodeIType<FCVT_S_LU>},
 };
 
-llvm::Optional<DecodeResult> EmulateInstructionRISCV::Decode(uint32_t inst) {
+Optional<DecodeResult> EmulateInstructionRISCV::Decode(uint32_t inst) {
   Log *log = GetLog(LLDBLog::Unwind);
 
   uint16_t try_rvc = uint16_t(inst & 0x0000ffff);
   // check whether the compressed encode could be valid
   uint16_t mask = try_rvc & 0b11;
   bool is_rvc = try_rvc != 0 && mask != 3;
   uint8_t inst_type = RV64;
 
private:
   uint64_t delta() { return size(m_is_rvc); }
 
 public:
   Executor(EmulateInstructionRISCV &emulator, bool ignoreCond, bool is_rvc)
       : m_emu(emulator), m_ignore_cond(ignoreCond), m_is_rvc(is_rvc) {}
 
   bool operator()(LUI inst) { return inst.rd.Write(m_emu, SignExt(inst.imm)); }
   bool operator()(AUIPC inst) {
-    return llvm::transformOptional(m_emu.ReadPC(),
-                                   [&](uint64_t pc) {
-                                     return inst.rd.Write(
-                                         m_emu, SignExt(inst.imm) + pc);
-                                   })
+    return transformOptional(m_emu.ReadPC(),
+                               return inst.rd.Write(m_emu,
+                                                    SignExt(inst.imm) + pc);
         .value_or(false);
   }
   bool operator()(JAL inst) {
-    return llvm::transformOptional(
-               m_emu.ReadPC(),
+    return transformOptional(m_emu.ReadPC(),
                              [&](uint64_t pc) {
                                return inst.rd.Write(m_emu, pc + delta()) &&
                                       m_emu.WritePC(SignExt(inst.imm) + pc);
                              })
         .value_or(false);
   }
   bool operator()(JALR inst) {
-    return llvm::transformOptional(
-               zipOpt(m_emu.ReadPC(), inst.rs1.Read(m_emu)),
+    return transformOptional(zipOpt(m_emu.ReadPC(), inst.rs1.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [pc, rs1] = tup;
                                return inst.rd.Write(m_emu, pc + delta()) &&
-                        m_emu.WritePC((SignExt(inst.imm) + rs1) & ~1);
+                                      m_emu.WritePC((SignExt(inst.imm) + rs1) &
+                                                    ~1);
                              })
         .value_or(false);
   }
   bool operator()(B inst) {
-    return llvm::transformOptional(
-               zipOpt(m_emu.ReadPC(), inst.rs1.Read(m_emu),
+    return transformOptional(zipOpt(m_emu.ReadPC(), inst.rs1.Read(m_emu),
                                     inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [pc, rs1, rs2] = tup;
-                 if (m_ignore_cond || CompareB(rs1, rs2, inst.funct3))
+                               if (m_ignore_cond ||
+                                   CompareB(rs1, rs2, inst.funct3))
                                  return m_emu.WritePC(SignExt(inst.imm) + pc);
                                return true;
                              })
         .value_or(false);
   }
   bool operator()(LB inst) {
     return Load<LB, uint8_t, int8_t>(m_emu, inst, SextW);
   }
   bool operator()(LH inst) {
     return Load<LH, uint16_t, int16_t>(m_emu, inst, SextW);
   }
   bool operator()(LW inst) {
     return Load<LW, uint32_t, int32_t>(m_emu, inst, SextW);
   }
   bool operator()(LBU inst) {
     return Load<LBU, uint8_t, uint8_t>(m_emu, inst, ZextD);
   }
   bool operator()(LHU inst) {
     return Load<LHU, uint16_t, uint16_t>(m_emu, inst, ZextD);
   }
   bool operator()(SB inst) { return Store<SB, uint8_t>(m_emu, inst); }
   bool operator()(SH inst) { return Store<SH, uint16_t>(m_emu, inst); }
   bool operator()(SW inst) { return Store<SW, uint32_t>(m_emu, inst); }
   bool operator()(ADDI inst) {
-    return llvm::transformOptional(
-               inst.rs1.ReadI64(m_emu),
+    return transformOptional(inst.rs1.ReadI64(m_emu),
                              [&](int64_t rs1) {
-                 return inst.rd.Write(m_emu, rs1 + int64_t(SignExt(inst.imm)));
+                               return inst.rd.Write(
+                                   m_emu, rs1 + int64_t(SignExt(inst.imm)));
                              })
         .value_or(false);
   }
   bool operator()(SLTI inst) {
-    return llvm::transformOptional(
-               inst.rs1.ReadI64(m_emu),
+    return transformOptional(inst.rs1.ReadI64(m_emu),
                              [&](int64_t rs1) {
-                 return inst.rd.Write(m_emu, rs1 < int64_t(SignExt(inst.imm)));
+                               return inst.rd.Write(
+                                   m_emu, rs1 < int64_t(SignExt(inst.imm)));
                              })
         .value_or(false);
   }
   bool operator()(SLTIU inst) {
-    return llvm::transformOptional(
-               inst.rs1.Read(m_emu),
+    return transformOptional(inst.rs1.Read(m_emu),
                              [&](uint64_t rs1) {
-                 return inst.rd.Write(m_emu, rs1 < uint64_t(SignExt(inst.imm)));
+                               return inst.rd.Write(
+                                   m_emu, rs1 < uint64_t(SignExt(inst.imm)));
                              })
         .value_or(false);
   }
   bool operator()(XORI inst) {
-    return llvm::transformOptional(
-               inst.rs1.Read(m_emu),
+    return transformOptional(inst.rs1.Read(m_emu),
                              [&](uint64_t rs1) {
-                 return inst.rd.Write(m_emu, rs1 ^ uint64_t(SignExt(inst.imm)));
+                               return inst.rd.Write(
+                                   m_emu, rs1 ^ uint64_t(SignExt(inst.imm)));
                              })
         .value_or(false);
   }
   bool operator()(ORI inst) {
-    return llvm::transformOptional(
-               inst.rs1.Read(m_emu),
+    return transformOptional(inst.rs1.Read(m_emu),
                              [&](uint64_t rs1) {
-                 return inst.rd.Write(m_emu, rs1 | uint64_t(SignExt(inst.imm)));
+                               return inst.rd.Write(
+                                   m_emu, rs1 | uint64_t(SignExt(inst.imm)));
                              })
         .value_or(false);
   }
   bool operator()(ANDI inst) {
-    return llvm::transformOptional(
-               inst.rs1.Read(m_emu),
+    return transformOptional(inst.rs1.Read(m_emu),
                              [&](uint64_t rs1) {
-                 return inst.rd.Write(m_emu, rs1 & uint64_t(SignExt(inst.imm)));
+                               return inst.rd.Write(
+                                   m_emu, rs1 & uint64_t(SignExt(inst.imm)));
                              })
         .value_or(false);
   }
   bool operator()(ADD inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
                                return inst.rd.Write(m_emu, rs1 + rs2);
                              })
         .value_or(false);
   }
   bool operator()(SUB inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
                                return inst.rd.Write(m_emu, rs1 - rs2);
                              })
         .value_or(false);
   }
   bool operator()(SLL inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
-                 return inst.rd.Write(m_emu, rs1 << (rs2 & 0b111111));
+                               return inst.rd.Write(m_emu,
+                                                    rs1 << (rs2 & 0b111111));
                              })
         .value_or(false);
   }
   bool operator()(SLT inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadI64(m_emu), inst.rs2.ReadI64(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  return inst.rd.Write(m_emu, rs1 < rs2);
                })
         .value_or(false);
   }
   bool operator()(SLTU inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
                                return inst.rd.Write(m_emu, rs1 < rs2);
                              })
         .value_or(false);
   }
   bool operator()(XOR inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
                                return inst.rd.Write(m_emu, rs1 ^ rs2);
                              })
         .value_or(false);
   }
   bool operator()(SRL inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
-                 return inst.rd.Write(m_emu, rs1 >> (rs2 & 0b111111));
+                               return inst.rd.Write(m_emu,
+                                                    rs1 >> (rs2 & 0b111111));
                              })
         .value_or(false);
   }
   bool operator()(SRA inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadI64(m_emu), inst.rs2.Read(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  return inst.rd.Write(m_emu, rs1 >> (rs2 & 0b111111));
                })
         .value_or(false);
   }
   bool operator()(OR inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
                                return inst.rd.Write(m_emu, rs1 | rs2);
                              })
         .value_or(false);
   }
   bool operator()(AND inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
                                return inst.rd.Write(m_emu, rs1 & rs2);
                              })
         .value_or(false);
   }
   bool operator()(LWU inst) {
     return Load<LWU, uint32_t, uint32_t>(m_emu, inst, ZextD);
   }
   bool operator()(LD inst) {
     return Load<LD, uint64_t, uint64_t>(m_emu, inst, ZextD);
   }
   bool operator()(SD inst) { return Store<SD, uint64_t>(m_emu, inst); }
   bool operator()(SLLI inst) {
-    return llvm::transformOptional(inst.rs1.Read(m_emu),
-                                   [&](uint64_t rs1) {
-                                     return inst.rd.Write(m_emu,
-                                                          rs1 << inst.shamt);
-                                   })
+    return transformOptional(inst.rs1.Read(m_emu),
+                               return inst.rd.Write(m_emu, rs1 << inst.shamt);
         .value_or(false);
   }
   bool operator()(SRLI inst) {
-    return llvm::transformOptional(inst.rs1.Read(m_emu),
-                                   [&](uint64_t rs1) {
-                                     return inst.rd.Write(m_emu,
-                                                          rs1 >> inst.shamt);
-                                   })
+    return transformOptional(inst.rs1.Read(m_emu),
+                               return inst.rd.Write(m_emu, rs1 >> inst.shamt);
         .value_or(false);
   }
   bool operator()(SRAI inst) {
-    return llvm::transformOptional(inst.rs1.ReadI64(m_emu),
-                                   [&](int64_t rs1) {
-                                     return inst.rd.Write(m_emu,
-                                                          rs1 >> inst.shamt);
-                                   })
+    return transformOptional(inst.rs1.ReadI64(m_emu),
+                               return inst.rd.Write(m_emu, rs1 >> inst.shamt);
         .value_or(false);
   }
   bool operator()(ADDIW inst) {
-    return llvm::transformOptional(inst.rs1.ReadI32(m_emu),
-                                   [&](int32_t rs1) {
-                                     return inst.rd.Write(
-                                         m_emu, SextW(rs1 + SignExt(inst.imm)));
-                                   })
+    return transformOptional(inst.rs1.ReadI32(m_emu),
         .value_or(false);
   }
   bool operator()(SLLIW inst) {
-    return llvm::transformOptional(inst.rs1.ReadU32(m_emu),
-                                   [&](uint32_t rs1) {
-                                     return inst.rd.Write(
-                                         m_emu, SextW(rs1 << inst.shamt));
-                                   })
+    return transformOptional(inst.rs1.ReadU32(m_emu),
+                               return inst.rd.Write(m_emu,
+                                                    SextW(rs1 << inst.shamt));
         .value_or(false);
   }
   bool operator()(SRLIW inst) {
-    return llvm::transformOptional(inst.rs1.ReadU32(m_emu),
-                                   [&](uint32_t rs1) {
-                                     return inst.rd.Write(
-                                         m_emu, SextW(rs1 >> inst.shamt));
-                                   })
+    return transformOptional(inst.rs1.ReadU32(m_emu),
+                               return inst.rd.Write(m_emu,
+                                                    SextW(rs1 >> inst.shamt));
         .value_or(false);
   }
   bool operator()(SRAIW inst) {
-    return llvm::transformOptional(inst.rs1.ReadI32(m_emu),
-                                   [&](int32_t rs1) {
-                                     return inst.rd.Write(
-                                         m_emu, SextW(rs1 >> inst.shamt));
-                                   })
+    return transformOptional(inst.rs1.ReadI32(m_emu),
+                               return inst.rd.Write(m_emu,
+                                                    SextW(rs1 >> inst.shamt));
         .value_or(false);
   }
   bool operator()(ADDW inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
-                 return inst.rd.Write(m_emu, SextW(uint32_t(rs1 + rs2)));
+                               return inst.rd.Write(m_emu,
+                                                    SextW(uint32_t(rs1 + rs2)));
                              })
         .value_or(false);
   }
   bool operator()(SUBW inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
-                 return inst.rd.Write(m_emu, SextW(uint32_t(rs1 - rs2)));
+                               return inst.rd.Write(m_emu,
+                                                    SextW(uint32_t(rs1 - rs2)));
                              })
         .value_or(false);
   }
   bool operator()(SLLW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadU32(m_emu), inst.rs2.ReadU32(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  return inst.rd.Write(m_emu, SextW(rs1 << (rs2 & 0b11111)));
                })
         .value_or(false);
   }
   bool operator()(SRLW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadU32(m_emu), inst.rs2.ReadU32(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  return inst.rd.Write(m_emu, SextW(rs1 >> (rs2 & 0b11111)));
                })
         .value_or(false);
   }
   bool operator()(SRAW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadI32(m_emu), inst.rs2.Read(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  return inst.rd.Write(m_emu, SextW(rs1 >> (rs2 & 0b11111)));
                })
         .value_or(false);
   }
   // RV32M & RV64M (Integer Multiplication and Division Extension) //
   bool operator()(MUL inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [rs1, rs2] = tup;
                                return inst.rd.Write(m_emu, rs1 * rs2);
                              })
         .value_or(false);
   }
   bool operator()(MULH inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  // signed * signed
-                 auto mul =
-                     llvm::APInt(128, rs1, true) * llvm::APInt(128, rs2, true);
+                 auto mul = APInt(128, rs1, true) * APInt(128, rs2, true);
                  return inst.rd.Write(m_emu,
                                       mul.ashr(64).trunc(64).getZExtValue());
                })
         .value_or(false);
   }
   bool operator()(MULHSU inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  // signed * unsigned
-                 auto mul = llvm::APInt(128, rs1, true).zext(128) *
-                            llvm::APInt(128, rs2, false);
+                 auto mul =
+                     APInt(128, rs1, true).zext(128) * APInt(128, rs2, false);
                  return inst.rd.Write(m_emu,
                                       mul.lshr(64).trunc(64).getZExtValue());
                })
         .value_or(false);
   }
   bool operator()(MULHU inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  // unsigned * unsigned
-                 auto mul = llvm::APInt(128, rs1, false) *
-                            llvm::APInt(128, rs2, false);
+                 auto mul = APInt(128, rs1, false) * APInt(128, rs2, false);
                  return inst.rd.Write(m_emu,
                                       mul.lshr(64).trunc(64).getZExtValue());
                })
         .value_or(false);
   }
   bool operator()(DIV inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadI64(m_emu), inst.rs2.ReadI64(m_emu)),
                [&](auto &&tup) {
                  auto [dividend, divisor] = tup;
 
                  if (divisor == 0)
                    return inst.rd.Write(m_emu, UINT64_MAX);
 
                  if (dividend == INT64_MIN && divisor == -1)
                    return inst.rd.Write(m_emu, dividend);
 
                  return inst.rd.Write(m_emu, dividend / divisor);
                })
         .value_or(false);
   }
   bool operator()(DIVU inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [dividend, divisor] = tup;
 
                                if (divisor == 0)
                                  return inst.rd.Write(m_emu, UINT64_MAX);
 
                                return inst.rd.Write(m_emu, dividend / divisor);
                              })
         .value_or(false);
   }
   bool operator()(REM inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadI64(m_emu), inst.rs2.ReadI64(m_emu)),
                [&](auto &&tup) {
                  auto [dividend, divisor] = tup;
 
                  if (divisor == 0)
                    return inst.rd.Write(m_emu, dividend);
 
                  if (dividend == INT64_MIN && divisor == -1)
                    return inst.rd.Write(m_emu, 0);
 
                  return inst.rd.Write(m_emu, dividend % divisor);
                })
         .value_or(false);
   }
   bool operator()(REMU inst) {
-    return llvm::transformOptional(
-               zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
+    return transformOptional(zipOpt(inst.rs1.Read(m_emu), inst.rs2.Read(m_emu)),
                              [&](auto &&tup) {
                                auto [dividend, divisor] = tup;
 
                                if (divisor == 0)
                                  return inst.rd.Write(m_emu, dividend);
 
                                return inst.rd.Write(m_emu, dividend % divisor);
                              })
         .value_or(false);
   }
   bool operator()(MULW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadI32(m_emu), inst.rs2.ReadI32(m_emu)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  return inst.rd.Write(m_emu, SextW(rs1 * rs2));
                })
         .value_or(false);
   }
   bool operator()(DIVW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadI32(m_emu), inst.rs2.ReadI32(m_emu)),
                [&](auto &&tup) {
                  auto [dividend, divisor] = tup;
 
                  if (divisor == 0)
                    return inst.rd.Write(m_emu, UINT64_MAX);
 
                  if (dividend == INT32_MIN && divisor == -1)
                    return inst.rd.Write(m_emu, SextW(dividend));
 
                  return inst.rd.Write(m_emu, SextW(dividend / divisor));
                })
         .value_or(false);
   }
   bool operator()(DIVUW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadU32(m_emu), inst.rs2.ReadU32(m_emu)),
                [&](auto &&tup) {
                  auto [dividend, divisor] = tup;
 
                  if (divisor == 0)
                    return inst.rd.Write(m_emu, UINT64_MAX);
 
                  return inst.rd.Write(m_emu, SextW(dividend / divisor));
                })
         .value_or(false);
   }
   bool operator()(REMW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadI32(m_emu), inst.rs2.ReadI32(m_emu)),
                [&](auto &&tup) {
                  auto [dividend, divisor] = tup;
 
                  if (divisor == 0)
                    return inst.rd.Write(m_emu, SextW(dividend));
 
                  if (dividend == INT32_MIN && divisor == -1)
                    return inst.rd.Write(m_emu, 0);
 
                  return inst.rd.Write(m_emu, SextW(dividend % divisor));
                })
         .value_or(false);
   }
   bool operator()(REMUW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadU32(m_emu), inst.rs2.ReadU32(m_emu)),
                [&](auto &&tup) {
                  auto [dividend, divisor] = tup;
 
                  if (divisor == 0)
                    return inst.rd.Write(m_emu, SextW(dividend));
 
                  return inst.rd.Write(m_emu, SextW(dividend % divisor));
return AtomicCmp<AMOMINU_D, uint64_t>(
         [](uint64_t a, uint64_t b) { return std::min(a, b); });
   }
   bool operator()(AMOMAXU_D inst) {
     return AtomicCmp<AMOMAXU_D, uint64_t>(
         m_emu, inst, 8, ZextD,
         [](uint64_t a, uint64_t b) { return std::max(a, b); });
   }
   bool operator()(FLW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                inst.rs1.Read(m_emu),
                [&](auto &&rs1) {
                  uint64_t addr = rs1 + uint64_t(inst.imm);
                  uint64_t bits = m_emu.ReadMem<uint64_t>(addr).value();
-                 llvm::APFloat f(llvm::APFloat::IEEEsingle(),
-                                 llvm::APInt(32, bits));
+                 APFloat f(APFloat::IEEEsingle(), APInt(32, bits));
                  return inst.rd.WriteAPFloat(m_emu, f);
                })
         .value_or(false);
   }
   bool operator()(FSW inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.Read(m_emu), inst.rs2.ReadAPFloat(m_emu, false)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  uint64_t addr = rs1 + uint64_t(inst.imm);
                  uint64_t bits = rs2.bitcastToAPInt().getZExtValue();
                  return m_emu.WriteMem<uint64_t>(addr, bits);
                })
         .value_or(false);
   }
   bool operator()(FMADD_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false),
-                                          inst.rs3.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2, rs3] = tup;
-                                     auto res = rs1.fusedMultiplyAdd(
-                                         rs2, rs3, m_emu.GetRoundingMode());
-                                     inst.rd.WriteAPFloat(m_emu, rs1);
-                                     return m_emu.SetAccruedExceptions(res);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FMSUB_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false),
-                                          inst.rs3.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2, rs3] = tup;
-                                     auto res = rs1.fusedMultiplyAdd(
-                                         rs2, -rs3, m_emu.GetRoundingMode());
-                                     inst.rd.WriteAPFloat(m_emu, rs1);
-                                     return m_emu.SetAccruedExceptions(res);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FNMSUB_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false),
-                                          inst.rs3.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2, rs3] = tup;
-                                     auto res = rs1.fusedMultiplyAdd(
-                                         -rs2, rs3, m_emu.GetRoundingMode());
-                                     inst.rd.WriteAPFloat(m_emu, rs1);
-                                     return m_emu.SetAccruedExceptions(res);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FNMADD_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false),
-                                          inst.rs3.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2, rs3] = tup;
-                                     auto res = rs1.fusedMultiplyAdd(
-                                         -rs2, -rs3, m_emu.GetRoundingMode());
-                                     inst.rd.WriteAPFloat(m_emu, rs1);
-                                     return m_emu.SetAccruedExceptions(res);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FADD_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2] = tup;
-                                     auto res =
-                                         rs1.add(rs2, m_emu.GetRoundingMode());
-                                     inst.rd.WriteAPFloat(m_emu, rs1);
-                                     return m_emu.SetAccruedExceptions(res);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
+                               auto res = rs1.add(rs2, m_emu.GetRoundingMode());
         .value_or(false);
   }
   bool operator()(FSUB_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2] = tup;
-                                     auto res = rs1.subtract(
-                                         rs2, m_emu.GetRoundingMode());
-                                     inst.rd.WriteAPFloat(m_emu, rs1);
-                                     return m_emu.SetAccruedExceptions(res);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
+                               auto res =
+                                   rs1.subtract(rs2, m_emu.GetRoundingMode());
         .value_or(false);
   }
   bool operator()(FMUL_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2] = tup;
-                                     auto res = rs1.multiply(
-                                         rs2, m_emu.GetRoundingMode());
-                                     inst.rd.WriteAPFloat(m_emu, rs1);
-                                     return m_emu.SetAccruedExceptions(res);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
+                               auto res =
+                                   rs1.multiply(rs2, m_emu.GetRoundingMode());
         .value_or(false);
   }
   bool operator()(FDIV_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2] = tup;
-                                     auto res = rs1.divide(
-                                         rs2, m_emu.GetRoundingMode());
-                                     inst.rd.WriteAPFloat(m_emu, rs1);
-                                     return m_emu.SetAccruedExceptions(res);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
+                               auto res =
+                                   rs1.divide(rs2, m_emu.GetRoundingMode());
         .value_or(false);
   }
   bool operator()(FSQRT_S inst) {
     // TODO: APFloat doesn't have a sqrt function.
     return false;
   }
   bool operator()(FSGNJ_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2] = tup;
-                                     rs1.copySign(rs2);
-                                     return inst.rd.WriteAPFloat(m_emu, rs1);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FSGNJN_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2] = tup;
-                                     rs1.copySign(-rs2);
-                                     return inst.rd.WriteAPFloat(m_emu, rs1);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FSGNJX_S inst) {
-    return llvm::transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
-                                          inst.rs2.ReadAPFloat(m_emu, false)),
-                                   [&](auto &&tup) {
-                                     auto [rs1, rs2] = tup;
-                                     // spec: the sign bit is the XOR of the
-                                     // sign bits of rs1 and rs2. if rs1 and rs2
-                                     // have the same signs set rs1 to positive
-                                     // else set rs1 to negative
-                                     if (rs1.isNegative() == rs2.isNegative()) {
-                                       rs1.clearSign();
-                                     } else {
-                                       rs1.clearSign();
-                                       rs1.changeSign();
-                                     }
-                                     return inst.rd.WriteAPFloat(m_emu, rs1);
-                                   })
+    return transformOptional(zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FMIN_S inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
                       inst.rs2.ReadAPFloat(m_emu, false)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  // If both inputs are NaNs, the result is the canonical NaN.
                  // If only one operand is a NaN, the result is the non-NaN
                  // operand. Signaling NaN inputs set the invalid operation
                  // exception flag, even when the result is not NaN.
                  if (rs1.isNaN() || rs2.isNaN())
-                   m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+                   m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
                  if (rs1.isNaN() && rs2.isNaN()) {
-                   auto canonicalNaN =
-                       llvm::APFloat::getQNaN(rs1.getSemantics());
+                   auto canonicalNaN = APFloat::getQNaN(rs1.getSemantics());
                    return inst.rd.WriteAPFloat(m_emu, canonicalNaN);
                  }
                  return inst.rd.WriteAPFloat(m_emu, minnum(rs1, rs2));
                })
         .value_or(false);
   }
   bool operator()(FMAX_S inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
                       inst.rs2.ReadAPFloat(m_emu, false)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  if (rs1.isNaN() || rs2.isNaN())
-                   m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+                   m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
                  if (rs1.isNaN() && rs2.isNaN()) {
-                   auto canonicalNaN =
-                       llvm::APFloat::getQNaN(rs1.getSemantics());
+                   auto canonicalNaN = APFloat::getQNaN(rs1.getSemantics());
                    return inst.rd.WriteAPFloat(m_emu, canonicalNaN);
                  }
                  return inst.rd.WriteAPFloat(m_emu, maxnum(rs1, rs2));
                })
         .value_or(false);
   }
   bool operator()(FCVT_W_S inst) {
-    return llvm::transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
-                                   [&](auto &&rs1) {
-                                     int32_t res = rs1.convertToFloat();
-                                     return inst.rd.Write(m_emu, uint64_t(res));
-                                   })
+    return transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FCVT_WU_S inst) {
-    return llvm::transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
-                                   [&](auto &&rs1) {
-                                     uint32_t res = rs1.convertToFloat();
-                                     return inst.rd.Write(m_emu, uint64_t(res));
-                                   })
+    return transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FMV_X_W inst) {
-    return llvm::transformOptional(
-               inst.rs1.ReadAPFloat(m_emu, false),
+    return transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
                              [&](auto &&rs1) {
                                if (rs1.isNaN())
                                  return inst.rd.Write(m_emu, 0x7fc00000);
                                auto bits = rs1.bitcastToAPInt();
-                 return inst.rd.Write(m_emu,
-                                      NanBoxing(uint64_t(bits.getSExtValue())));
+                               return inst.rd.Write(
+                                   m_emu,
                              })
         .value_or(false);
   }
   bool operator()(FEQ_S inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
                       inst.rs2.ReadAPFloat(m_emu, false)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  if (rs1.isNaN() || rs2.isNaN()) {
                    if (rs1.isSignaling() || rs2.isSignaling())
-                     m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+                     m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
                    return inst.rd.Write(m_emu, 0);
                  }
-                 return inst.rd.Write(m_emu, rs1.compare(rs2) ==
-                                                 llvm::APFloat::cmpEqual);
+                 return inst.rd.Write(m_emu,
+                                      rs1.compare(rs2) == APFloat::cmpEqual);
                })
         .value_or(false);
   }
   bool operator()(FLT_S inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
                       inst.rs2.ReadAPFloat(m_emu, false)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  if (rs1.isNaN() || rs2.isNaN()) {
-                   m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+                   m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
                    return inst.rd.Write(m_emu, 0);
                  }
-                 return inst.rd.Write(m_emu, rs1.compare(rs2) ==
-                                                 llvm::APFloat::cmpLessThan);
+                 return inst.rd.Write(m_emu,
+                                      rs1.compare(rs2) == APFloat::cmpLessThan);
                })
         .value_or(false);
   }
   bool operator()(FLE_S inst) {
-    return llvm::transformOptional(
+    return transformOptional(
                zipOpt(inst.rs1.ReadAPFloat(m_emu, false),
                       inst.rs2.ReadAPFloat(m_emu, false)),
                [&](auto &&tup) {
                  auto [rs1, rs2] = tup;
                  if (rs1.isNaN() || rs2.isNaN()) {
-                   m_emu.SetAccruedExceptions(llvm::APFloat::opInvalidOp);
+                   m_emu.SetAccruedExceptions(APFloat::opInvalidOp);
                    return inst.rd.Write(m_emu, 0);
                  }
                  return inst.rd.Write(m_emu, rs1.compare(rs2) !=
-                                                 llvm::APFloat::cmpGreaterThan);
+                                                 APFloat::cmpGreaterThan);
                })
         .value_or(false);
   }
   bool operator()(FCLASS_S inst) {
-    return llvm::transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
-                                   [&](auto &&rs1) {
-                                     uint64_t result = 0;
-                                     if (rs1.isInfinity() && rs1.isNegative())
-                                       result |= 1 << 0;
-                                     // neg normal
-                                     if (rs1.isNormal() && rs1.isNegative())
-                                       result |= 1 << 1;
-                                     // neg subnormal
-                                     if (rs1.isDenormal() && rs1.isNegative())
-                                       result |= 1 << 2;
-                                     if (rs1.isNegZero())
-                                       result |= 1 << 3;
-                                     if (rs1.isPosZero())
-                                       result |= 1 << 4;
-                                     // pos normal
-                                     if (rs1.isNormal() && !rs1.isNegative())
-                                       result |= 1 << 5;
-                                     // pos subnormal
-                                     if (rs1.isDenormal() && !rs1.isNegative())
-                                       result |= 1 << 6;
-                                     if (rs1.isInfinity() && !rs1.isNegative())
-                                       result |= 1 << 7;
-                                     if (rs1.isNaN()) {
-                                       if (rs1.isSignaling())
-                                         result |= 1 << 8;
-                                       else
-                                         result |= 1 << 9;
-                                     }
-                                     return inst.rd.Write(m_emu, result);
-                                   })
+    return transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FCVT_S_W inst) {
-    return llvm::transformOptional(inst.rs1.ReadI32(m_emu),
-                                   [&](auto &&rs1) {
-                                     llvm::APFloat apf(
-                                         llvm::APFloat::IEEEsingle(), rs1);
-                                     return inst.rd.WriteAPFloat(m_emu, apf);
-                                   })
+    return transformOptional(inst.rs1.ReadI32(m_emu),
+                               APFloat apf(APFloat::IEEEsingle(), rs1);
         .value_or(false);
   }
   bool operator()(FCVT_S_WU inst) {
-    return llvm::transformOptional(inst.rs1.ReadU32(m_emu),
-                                   [&](auto &&rs1) {
-                                     llvm::APFloat apf(
-                                         llvm::APFloat::IEEEsingle(), rs1);
-                                     return inst.rd.WriteAPFloat(m_emu, apf);
-                                   })
+    return transformOptional(inst.rs1.ReadU32(m_emu),
+                               APFloat apf(APFloat::IEEEsingle(), rs1);
         .value_or(false);
   }
   bool operator()(FMV_W_X inst) {
-    return llvm::transformOptional(inst.rs1.Read(m_emu),
-                                   [&](auto &&rs1) {
-                                     llvm::APInt apInt(32, NanUnBoxing(rs1));
-                                     llvm::APFloat apf(apInt.bitsToFloat());
-                                     return inst.rd.WriteAPFloat(m_emu, apf);
-                                   })
+    return transformOptional(inst.rs1.Read(m_emu),
+                               APInt apInt(32, NanUnBoxing(rs1));
+                               APFloat apf(apInt.bitsToFloat());
         .value_or(false);
   }
   bool operator()(FCVT_L_S inst) {
-    return llvm::transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
-                                   [&](auto &&rs1) {
-                                     int64_t res = rs1.convertToFloat();
-                                     return inst.rd.Write(m_emu, uint64_t(res));
-                                   })
+    return transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FCVT_LU_S inst) {
-    return llvm::transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
-                                   [&](auto &&rs1) {
-                                     uint64_t res = rs1.convertToFloat();
-                                     return inst.rd.Write(m_emu, res);
-                                   })
+    return transformOptional(inst.rs1.ReadAPFloat(m_emu, false),
         .value_or(false);
   }
   bool operator()(FCVT_S_L inst) {
-    return llvm::transformOptional(inst.rs1.ReadI64(m_emu),
-                                   [&](auto &&rs1) {
-                                     llvm::APFloat apf(
-                                         llvm::APFloat::IEEEsingle(), rs1);
-                                     return inst.rd.WriteAPFloat(m_emu, apf);
-                                   })
+    return transformOptional(inst.rs1.ReadI64(m_emu),
+                               APFloat apf(APFloat::IEEEsingle(), rs1);
         .value_or(false);
   }
   bool operator()(FCVT_S_LU inst) {
-    return llvm::transformOptional(inst.rs1.Read(m_emu),
-                                   [&](auto &&rs1) {
-                                     llvm::APFloat apf(
-                                         llvm::APFloat::IEEEsingle(), rs1);
-                                     return inst.rd.WriteAPFloat(m_emu, apf);
-                                   })
+    return transformOptional(inst.rs1.Read(m_emu),
+                               APFloat apf(APFloat::IEEEsingle(), rs1);
         .value_or(false);
   }
   bool operator()(INVALID inst) { return false; }
   bool operator()(RESERVED inst) { return false; }
   bool operator()(EBREAK inst) { return false; }
   bool operator()(HINT inst) { return true; }
   bool operator()(NOP inst) { return true; }
 };
bool EmulateInstructionRISCV::EvaluateInstruction(uint32_t options) {
   if (!new_pc)
     return false;
 
   // If the pc is not updated during execution, we do it here.
   return new_pc != old_pc ||
          WritePC(*old_pc + Executor::size(m_decoded.is_rvc));
 }
 
-llvm::Optional<DecodeResult>
-EmulateInstructionRISCV::ReadInstructionAt(lldb::addr_t addr) {
-  return llvm::transformOptional(ReadMem<uint32_t>(addr),
-                                 [&](uint32_t inst) { return Decode(inst); })
+Optional<DecodeResult> EmulateInstructionRISCV::ReadInstructionAt(addr_t addr) {
+  return transformOptional(ReadMem<uint32_t>(addr),
       .value_or(std::nullopt);
 }
 
 bool EmulateInstructionRISCV::ReadInstruction() {
   auto addr = ReadPC();
   m_addr = addr.value_or(LLDB_INVALID_ADDRESS);
   if (!addr)
     return false;
   auto inst = ReadInstructionAt(*addr);
   if (!inst)
     return false;
   m_decoded = *inst;
   if (inst->is_rvc)
     m_opcode.SetOpcode16(inst->inst, GetByteOrder());
   else
     m_opcode.SetOpcode32(inst->inst, GetByteOrder());
   return true;
 }
 
-llvm::Optional<lldb::addr_t> EmulateInstructionRISCV::ReadPC() {
+Optional<addr_t> EmulateInstructionRISCV::ReadPC() {
   bool success = false;
   auto addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
                                    LLDB_INVALID_ADDRESS, &success);
-  return success ? llvm::Optional<lldb::addr_t>(addr) : std::nullopt;
+  return success ? Optional<addr_t>(addr) : std::nullopt;
 }
 
-bool EmulateInstructionRISCV::WritePC(lldb::addr_t pc) {
+bool EmulateInstructionRISCV::WritePC(addr_t pc) {
   EmulateInstruction::Context ctx;
   ctx.type = eContextAdvancePC;
   ctx.SetNoArgs();
   return WriteRegisterUnsigned(ctx, eRegisterKindGeneric,
                                LLDB_REGNUM_GENERIC_PC, pc);
 }
 
-llvm::RoundingMode EmulateInstructionRISCV::GetRoundingMode() {
+RoundingMode EmulateInstructionRISCV::GetRoundingMode() {
   bool success = false;
   auto fcsr = ReadRegisterUnsigned(eRegisterKindLLDB, fpr_fcsr_riscv,
                                    LLDB_INVALID_ADDRESS, &success);
   if (!success)
-    return llvm::RoundingMode::Invalid;
+    return RoundingMode::Invalid;
   auto frm = (fcsr >> 5) & 0x7;
   switch (frm) {
   case 0b000:
-    return llvm::RoundingMode::NearestTiesToEven;
+    return RoundingMode::NearestTiesToEven;
   case 0b001:
-    return llvm::RoundingMode::TowardZero;
+    return RoundingMode::TowardZero;
   case 0b010:
-    return llvm::RoundingMode::TowardNegative;
+    return RoundingMode::TowardNegative;
   case 0b011:
-    return llvm::RoundingMode::TowardPositive;
+    return RoundingMode::TowardPositive;
   case 0b111:
-    return llvm::RoundingMode::Dynamic;
+    return RoundingMode::Dynamic;
   default:
     // Reserved for future use.
-    return llvm::RoundingMode::Invalid;
+    return RoundingMode::Invalid;
   }
 }
 
 bool EmulateInstructionRISCV::SetAccruedExceptions(
-    llvm::APFloatBase::opStatus opStatus) {
+    APFloatBase::opStatus opStatus) {
   bool success = false;
   auto fcsr = ReadRegisterUnsigned(eRegisterKindLLDB, fpr_fcsr_riscv,
                                    LLDB_INVALID_ADDRESS, &success);
   if (!success)
     return false;
   switch (opStatus) {
-  case llvm::APFloatBase::opInvalidOp:
+  case APFloatBase::opInvalidOp:
     fcsr |= 1 << 4;
     break;
-  case llvm::APFloatBase::opDivByZero:
+  case APFloatBase::opDivByZero:
     fcsr |= 1 << 3;
     break;
-  case llvm::APFloatBase::opOverflow:
+  case APFloatBase::opOverflow:
     fcsr |= 1 << 2;
     break;
-  case llvm::APFloatBase::opUnderflow:
+  case APFloatBase::opUnderflow:
     fcsr |= 1 << 1;
     break;
-  case llvm::APFloatBase::opInexact:
+  case APFloatBase::opInexact:
     fcsr |= 1 << 0;
     break;
-  case llvm::APFloatBase::opOK:
+  case APFloatBase::opOK:
     break;
   }
   EmulateInstruction::Context ctx;
   ctx.type = eContextRegisterStore;
   ctx.SetNoArgs();
   return WriteRegisterUnsigned(ctx, eRegisterKindLLDB, fpr_fcsr_riscv, fcsr);
 }
 
-llvm::Optional<RegisterInfo>
-EmulateInstructionRISCV::GetRegisterInfo(lldb::RegisterKind reg_kind,
+Optional<RegisterInfo>
+EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
                                          uint32_t reg_index) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_index) {
     case LLDB_REGNUM_GENERIC_PC:
       reg_kind = eRegisterKindLLDB;
       reg_index = gpr_pc_riscv;
       break;
     case LLDB_REGNUM_GENERIC_SP:

lldb/source/Plugins/Instruction/RISCV/RISCVInstructions.h

 
 #include <cstdint>
 #include <variant>
 
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/Optional.h"
 
 namespace lldb_private {
+using namespace llvm;
 
 class EmulateInstructionRISCV;
 
 struct Rd {
   uint32_t rd;
   bool Write(EmulateInstructionRISCV &emulator, uint64_t value);
-  bool WriteAPFloat(EmulateInstructionRISCV &emulator, llvm::APFloat value);
+  bool WriteAPFloat(EmulateInstructionRISCV &emulator, APFloat value);
 };
 
 struct Rs {
   uint32_t rs;
-  llvm::Optional<uint64_t> Read(EmulateInstructionRISCV &emulator);
-  llvm::Optional<int32_t> ReadI32(EmulateInstructionRISCV &emulator);
-  llvm::Optional<int64_t> ReadI64(EmulateInstructionRISCV &emulator);
-  llvm::Optional<uint32_t> ReadU32(EmulateInstructionRISCV &emulator);
-  llvm::Optional<llvm::APFloat> ReadAPFloat(EmulateInstructionRISCV &emulator,
-                                            bool isDouble);
+  Optional<uint64_t> Read(EmulateInstructionRISCV &emulator);
+  Optional<int32_t> ReadI32(EmulateInstructionRISCV &emulator);
+  Optional<int64_t> ReadI64(EmulateInstructionRISCV &emulator);
+  Optional<uint32_t> ReadU32(EmulateInstructionRISCV &emulator);
+  Optional<APFloat> ReadAPFloat(EmulateInstructionRISCV &emulator,
 };
 
 #define I_TYPE_INST(NAME)                                                      \
   struct NAME {                                                                \
     Rd rd;                                                                     \
     Rs rs1;                                                                    \
     uint32_t imm;                                                              \
   }

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

 #include "lldb/Target/ExecutionContext.h"
 #include "lldb/Utility/ArchSpec.h"
 #include "lldb/Utility/RegisterValue.h"
 
 #include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
 #include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
 #include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
 
+using namespace llvm;
 using namespace lldb;
 using namespace lldb_private;
 
 struct RISCVEmulatorTester : public EmulateInstructionRISCV, testing::Test {
   RegisterInfoPOSIX_riscv64::GPR gpr;
   RegisterInfoPOSIX_riscv64::FPR fpr;
   uint8_t memory[1024] = {0};
 
static bool WriteRegisterCallback(EmulateInstruction *instruction,
     if (reg >= fpr_f0_riscv && reg <= fpr_f31_riscv)
       tester->fpr.fpr[reg - fpr_f0_riscv] = reg_value.GetAsUInt64();
     if (reg == fpr_fcsr_riscv)
       tester->fpr.fcsr = reg_value.GetAsUInt32();
     return true;
   }
 
   static size_t ReadMemoryCallback(EmulateInstruction *instruction, void *baton,
-                                   const Context &context, lldb::addr_t addr,
+                                   const Context &context, addr_t addr,
                                    void *dst, size_t length) {
     RISCVEmulatorTester *tester = (RISCVEmulatorTester *)instruction;
     assert(addr + length < sizeof(tester->memory));
     memcpy(dst, tester->memory + addr, length);
     return length;
   };
 
   static size_t WriteMemoryCallback(EmulateInstruction *instruction,
                                     void *baton, const Context &context,
-                                    lldb::addr_t addr, const void *dst,
+                                    addr_t addr, const void *dst,
                                     size_t length) {
     RISCVEmulatorTester *tester = (RISCVEmulatorTester *)instruction;
     assert(addr + length < sizeof(tester->memory));
     memcpy(tester->memory + addr, dst, length);
     return length;
   };
 
   bool DecodeAndExecute(uint32_t inst, bool ignore_cond) {
     return llvm::transformOptional(
                Decode(inst),
                [&](DecodeResult res) { return Execute(res, ignore_cond); })
         .value_or(false);
   }
 
   void ClearAll() {
     memset(&gpr, 0, sizeof(gpr));
     memset(&fpr, 0, sizeof(fpr));
     memset(memory, 0, sizeof(memory));
   }
 };
 
 TEST_F(RISCVEmulatorTester, testJAL) {
-  lldb::addr_t old_pc = 0x114514;
+  addr_t old_pc = 0x114514;
   WritePC(old_pc);
   // jal x1, -6*4
   uint32_t inst = 0b11111110100111111111000011101111;
   ASSERT_TRUE(DecodeAndExecute(inst, false));
   auto x1 = gpr.gpr[1];
   auto pc = ReadPC();
   ASSERT_TRUE(pc.has_value());
   ASSERT_EQ(x1, old_pc + 4);
   ASSERT_EQ(*pc, old_pc + (-6 * 4));
 }
 
 constexpr uint32_t EncodeIType(uint32_t opcode, uint32_t funct3, uint32_t rd,
                                uint32_t rs1, uint32_t imm) {
   return imm << 20 | rs1 << 15 | funct3 << 12 | rd << 7 | opcode;
 }
 
 constexpr uint32_t EncodeJALR(uint32_t rd, uint32_t rs1, int32_t offset) {
   return EncodeIType(0b1100111, 0, rd, rs1, uint32_t(offset));
 }
 
 TEST_F(RISCVEmulatorTester, testJALR) {
-  lldb::addr_t old_pc = 0x114514;
-  lldb::addr_t old_x2 = 0x1024;
+  addr_t old_pc = 0x114514;
+  addr_t old_x2 = 0x1024;
   WritePC(old_pc);
   gpr.gpr[2] = old_x2;
   // jalr x1, x2(-255)
   uint32_t inst = EncodeJALR(1, 2, -255);
   ASSERT_TRUE(DecodeAndExecute(inst, false));
   auto x1 = gpr.gpr[1];
   auto pc = ReadPC();
   ASSERT_TRUE(pc.has_value());
constexpr uint32_t BGEU(uint32_t rs1, uint32_t rs2, int32_t offset) {
   return EncodeBType(0b1100011, 0b111, rs1, rs2, uint32_t(offset));
 }
 
 using EncoderB = uint32_t (*)(uint32_t rs1, uint32_t rs2, int32_t offset);
 
 static void testBranch(RISCVEmulatorTester *tester, EncoderB encoder,
                        bool branched, uint64_t rs1, uint64_t rs2) {
   // prepare test registers
-  lldb::addr_t old_pc = 0x114514;
+  addr_t old_pc = 0x114514;
   tester->WritePC(old_pc);
   tester->gpr.gpr[1] = rs1;
   tester->gpr.gpr[2] = rs2;
   // b<cmp> x1, x2, (-256)
   uint32_t inst = encoder(1, 2, -256);
   ASSERT_TRUE(tester->DecodeAndExecute(inst, false));
   auto pc = tester->ReadPC();
   ASSERT_TRUE(pc.has_value());

 using RS1 = uint64_t;
 using RS2 = uint64_t;
 using PC = uint64_t;
 using RDComputer = std::function<uint64_t(RS1, RS2, PC)>;
 
 static void TestInst(RISCVEmulatorTester *tester, DecodeResult inst,
                      bool has_rs2, RDComputer rd_val) {
 
-  lldb::addr_t old_pc = 0x114514;
+  addr_t old_pc = 0x114514;
   tester->WritePC(old_pc);
   uint32_t rd = DecodeRD(inst.inst);
   uint32_t rs1 = DecodeRS1(inst.inst);
   uint32_t rs2 = 0;
 
   uint64_t rs1_val = 0x19;
   uint64_t rs2_val = 0x81;
 
static void TestFloatCalInst(RISCVEmulatorTester *tester, DecodeResult inst,
   std::vector<std::string> FloatCMP = {"FEQ_S", "FLT_S", "FLE_S"};
   std::vector<std::string> FloatCal3 = {"FMADD_S", "FMSUB_S", "FNMSUB_S",
                                         "FNMADD_S"};
 
   uint32_t rd = DecodeRD(inst.inst);
   uint32_t rs1 = DecodeRS1(inst.inst);
   uint32_t rs2 = DecodeRS2(inst.inst);
 
-  llvm::APFloat ap_rs1_val(rs1_val);
-  llvm::APFloat ap_rs2_val(rs2_val);
-  llvm::APFloat ap_rs3_val(0.5f);
+  APFloat ap_rs1_val(rs1_val);
+  APFloat ap_rs2_val(rs2_val);
+  APFloat ap_rs3_val(0.5f);
 
   if (rs1)
     tester->fpr.fpr[rs1] = ap_rs1_val.bitcastToAPInt().getZExtValue();
   if (rs2)
     tester->fpr.fpr[rs2] = ap_rs2_val.bitcastToAPInt().getZExtValue();
   for (auto i : FloatCal3) {
     if (inst.pattern.name == i) {
       uint32_t rs3 = DecodeRS3(inst.inst);
       tester->fpr.fpr[rs3] = ap_rs3_val.bitcastToAPInt().getZExtValue();
     }
   }
   ASSERT_TRUE(tester->Execute(inst, false));
   for (auto i : FloatCMP) {
     if (inst.pattern.name == i) {
       ASSERT_EQ(tester->gpr.gpr[rd], rd_exp);
       return;
     }
   }
 
-  llvm::APInt apInt(32, tester->fpr.fpr[rd]);
-  llvm::APFloat rd_val(apInt.bitsToFloat());
+  APInt apInt(32, tester->fpr.fpr[rd]);
+  APFloat rd_val(apInt.bitsToFloat());
   ASSERT_EQ(rd_val.convertToFloat(), rd_exp);
 }
 
 TEST_F(RISCVEmulatorTester, TestFloatInst) {
   std::vector<FloatCalInst> tests = {
       {0x21F253, "FADD_S", 0.5f, 0.5f, 1.0f},
       {0x821F253, "FSUB_S", 1.0f, 0.5f, 0.5f},
       {0x1021F253, "FMUL_S", 0.5f, 0.5f, 0.25f},
static void TestFCVT(RISCVEmulatorTester *tester, DecodeResult inst) {
   std::vector<std::string> FloatToInt = {"FCVT_W_S", "FCVT_WU_S"};
   std::vector<std::string> IntToFloat = {"FCVT_S_W", "FCVT_S_WU"};
 
   uint32_t rd = DecodeRD(inst.inst);
   uint32_t rs1 = DecodeRS1(inst.inst);
 
   for (auto i : FloatToInt) {
     if (inst.pattern.name == i) {
-      llvm::APFloat apf_rs1_val(12.0f);
+      APFloat apf_rs1_val(12.0f);
       tester->fpr.fpr[rs1] = apf_rs1_val.bitcastToAPInt().getZExtValue();
       ASSERT_TRUE(tester->Execute(inst, false));
       ASSERT_EQ(tester->gpr.gpr[rd], uint64_t(12));
       return;
     }
   }
 
   for (auto i : IntToFloat) {
     if (inst.pattern.name == i) {
       tester->gpr.gpr[rs1] = 12;
       ASSERT_TRUE(tester->Execute(inst, false));
-      llvm::APInt apInt(32, tester->fpr.fpr[rd]);
-      llvm::APFloat rd_val(apInt.bitsToFloat());
+      APInt apInt(32, tester->fpr.fpr[rd]);
+      APFloat rd_val(apInt.bitsToFloat());
       ASSERT_EQ(rd_val.convertToFloat(), 12.0f);
       return;
     }
   }
 }
 
 struct FCVTInst {
   uint32_t inst;
for (auto i : tests) {
     TestFCVT(this, decode.value());
   }
 }
 
 TEST_F(RISCVEmulatorTester, TestFloatLSInst) {
   uint32_t FLWInst = 0x1A207;  // imm = 0
   uint32_t FSWInst = 0x21A827; // imm = 16
 
-  llvm::APFloat apf(12.0f);
+  APFloat apf(12.0f);
   uint64_t bits = apf.bitcastToAPInt().getZExtValue();
 
   *(uint64_t *)this->memory = bits;
   auto decode = this->Decode(FLWInst);
   ASSERT_TRUE(decode.has_value());
   std::string name = decode->pattern.name;
   ASSERT_EQ(name, "FLW");
   ASSERT_TRUE(this->Execute(decode.value(), false));
   ASSERT_EQ(this->fpr.fpr[DecodeRD(FLWInst)], bits);
 
   this->fpr.fpr[DecodeRS2(FSWInst)] = bits;
   decode = this->Decode(FSWInst);
   ASSERT_TRUE(decode.has_value());
   name = decode->pattern.name;
   ASSERT_EQ(name, "FSW");
   ASSERT_TRUE(this->Execute(decode.value(), false));
   ASSERT_EQ(*(uint32_t *)(this->memory + 16), bits);
 }
 
 TEST_F(RISCVEmulatorTester, TestFMV_X_WInst) {
   auto FMV_X_WInst = 0xE0018253;
 
-  llvm::APFloat apf(12.0f);
+  APFloat apf(12.0f);
   auto bits = NanBoxing(apf.bitcastToAPInt().getZExtValue());
   this->fpr.fpr[DecodeRS1(FMV_X_WInst)] = bits;
   auto decode = this->Decode(FMV_X_WInst);
   ASSERT_TRUE(decode.has_value());
   std::string name = decode->pattern.name;
   ASSERT_EQ(name, "FMV_X_W");
   ASSERT_TRUE(this->Execute(decode.value(), false));
   ASSERT_EQ(this->gpr.gpr[DecodeRD(FMV_X_WInst)], bits);
 }
 
 TEST_F(RISCVEmulatorTester, TestFMV_W_XInst) {
   auto FMV_W_XInst = 0xF0018253;
 
-  llvm::APFloat apf(12.0f);
+  APFloat apf(12.0f);
   uint64_t bits = NanUnBoxing(apf.bitcastToAPInt().getZExtValue());
   this->gpr.gpr[DecodeRS1(FMV_W_XInst)] = bits;
   auto decode = this->Decode(FMV_W_XInst);
   ASSERT_TRUE(decode.has_value());
   std::string name = decode->pattern.name;
   ASSERT_EQ(name, "FMV_W_X");
   ASSERT_TRUE(this->Execute(decode.value(), false));
   ASSERT_EQ(this->fpr.fpr[DecodeRD(FMV_W_XInst)], bits);
 }