[AArch64] RASv2 Assembly Support

[lenary]

Summary

This feature adds upstream support for FEAT_RASv2 and FEAT_PFAR. Both
are system-register-only, but FEAT_RAS is behind the command-line
extension "+ras", so FEAT_RASv2 is behind "+rasv2".

This patch includes support for ID_AA64MMFR4_EL1. This is an ID system
register so it is not behind any feature flags.

[lenary]

Adding a handful of reviewers.

[pratlucas]

LGTM.

[stuij]

LGTM

llvm/include/llvm/Support/AArch64TargetParser.h

enum ArchExtKind : uint64_t {
   AEK_B16B16 =      1ULL << 46, // FEAT_B16B16
   AEK_SMEF16F16 =   1ULL << 47, // FEAT_SMEF16F16
   AEK_CSSC =        1ULL << 48, // FEAT_CSSC
   AEK_RCPC3 =       1ULL << 49, // FEAT_LRCPC3
   AEK_THE =         1ULL << 50, // FEAT_THE
   AEK_D128 =        1ULL << 51, // FEAT_D128
   AEK_LSE128 =      1ULL << 52, // FEAT_LSE128
   AEK_SPECRES2 =    1ULL << 53, // FEAT_SPECRES2
+  AEK_RASv2 =       1ULL << 54, // FEAT_RASv2
 };
 // clang-format on
 
 enum class ArchKind {
 #define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) ID,
 #include "AArch64TargetParser.def"
 };
 

llvm/include/llvm/Support/AArch64TargetParser.def

AARCH64_ARCH("armv8.8-a", ARMV8_8A, "+v8.8a",
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
               AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
 AARCH64_ARCH("armv8.9-a", ARMV8_9A, "+v8.9a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
-              AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
+              AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM |
+              AArch64::AEK_RASv2))
 AARCH64_ARCH("armv9-a",   ARMV9A, "+v9a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_SVE2))
 AARCH64_ARCH("armv9.1-a", ARMV9_1A, "+v9.1a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
 AARCH64_ARCH("armv9.2-a", ARMV9_2A, "+v9.2a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
 AARCH64_ARCH("armv9.3-a", ARMV9_3A, "+v9.3a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
 AARCH64_ARCH("armv9.4-a", ARMV9_4A, "+v9.4a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
-              AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
+              AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2 |
+              AArch64::AEK_RASv2))
 // For v8-R, we do not enable crypto and align with GCC that enables a more
 // minimal set of optional architecture extensions.
 AARCH64_ARCH("armv8-r", ARMV8R, "+v8r",
              (AArch64::AEK_CRC     | AArch64::AEK_RDM  | AArch64::AEK_SSBS |
               AArch64::AEK_DOTPROD | AArch64::AEK_FP   | AArch64::AEK_SIMD |
               AArch64::AEK_FP16    | AArch64::AEK_FP16FML | AArch64::AEK_RAS |
               AArch64::AEK_RCPC    | AArch64::AEK_SB))
 #undef AARCH64_ARCH

 AARCH64_ARCH_EXT_NAME("aes",          AArch64::AEK_AES,         "+aes",          "-aes")
 AARCH64_ARCH_EXT_NAME("dotprod",      AArch64::AEK_DOTPROD,     "+dotprod",      "-dotprod")
 AARCH64_ARCH_EXT_NAME("fp",           AArch64::AEK_FP,          "+fp-armv8",     "-fp-armv8")
 AARCH64_ARCH_EXT_NAME("simd",         AArch64::AEK_SIMD,        "+neon",         "-neon")
 AARCH64_ARCH_EXT_NAME("fp16",         AArch64::AEK_FP16,        "+fullfp16",     "-fullfp16")
 AARCH64_ARCH_EXT_NAME("fp16fml",      AArch64::AEK_FP16FML,     "+fp16fml",      "-fp16fml")
 AARCH64_ARCH_EXT_NAME("profile",      AArch64::AEK_PROFILE,     "+spe",          "-spe")
 AARCH64_ARCH_EXT_NAME("ras",          AArch64::AEK_RAS,         "+ras",          "-ras")
+AARCH64_ARCH_EXT_NAME("rasv2",        AArch64::AEK_RASv2,       "+rasv2",        "-rasv2")
 AARCH64_ARCH_EXT_NAME("sve",          AArch64::AEK_SVE,         "+sve",          "-sve")
 AARCH64_ARCH_EXT_NAME("sve2",         AArch64::AEK_SVE2,        "+sve2",         "-sve2")
 AARCH64_ARCH_EXT_NAME("sve2-aes",     AArch64::AEK_SVE2AES,     "+sve2-aes",     "-sve2-aes")
 AARCH64_ARCH_EXT_NAME("sve2-sm4",     AArch64::AEK_SVE2SM4,     "+sve2-sm4",     "-sve2-sm4")
 AARCH64_ARCH_EXT_NAME("sve2-sha3",    AArch64::AEK_SVE2SHA3,    "+sve2-sha3",    "-sve2-sha3")
 AARCH64_ARCH_EXT_NAME("sve2-bitperm", AArch64::AEK_SVE2BITPERM, "+sve2-bitperm", "-sve2-bitperm")
 AARCH64_ARCH_EXT_NAME("sve2p1",       AArch64::AEK_SVE2p1,      "+sve2p1",       "-sve2p1")
 AARCH64_ARCH_EXT_NAME("b16b16",       AArch64::AEK_B16B16,      "+b16b16",       "-b16b16")

llvm/lib/Target/AArch64/AArch64.td

def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
   "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
 
 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
   "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">;
 
 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
   "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
 
+def FeatureRASv2 : SubtargetFeature<"rasv2", "HasRASv2", "true",
+  "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)",
+  [FeatureRAS]>;
+
 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)">;
 
 def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
   "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
 
 def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
   "Enable out of line atomics to support LSE instructions">;

 
 def HasV8_8aOps : SubtargetFeature<
   "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
   [HasV8_7aOps, FeatureHBC, FeatureMOPS]>;
 
 def HasV8_9aOps : SubtargetFeature<
   "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
   [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2,
-   FeatureCSSC]>;
+   FeatureCSSC, FeatureRASv2]>;
 
 def HasV9_0aOps : SubtargetFeature<
   "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
   [HasV8_5aOps, FeatureMEC, FeatureSVE2]>;
 
 def HasV9_1aOps : SubtargetFeature<
   "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
   [HasV8_6aOps, HasV9_0aOps]>;

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : ROSysReg<"ID_AA64AFR1_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b101>;
 def : ROSysReg<"ID_AA64ISAR0_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b000>;
 def : ROSysReg<"ID_AA64ISAR1_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b001>;
 def : ROSysReg<"ID_AA64ISAR2_EL1",    0b11, 0b000, 0b0000, 0b0110, 0b010>;
 def : ROSysReg<"ID_AA64MMFR0_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b000>;
 def : ROSysReg<"ID_AA64MMFR1_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b001>;
 def : ROSysReg<"ID_AA64MMFR2_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b010>;
 def : ROSysReg<"ID_AA64MMFR3_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b011>;
+def : ROSysReg<"ID_AA64MMFR4_EL1",    0b11, 0b000, 0b0000, 0b0111, 0b100>;
 def : ROSysReg<"MVFR0_EL1",           0b11, 0b000, 0b0000, 0b0011, 0b000>;
 def : ROSysReg<"MVFR1_EL1",           0b11, 0b000, 0b0000, 0b0011, 0b001>;
 def : ROSysReg<"MVFR2_EL1",           0b11, 0b000, 0b0000, 0b0011, 0b010>;
 def : ROSysReg<"RVBAR_EL1",           0b11, 0b000, 0b1100, 0b0000, 0b001>;
 def : ROSysReg<"RVBAR_EL2",           0b11, 0b100, 0b1100, 0b0000, 0b001>;
 def : ROSysReg<"RVBAR_EL3",           0b11, 0b110, 0b1100, 0b0000, 0b001>;
 def : ROSysReg<"ISR_EL1",             0b11, 0b000, 0b1100, 0b0001, 0b000>;
 def : ROSysReg<"CNTPCT_EL0",          0b11, 0b011, 0b1110, 0b0000, 0b001>;

 def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>;
 def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>;
 }
 
 // v9a Realm Management Extension registers
 let Requires = [{ {AArch64::FeatureRME} }] in {
-def : RWSysReg<"MFAR_EL3",  0b11, 0b110, 0b0110, 0b0000, 0b101>;
 def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
 def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
 }
+// MFAR_EL3 is part of both FEAT_RME and FEAT_PFAR (further below). The latter
+// is unconditional so this register has to be too.
+def : RWSysReg<"MFAR_EL3",  0b11, 0b110, 0b0110, 0b0000, 0b101>;
 
 // v9a Memory Encryption Contexts Extension registers
 let Requires = [{ {AArch64::FeatureMEC} }] in {
 def : ROSysReg<"MECIDR_EL2",     0b11, 0b100, 0b1010, 0b1000, 0b111>;
 def : RWSysReg<"MECID_P0_EL2",   0b11, 0b100, 0b1010, 0b1000, 0b000>;
 def : RWSysReg<"MECID_A0_EL2",   0b11, 0b100, 0b1010, 0b1000, 0b001>;
 def : RWSysReg<"MECID_P1_EL2",   0b11, 0b100, 0b1010, 0b1000, 0b010>;
 def : RWSysReg<"MECID_A1_EL2",   0b11, 0b100, 0b1010, 0b1000, 0b011>;

 def : RWSysReg<"TRCITECR_EL1",      0b11, 0b000, 0b0001, 0b0010, 0b011>;
 def : RWSysReg<"TRCITECR_EL12",     0b11, 0b101, 0b0001, 0b0010, 0b011>;
 def : RWSysReg<"TRCITECR_EL2",      0b11, 0b100, 0b0001, 0b0010, 0b011>;
 }
 
 // v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS)
 //                                  Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"PMSDSFR_EL1",       0b11, 0b000, 0b1001, 0b1010, 0b100>;
+
+// v8.9a/9.4a RASv2 (FEAT_RASv2)
+//                                  Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureRASv2} }] in
+def : ROSysReg<"ERXGSR_EL1",        0b11, 0b000, 0b0101, 0b0011, 0b010>;
+
+// v8.9a/9.4a Physical Fault Address (FEAT_PFAR)
+//                                  Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"PFAR_EL1",          0b11, 0b000, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"PFAR_EL12",         0b11, 0b101, 0b0110, 0b0000, 0b101>;
+def : RWSysReg<"PFAR_EL2",          0b11, 0b100, 0b0110, 0b0000, 0b101>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

const FeatureBitset Features;
     {"sm4", {AArch64::FeatureSM4}},
     {"sha3", {AArch64::FeatureSHA3}},
     {"sha2", {AArch64::FeatureSHA2}},
     {"aes", {AArch64::FeatureAES}},
     {"crypto", {AArch64::FeatureCrypto}},
     {"fp", {AArch64::FeatureFPARMv8}},
     {"simd", {AArch64::FeatureNEON}},
     {"ras", {AArch64::FeatureRAS}},
+    {"rasv2", {AArch64::FeatureRASv2}},
     {"lse", {AArch64::FeatureLSE}},
     {"predres", {AArch64::FeaturePredRes}},
     {"predres2", {AArch64::FeatureSPECRES2}},
     {"ccdp", {AArch64::FeatureCacheDeepPersist}},
     {"mte", {AArch64::FeatureMTE}},
     {"memtag", {AArch64::FeatureMTE}},
     {"tlb-rmi", {AArch64::FeatureTLB_RMI}},
     {"pan", {AArch64::FeaturePAN}},

llvm/test/MC/AArch64/arm64-system-encoding.s

; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate
   mrs x3, ID_AA64DFR1_EL1
   mrs x3, ID_AA64ISAR0_EL1
   mrs x3, ID_AA64ISAR1_EL1
   mrs x3, ID_AA64ISAR2_EL1
   mrs x3, ID_AA64MMFR0_EL1
   mrs x3, ID_AA64MMFR1_EL1
   mrs x3, ID_AA64MMFR2_EL1
   mrs x3, ID_AA64MMFR3_EL1
+  mrs x3, ID_AA64MMFR4_EL1
   mrs x3, ID_AA64PFR0_EL1
   mrs x3, ID_AA64PFR1_EL1
   mrs x3, ID_AA64PFR2_EL1
   mrs x3, IFSR32_EL2
   mrs x3, ISR_EL1
   mrs x3, MAIR_EL1
   mrs x3, MAIR_EL2
   mrs x3, MAIR_EL3

 ; CHECK: mrs x3, ID_AA64DFR1_EL1        ; encoding: [0x23,0x05,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64ISAR0_EL1       ; encoding: [0x03,0x06,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64ISAR1_EL1       ; encoding: [0x23,0x06,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64ISAR2_EL1       ; encoding: [0x43,0x06,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64MMFR0_EL1       ; encoding: [0x03,0x07,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64MMFR1_EL1       ; encoding: [0x23,0x07,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64MMFR2_EL1       ; encoding: [0x43,0x07,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64MMFR3_EL1       ; encoding: [0x63,0x07,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64MMFR4_EL1       ; encoding: [0x83,0x07,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64PFR0_EL1        ; encoding: [0x03,0x04,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64PFR1_EL1        ; encoding: [0x23,0x04,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64PFR2_EL1        ; encoding: [0x43,0x04,0x38,0xd5]
 ; CHECK: mrs x3, IFSR32_EL2             ; encoding: [0x23,0x50,0x3c,0xd5]
 ; CHECK: mrs x3, ISR_EL1                ; encoding: [0x03,0xc1,0x38,0xd5]
 ; CHECK: mrs x3, MAIR_EL1               ; encoding: [0x03,0xa2,0x38,0xd5]
 ; CHECK: mrs x3, MAIR_EL2               ; encoding: [0x03,0xa2,0x3c,0xd5]
 ; CHECK: mrs x3, MAIR_EL3               ; encoding: [0x03,0xa2,0x3e,0xd5]

llvm/test/MC/AArch64/armv8.9a-pfar.s

+// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s
+
+mrs x0, PFAR_EL1
+// CHECK: mrs x0, PFAR_EL1                    // encoding: [0xa0,0x60,0x38,0xd5]
+msr PFAR_EL1, x0
+// CHECK: msr PFAR_EL1, x0                    // encoding: [0xa0,0x60,0x18,0xd5]
+
+mrs x0, PFAR_EL2
+// CHECK: mrs x0, PFAR_EL2                    // encoding: [0xa0,0x60,0x3c,0xd5]
+msr PFAR_EL2, x0
+// CHECK: msr PFAR_EL2, x0                    // encoding: [0xa0,0x60,0x1c,0xd5]
+
+mrs x0, PFAR_EL12
+// CHECK: mrs x0, PFAR_EL12                   // encoding: [0xa0,0x60,0x3d,0xd5]
+msr PFAR_EL12, x0
+// CHECK: msr PFAR_EL12, x0                   // encoding: [0xa0,0x60,0x1d,0xd5]
+
+mrs x0, MFAR_EL3
+// CHECK: mrs x0, MFAR_EL3                    // encoding: [0xa0,0x60,0x3e,0xd5]
+msr MFAR_EL3, x0
+// CHECK: msr MFAR_EL3, x0                    // encoding: [0xa0,0x60,0x1e,0xd5]

llvm/test/MC/AArch64/armv8.9a-rasv2-error.s

+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+rasv2 < %s 2>&1| FileCheck %s
+
+msr ERXGSR_EL1, x0
+// CHECK: [[@LINE-1]]:5: error: expected writable system register or pstate

llvm/test/MC/AArch64/armv8.9a-rasv2.s

+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+rasv2 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.9a < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v9.4a < %s | FileCheck %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu               < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RAS %s
+
+mrs x0, ERXGSR_EL1
+// CHECK: mrs x0, ERXGSR_EL1                  // encoding: [0x40,0x53,0x38,0xd5]
+// ERROR-NO-RAS: [[@LINE-2]]:9: error: expected readable system register

llvm/test/MC/AArch64/armv9a-rme.s

 mrs x0, GPCCR_EL3
 mrs x0, GPTBR_EL3
 // CHECK: msr MFAR_EL3,  x0   // encoding: [0xa0,0x60,0x1e,0xd5]
 // CHECK: msr GPCCR_EL3, x0   // encoding: [0xc0,0x21,0x1e,0xd5]
 // CHECK: msr GPTBR_EL3, x0   // encoding: [0x80,0x21,0x1e,0xd5]
 // CHECK: mrs x0, MFAR_EL3    // encoding: [0xa0,0x60,0x3e,0xd5]
 // CHECK: mrs x0, GPCCR_EL3   // encoding: [0xc0,0x21,0x3e,0xd5]
 // CHECK: mrs x0, GPTBR_EL3   // encoding: [0x80,0x21,0x3e,0xd5]
+// CHECK-NO-RME: msr MFAR_EL3,  x0   // encoding: [0xa0,0x60,0x1e,0xd5]
 // CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
 // CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
-// CHECK-NO-RME-ERROR: [[@LINE-12]]:5: error: expected writable system register
-// CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
+// CHECK-NO-RME: mrs x0, MFAR_EL3    // encoding: [0xa0,0x60,0x3e,0xd5]
 // CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
 // CHECK-NO-RME-ERROR: [[@LINE-12]]:9: error: expected readable system register
 
 tlbi rpaos, x0
 tlbi rpalos, x0
 tlbi paallos
 tlbi paall
 // CHECK: tlbi rpaos, x0      // encoding: [0x60,0x84,0x0e,0xd5]

llvm/test/MC/AArch64/basic-a64-diagnostics.s

// write-only registers actually are.
         msr ID_AA64AFR0_EL1, x12
         msr ID_AA64AFR1_EL1, x12
         msr ID_AA64ISAR0_EL1, x12
         msr ID_AA64ISAR1_EL1, x12
         msr ID_AA64MMFR0_EL1, x12
         msr ID_AA64MMFR1_EL1, x12
         msr ID_AA64MMFR2_EL1, x12
         msr ID_AA64MMFR3_EL1, x12
+        msr ID_AA64MMFR4_EL1, x12
         msr PMCEID0_EL0, x12
         msr PMCEID1_EL0, x12
         msr PMMIR_EL1, x12
         msr RVBAR_EL1, x12
         msr RVBAR_EL2, x12
         msr RVBAR_EL3, x12
         msr ISR_EL1, x12
         msr CNTPCT_EL0, x12

 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64MMFR2_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64MMFR3_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr ID_AA64MMFR4_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr PMCEID0_EL0, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr PMCEID1_EL0, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr PMMIR_EL1, x12
 // CHECK-ERROR-NEXT:             ^

llvm/test/MC/AArch64/basic-a64-instructions.s

// CHECK: msr      {{tcr2_el2|TCR2_EL2}}, x12       // encoding: [0x6c,0x20,0x1c,0xd5]
   mrs x9, ID_AA64AFR0_EL1
   mrs x9, ID_AA64AFR1_EL1
   mrs x9, ID_AA64ISAR0_EL1
   mrs x9, ID_AA64ISAR1_EL1
   mrs x9, ID_AA64MMFR0_EL1
   mrs x9, ID_AA64MMFR1_EL1
   mrs x9, ID_AA64MMFR2_EL1
   mrs x9, ID_AA64MMFR3_EL1
+  mrs x9, ID_AA64MMFR4_EL1
   mrs x9, SCTLR_EL1
   mrs x9, SCTLR_EL2
   mrs x9, SCTLR_EL3
   mrs x9, ACTLR_EL1
   mrs x9, ACTLR_EL2
   mrs x9, ACTLR_EL3
   mrs x9, CPACR_EL1
   mrs x9, HCR_EL2

 // CHECK: mrs      x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}}        // encoding: [0x89,0x05,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}        // encoding: [0xa9,0x05,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}       // encoding: [0x09,0x06,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}       // encoding: [0x29,0x06,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}       // encoding: [0x09,0x07,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}       // encoding: [0x29,0x07,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64mmfr2_el1|ID_AA64MMFR2_EL1}}       // encoding: [0x49,0x07,0x38,0xd5]
 // CHECK: mrs      x9, {{id_aa64mmfr3_el1|ID_AA64MMFR3_EL1}}       // encoding: [0x69,0x07,0x38,0xd5]
+// CHECK: mrs      x9, {{id_aa64mmfr4_el1|ID_AA64MMFR4_EL1}}       // encoding: [0x89,0x07,0x38,0xd5]
 // CHECK: mrs      x9, {{sctlr_el1|SCTLR_EL1}}              // encoding: [0x09,0x10,0x38,0xd5]
 // CHECK: mrs      x9, {{sctlr_el2|SCTLR_EL2}}              // encoding: [0x09,0x10,0x3c,0xd5]
 // CHECK: mrs      x9, {{sctlr_el3|SCTLR_EL3}}              // encoding: [0x09,0x10,0x3e,0xd5]
 // CHECK: mrs      x9, {{actlr_el1|ACTLR_EL1}}              // encoding: [0x29,0x10,0x38,0xd5]
 // CHECK: mrs      x9, {{actlr_el2|ACTLR_EL2}}              // encoding: [0x29,0x10,0x3c,0xd5]
 // CHECK: mrs      x9, {{actlr_el3|ACTLR_EL3}}              // encoding: [0x29,0x10,0x3e,0xd5]
 // CHECK: mrs      x9, {{cpacr_el1|CPACR_EL1}}              // encoding: [0x49,0x10,0x38,0xd5]
 // CHECK: mrs      x9, {{hcr_el2|HCR_EL2}}                // encoding: [0x09,0x11,0x3c,0xd5]

llvm/test/MC/AArch64/directive-arch_extension-negative.s

 // RUN: not llvm-mc -triple aarch64 \
 // RUN: -mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm,+hbc,+mops \
-// RUN: -mattr=+rcpc3,+lse128,+d128,+the \
+// RUN: -mattr=+rcpc3,+lse128,+d128,+the,+rasv2 \
 // RUN: -filetype asm -o - %s 2>&1 | FileCheck %s
 
 .arch_extension axp64
 // CHECK: error: unknown architectural extension: axp64
 // CHECK-NEXT: .arch_extension axp64
 
 crc32cx w0, w1, x3
 // CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: crc

 // CHECK-NEXT: rcwcasp   x0, x1, x6, x7, [x4]
 
 rcwswp x0, x1, [x2]
 // CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: the
 .arch_extension nothe
 rcwswp x0, x1, [x2]
 // CHECK: [[@LINE-1]]:1: error: instruction requires: the
 // CHECK-NEXT: rcwswp x0, x1, [x2]
+
+mrs x0, ERXGSR_EL1
+// CHECK-NOT: [[@LINE-1]]:9: error: expected readable system register
+.arch_extension norasv2
+mrs x0, ERXGSR_EL1
+// CHECK: [[@LINE-1]]:9: error: expected readable system register
+// CHECK-NEXT: mrs x0, ERXGSR_EL1

llvm/test/MC/AArch64/directive-arch_extension.s

 
 // This needs to come after `.arch_extension the` as it uses an instruction that
 // requires both the and d128
 .arch_extension d128
 sysp #0, c2, c0, #0, x0, x1
 rcwcasp   x0, x1, x6, x7, [x4]
 // CHECK: sysp #0, c2, c0, #0, x0, x1
 // CHECK: rcwcasp   x0, x1, x6, x7, [x4]
+
+.arch_extension rasv2
+mrs x0, ERXGSR_EL1
+// CHECK: mrs x0, ERXGSR_EL1

llvm/test/MC/Disassembler/AArch64/armv8.9a-pfar.txt

+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s
+
+[0xa0,0x60,0x38,0xd5]
+# CHECK: mrs x0, PFAR_EL1
+
+[0xa0,0x60,0x18,0xd5]
+# CHECK: msr PFAR_EL1, x0
+
+[0xa0,0x60,0x3c,0xd5]
+# CHECK: mrs x0, PFAR_EL2
+
+[0xa0,0x60,0x1c,0xd5]
+# CHECK: msr PFAR_EL2, x0
+
+[0xa0,0x60,0x3d,0xd5]
+# CHECK: mrs x0, PFAR_EL12
+
+[0xa0,0x60,0x1d,0xd5]
+# CHECK: msr PFAR_EL12, x0
+
+[0xa0,0x60,0x3e,0xd5]
+# CHECK: mrs x0, MFAR_EL3
+
+[0xa0,0x60,0x1e,0xd5]
+# CHECK: msr MFAR_EL3, x0

llvm/test/MC/Disassembler/AArch64/armv8.9a-rasv2.txt

+# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+rasv2 < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+v8.9a < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+v9.4a < %s | FileCheck %s
+
+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s --check-prefix=NO-RAS
+
+[0x40,0x53,0x38,0xd5]
+# CHECK: mrs x0, ERXGSR_EL1
+# NO-RAS: mrs x0, S3_0_C5_C3_2
+
+[0x40,0x53,0x18,0xd5]
+# CHECK: msr S3_0_C5_C3_2, x0
+# NO-RAS: msr S3_0_C5_C3_2, x0

llvm/test/MC/Disassembler/AArch64/armv9a-rme.txt

 # RUN: llvm-mc -triple aarch64-arm-none-eabi -mattr +rme -disassemble %s 2>&1 | FileCheck %s
 # RUN: llvm-mc -triple aarch64-arm-none-eabi -disassemble %s 2>&1 | FileCheck --check-prefix=CHECK-NO-RME %s
 
 [0xa0,0x60,0x3e,0xd5]
 [0xc0,0x21,0x3e,0xd5]
 [0x80,0x21,0x3e,0xd5]
 # CHECK: mrs x0, MFAR_EL3
 # CHECK: mrs x0, GPCCR_EL3
 # CHECK: mrs x0, GPTBR_EL3
-# CHECK-NO-RME: mrs x0, S3_6_C6_C0_5
+# CHECK-NO-RME: mrs x0, MFAR_EL3
 # CHECK-NO-RME: mrs x0, S3_6_C2_C1_6
 # CHECK-NO-RME: mrs x0, S3_6_C2_C1_4
 
 [0x60,0x84,0x0e,0xd5]
 [0xe0,0x84,0x0e,0xd5]
 [0x9f,0x81,0x0e,0xd5]
 [0x9f,0x87,0x0e,0xd5]
 # CHECK: tlbi rpaos, x0
 # CHECK: tlbi rpalos, x0
 # CHECK: tlbi paallos
 # CHECK: tlbi paall
 # CHECK-NO-RME: sys #6, c8, c4, #3
 # CHECK-NO-RME: sys #6, c8, c4, #7
 # CHECK-NO-RME: sys #6, c8, c1, #4
-# CHECK-NO-RME: sys #6, c8, c7, #4
+# CHECK-NO-RME: sys #6, c8, c7, #4
 

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

 # CHECK: mrs      x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}
 # CHECK: mrs      x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}
 # CHECK: mrs      x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}
 # CHECK: mrs      x9, {{id_aa64isar2_el1|ID_AA64ISAR2_EL1}}
 # CHECK: mrs      x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}
 # CHECK: mrs      x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}
 # CHECK: mrs      x9, {{id_aa64mmfr2_el1|ID_AA64MMFR2_EL1}}
 # CHECK: mrs      x9, {{id_aa64mmfr3_el1|ID_AA64MMFR3_EL1}}
+# CHECK: mrs      x9, {{id_aa64mmfr4_el1|ID_AA64MMFR4_EL1}}
 # CHECK: mrs      x9, {{sctlr_el1|SCTLR_EL1}}
 # CHECK: mrs      x9, {{sctlr_el2|SCTLR_EL2}}
 # CHECK: mrs      x9, {{sctlr_el3|SCTLR_EL3}}
 # CHECK: mrs      x9, {{actlr_el1|ACTLR_EL1}}
 # CHECK: mrs      x9, {{actlr_el2|ACTLR_EL2}}
 # CHECK: mrs      x9, {{actlr_el3|ACTLR_EL3}}
 # CHECK: mrs      x9, {{cpacr_el1|CPACR_EL1}}
 # CHECK: mrs      x9, {{hcr_el2|HCR_EL2}}

 0xa9 0x5 0x38 0xd5
 0x9 0x6 0x38 0xd5
 0x29 0x6 0x38 0xd5
 0x49 0x06 0x38 0xd5
 0x9 0x7 0x38 0xd5
 0x29 0x7 0x38 0xd5
 0x49 0x7 0x38 0xd5
 0x69 0x7 0x38 0xd5
+0x89 0x7 0x38 0xd5
 0x9 0x10 0x38 0xd5
 0x9 0x10 0x3c 0xd5
 0x9 0x10 0x3e 0xd5
 0x29 0x10 0x38 0xd5
 0x29 0x10 0x3c 0xd5
 0x29 0x10 0x3e 0xd5
 0x49 0x10 0x38 0xd5
 0x9 0x11 0x3c 0xd5

llvm/unittests/Support/TargetParserTest.cpp

std::vector<uint64_t> Extensions = {
       AArch64::AEK_BF16,    AArch64::AEK_I8MM,      AArch64::AEK_F32MM,
       AArch64::AEK_F64MM,   AArch64::AEK_TME,       AArch64::AEK_LS64,
       AArch64::AEK_BRBE,    AArch64::AEK_PAUTH,     AArch64::AEK_FLAGM,
       AArch64::AEK_SME,     AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
       AArch64::AEK_SME2,    AArch64::AEK_HBC,       AArch64::AEK_MOPS,
       AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,    AArch64::AEK_SME2p1,
       AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
       AArch64::AEK_RCPC3,   AArch64::AEK_THE,       AArch64::AEK_D128,
-      AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,
+      AArch64::AEK_LSE128,  AArch64::AEK_SPECRES2,  AArch64::AEK_RASv2,
   };
 
   std::vector<StringRef> Features;
 
   uint64_t ExtVal = 0;
   for (auto Ext : Extensions)
     ExtVal |= Ext;
 
const char *ArchExt[][4] = {
       {"sme-i16i64", "nosme-i16i64", "+sme-i16i64", "-sme-i16i64"},
       {"sme-f16f16", "nosme-f16f16", "+sme-f16f16", "-sme-f16f16"},
       {"sme2", "nosme2", "+sme2", "-sme2"},
       {"sme2p1", "nosme2p1", "+sme2p1", "-sme2p1"},
       {"hbc", "nohbc", "+hbc", "-hbc"},
       {"mops", "nomops", "+mops", "-mops"},
       {"pmuv3", "nopmuv3", "+perfmon", "-perfmon"},
       {"predres2", "nopredres2", "+specres2", "-specres2"},
+      {"rasv2", "norasv2", "+rasv2", "-rasv2"},
   };
 
   for (unsigned i = 0; i < std::size(ArchExt); i++) {
     EXPECT_EQ(StringRef(ArchExt[i][2]),
               AArch64::getArchExtFeature(ArchExt[i][0]));
     EXPECT_EQ(StringRef(ArchExt[i][3]),
               AArch64::getArchExtFeature(ArchExt[i][1]));
   }
 }
 
 } // namespace