[PowerPC] Improve materialization for immediates which is almost a 32 bit splat.

[Esme]

Summary

Some 64 bit constants can be materialized with fewer instructions than we currently use.
We consider a 64 bit immediate value divided into four parts, Hi16OfHi32 (bits 48...63), Lo16OfHi32 (bits 32...47), Hi16OfLo32 (bits 16...31), Lo16OfLo32 (bits 0...15). When any three parts are equal, the immediate can be treated as "almost" a splat of a 32 bit value in a 64 bit register.
For example:

define  i64 @almost_splat() {
entry:
  ; 0xCCFFCCFF0123CCFF (Hi16OfHi32 == Lo16OfHi32 ==Lo16OfLo32)
  ret i64 14771750698406366463
}

Currently we use 5 instruction to materialize the immediate:

# %bb.0:                                # %entry
	lis 3, -13057
	ori 3, 3, 52479
	rldic 3, 3, 32, 0
	oris 3, 3, 291
	ori 3, 3, 52479
	blr

To improve that we can use 3 instructions to generate the splat and use 1 instruction to modify the different part:

# %bb.0:                                # %entry
	lis 3, 291
	ori 3, 3, 52479
	rldimi 3, 3, 32, 0       // 0x0123CCFF0123CCFF is generated here
	rldimi 3, 3, 48, 0       // modify Hi16OfHi32, then we get 0xCCFFCCFF0123CCFF
	blr

[shchenz]

llvm/test/CodeGen/PowerPC/constants-i64.ll

378

please commit the new cases first

[Esme]

Address comments.

[Esme]

ping

[shchenz]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1389

For compile time concern, since the 1 instruction patterns for Imm & 0xffffffff00000000 are simple, can we move the new code before line 1318 and do some simple check for 1 instruction pattern in selectI64ImmDirect?

1396

nit: there is a getI32Imm lambda at line 1314.

1412

I don't get the point here.
original input: 0xAAAABBBBAAAACCCC
splat result: 0XAAAABBBBAAAABBBB
after the ORI8: 0XAAAABBBBAAAABBBB | 0xCCCC != 0xAAAABBBBAAAACCCC ?

Seems another rldimi is needed to insert Lo16OfLo32 to the splat result.

[Esme]

Addressed comments and verified the materialization results.
However, I can't find a proper instruction to turn 0xABCD ADDD ABCD ADDD into 0xABCD ABCD ABCD ADDD, ie. modify Lo16OfHi32 (bits 32...47), so I didn't handle the pattern like 0xABCD ABCD ABCD ADDD.

[Esme]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1389

Sorry I didn't quite understand this comment.
Imm & 0xffffffff00000000 always takes more than 1 instruction because it is impossible to match the 1-instruction-pattern:

// 1-1) Patterns : {zeros}{15-bit valve}
//                 {ones}{15-bit valve}

// 1-2) Patterns : {zeros}{15-bit valve}{16 zeros}
//                 {ones}{15-bit valve}{16 zeros}

[shchenz]

In D139813#4034807, @Esme wrote:

Addressed comments and verified the materialization results.
However, I can't find a proper instruction to turn 0xABCD ADDD ABCD ADDD into 0xABCD ABCD ABCD ADDD, ie. modify Lo16OfHi32 (bits 32...47), so I didn't handle the pattern like 0xABCD ABCD ABCD ADDD.

Thanks, the new selection seems correct. For pattern 0xABCD ABCD ABCD ADDD, yeah, I can not find a 4 instruction selection for it either.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1389

I mean the new codes can be moved before line 1317 with some simple checks. For example if select Imm & 0xffffffff00000000 requires no less than 2 instructions and the lower 32 bit also requires 2 instructions, the new splat handling can be done first. Generating a 5 instruction pattern and then marking them as dead can be avoided even the new codes are hit.

[Esme]

Addressed comments.

[shchenz]

LGTM. Thanks for the improvement. Please wait for some days for other reviewers.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

static SDNode *selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm,
   if (Result) {
     if (InstCnt)
       *InstCnt = InstCntDirect;
     return Result;
   }
   auto getI32Imm = [CurDAG, dl](unsigned Imm) {
     return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
   };
+
+  uint32_t Hi16OfLo32 = (Lo_32(Imm) >> 16) & 0xffff;
+  uint32_t Lo16OfLo32 = Lo_32(Imm) & 0xffff;
+
+  // Try to use 4 instructions to materialize the immediate which is "almost" a
+  // splat of a 32 bit immediate.
+  if (Hi16OfLo32 && Lo16OfLo32) {
+    uint32_t Hi16OfHi32 = (Hi_32(Imm) >> 16) & 0xffff;
+    uint32_t Lo16OfHi32 = Hi_32(Imm) & 0xffff;
+    bool IsSelected = false;
+
+    auto getSplat = [CurDAG, dl, getI32Imm](uint32_t Hi16, uint32_t Lo16) {
+      SDNode *Result =
+          CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi16));
+      Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
+                                      SDValue(Result, 0), getI32Imm(Lo16));
+      SDValue Ops[] = {SDValue(Result, 0), SDValue(Result, 0), getI32Imm(32),
+                       getI32Imm(0)};
+      return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
+    };
+
+    if (Hi16OfHi32 == Lo16OfHi32 && Lo16OfHi32 == Lo16OfLo32) {
+      IsSelected = true;
+      Result = getSplat(Hi16OfLo32, Lo16OfLo32);
+      // Modify Hi16OfHi32.
+      SDValue Ops[] = {SDValue(Result, 0), SDValue(Result, 0), getI32Imm(48),
+                       getI32Imm(0)};
+      Result = CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
+    } else if (Hi16OfHi32 == Hi16OfLo32 && Hi16OfLo32 == Lo16OfLo32) {
+      IsSelected = true;
+      Result = getSplat(Hi16OfHi32, Lo16OfHi32);
+      // Modify Lo16OfLo32.
+      SDValue Ops[] = {SDValue(Result, 0), SDValue(Result, 0), getI32Imm(16),
+                       getI32Imm(16), getI32Imm(31)};
+      Result = CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64, Ops);
+    } else if (Lo16OfHi32 == Lo16OfLo32 && Hi16OfLo32 == Lo16OfLo32) {
+      IsSelected = true;
+      Result = getSplat(Hi16OfHi32, Lo16OfHi32);
+      // Modify Hi16OfLo32.
+      SDValue Ops[] = {SDValue(Result, 0), SDValue(Result, 0), getI32Imm(16),
+                       getI32Imm(0), getI32Imm(15)};
+      Result = CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64, Ops);
+    }
+    if (IsSelected == true) {
+      if (InstCnt)
+        *InstCnt = 4;
+      return Result;
+    }
+  }
+
   // Handle the upper 32 bit value.
   Result =
       selectI64ImmDirect(CurDAG, dl, Imm & 0xffffffff00000000, InstCntDirect);
   // Add in the last bits as required.
-  if (uint32_t Hi16 = (Lo_32(Imm) >> 16) & 0xffff) {
+  if (Hi16OfLo32) {
     Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
-                                    SDValue(Result, 0), getI32Imm(Hi16));
+                                    SDValue(Result, 0), getI32Imm(Hi16OfLo32));
     ++InstCntDirect;
   }
-  if (uint32_t Lo16 = Lo_32(Imm) & 0xffff) {
+  if (Lo16OfLo32) {
     Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
-                                    getI32Imm(Lo16));
+                                    getI32Imm(Lo16OfLo32));
     ++InstCntDirect;
   }
   if (InstCnt)
     *InstCnt = InstCntDirect;
   return Result;
 }
 
 // Select a 64-bit constant.
 static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) {
   SDLoc dl(N);
 
   // Get 64 bit value.
   int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
   if (unsigned MinSize = allUsesTruncate(CurDAG, N)) {
     uint64_t SextImm = SignExtend64(Imm, MinSize);
     SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
     if (isInt<16>(SextImm))
       return CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
   }
   return selectI64Imm(CurDAG, dl, Imm);
 }
 
 namespace {
 
 class BitPermutationSelector {
   struct ValueBit {
     SDValue V;
 
     // The bit number in the value, using a convention where bit 0 is the
     // lowest-order bit.
     unsigned Idx;
 
     // ConstZero means a bit we need to mask off.
     // Variable is a bit comes from an input variable.
     // VariableKnownToBeZero is also a bit comes from an input variable,
     // but it is known to be already zero. So we do not need to mask them.
     enum Kind {

llvm/test/CodeGen/PowerPC/constants-i64.ll

 ; CHECK-NEXT:    rldic 3, 3, 33, 30
 ; CHECK-NEXT:    oris 3, 3, 39436
 ; CHECK-NEXT:    ori 3, 3, 61633
 ; CHECK-NEXT:    blr
 entry:
   ret i64 11174473921
 }
 
 define i64 @imm19() {
 ; CHECK-LABEL: imm19:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:  lis 3, -13105
 ; CHECK-NEXT:  ori 3, 3, 52479
 ; CHECK-NEXT:  rldic 3, 3, 32, 0
 ; CHECK-NEXT:  oris 3, 3, 52431
 ; CHECK-NEXT:  ori 3, 3, 291
 ; CHECK-NEXT:  blr
 entry:
   ret i64 14758239902941249827 ;0xCCCFCCFFCCCF0123
 }
 
 define i64 @imm20() {
 ; CHECK-LABEL: imm20:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:  lis 3, -13057
-; CHECK-NEXT:  ori 3, 3, 52479
-; CHECK-NEXT:  rldic 3, 3, 32, 0
-; CHECK-NEXT:  oris 3, 3, 291
+; CHECK-NEXT:  lis 3, 291
 ; CHECK-NEXT:  ori 3, 3, 52479
+; CHECK-NEXT:  rldimi 3, 3, 32, 0
+; CHECK-NEXT:  rldimi 3, 3, 48, 0
 ; CHECK-NEXT:  blr
 entry:
   ret i64 14771750698406366463 ;0xCCFFCCFF0123CCFF
 }
 
+define i64 @imm21() {
+; CHECK-LABEL: imm21:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  lis 3, -13057
+; CHECK-NEXT:  ori 3, 3, 291
+; CHECK-NEXT:  rldimi 3, 3, 32, 0
+; CHECK-NEXT:  rlwimi 3, 3, 16, 16, 31
+; CHECK-NEXT:  blr
+entry:
+  ret i64 14771526556073315583 ;0xCCFF0123CCFFCCFF
+}
+
+define i64 @imm22() {
+; CHECK-LABEL: imm22:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  lis 3, 291
+; CHECK-NEXT:  ori 3, 3, 52479
+; CHECK-NEXT:  rldimi 3, 3, 32, 0
+; CHECK-NEXT:  rlwimi 3, 3, 16, 0, 15
+; CHECK-NEXT:  blr
+entry:
+  ret i64 82134617250843903 ;0x0123CCFFCCFFCCFF
+}
+
 attributes #0 = { nounwind readnone }