[AMDGPU] Enable OMod on more VOP3 instructions

[Joe_Nash]

Summary

OMod was disabled if OpSel was enabled, but that restriction is more
specific than necessary. Any VOP3 with float operands can use OMod.

On GFX11, FMAC_F16_e64 can use op_sel.
Previously, SIFoldOperands and convertToThreeAddress were accidentally correct when
they reinterpreted the zero OMod operand on V_FMAC_F16_e64 as the OpSel operand on
V_FMA_F16_gfx9_e64. Now we explicitly add op_sel if required.

[foad]

llvm/test/CodeGen/AMDGPU/omod.ll

4

Can you precommit this part?

[Joe_Nash]

llvm/test/CodeGen/AMDGPU/omod.ll

4

c6c4f54e6bf71b9e35a25c36d7c8ae59b636f3cc

[Joe_Nash]

precommit gfx11 runline and rebase

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

 //===-- SIFoldOperands.cpp - Fold operands --- ----------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 /// \file
 //===----------------------------------------------------------------------===//
 //
 
 #include "AMDGPU.h"
 #include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIMachineFunctionInfo.h"
 #include "llvm/ADT/DepthFirstIterator.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineOperand.h"
 
 #define DEBUG_TYPE "si-fold-operands"
 using namespace llvm;
 
 namespace {
 
 struct FoldCandidate {
   MachineInstr *UseMI;
bool SIFoldOperands::tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
   if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
     // Special case for v_mac_{f16, f32}_e64 if we are trying to fold into src2
     unsigned Opc = MI->getOpcode();
     unsigned NewOpc = macToMad(Opc);
     if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
       // Check if changing this to a v_mad_{f16, f32} instruction will allow us
       // to fold the operand.
       MI->setDesc(TII->get(NewOpc));
+      if (!AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel) &&
+          AMDGPU::hasNamedOperand(NewOpc, AMDGPU::OpName::op_sel))
+        MI->addOperand(MachineOperand::CreateImm(0));
       bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold);
       if (FoldAsMAD) {
         MI->untieRegOperand(OpNo);
         return true;
       }
       MI->setDesc(TII->get(Opc));
     }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
   const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
   const MachineOperand *Src1Mods =
     getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
   const MachineOperand *Src2Mods =
       getNamedOperand(MI, AMDGPU::OpName::src2_modifiers);
   const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
   const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
+  const MachineOperand *OpSel = getNamedOperand(MI, AMDGPU::OpName::op_sel);
 
   if (!Src0Mods && !Src1Mods && !Src2Mods && !Clamp && !Omod && !IsF64 &&
       !IsLegacy &&
       // If we have an SGPR input, we will violate the constant bus restriction.
       (ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
        !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
     MachineInstr *DefMI;
     const auto killDef = [&]() -> void {
MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
             .addImm(Src0Mods ? Src0Mods->getImm() : 0)
             .add(*Src0)
             .addImm(Src1Mods ? Src1Mods->getImm() : 0)
             .add(*Src1)
             .addImm(Src2Mods ? Src2Mods->getImm() : 0)
             .add(*Src2)
             .addImm(Clamp ? Clamp->getImm() : 0)
             .addImm(Omod ? Omod->getImm() : 0);
+  if (AMDGPU::hasNamedOperand(NewOpc, AMDGPU::OpName::op_sel))
+    MIB.addImm(OpSel ? OpSel->getImm() : 0);
   updateLiveVariables(LV, MI, *MIB);
   if (LIS)
     LIS->ReplaceMachineInstrInMaps(MI, *MIB);
   return MIB;
 }
 
 // It's not generally safe to move VALU instructions across these since it will
 // start using the register as a base index rather than directly.

llvm/lib/Target/AMDGPU/SIInstrInfo.td

class getAsmVOP3P <int NumSrcArgs, bit HasModifiers,
 
   // Each modifier is printed as an array of bits for each operand, so
   // all operands are printed as part of src0_modifiers.
   string ret = dst#", "#src0#src1#src2#opsel#mods#clamp;
 }
 
 class getAsmVOP3OpSel <int NumSrcArgs,
                        bit HasClamp,
+                       bit HasOMod,
                        bit Src0HasMods,
                        bit Src1HasMods,
                        bit Src2HasMods> {
   string dst = "$vdst";
 
   string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
   string isrc1 = !if(!eq(NumSrcArgs, 1), "",
                      !if(!eq(NumSrcArgs, 2), " $src1",
                                              " $src1,"));
   string isrc2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
 
   string fsrc0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
   string fsrc1 = !if(!eq(NumSrcArgs, 1), "",
                      !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
                                              " $src1_modifiers,"));
   string fsrc2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
 
   string src0 = !if(Src0HasMods, fsrc0, isrc0);
   string src1 = !if(Src1HasMods, fsrc1, isrc1);
   string src2 = !if(Src2HasMods, fsrc2, isrc2);
 
   string clamp = !if(HasClamp, "$clamp", "");
-  string omod = "";
+  string omod = !if(HasOMod, "$omod", "");
   string ret = dst#", "#src0#src1#src2#"$op_sel"#clamp#omod;
 }
 
 class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
   string dst = !if(HasDst,
                    !if(!eq(DstVT.Size, 1),
                        "$sdst",
                        "$vdst"),
class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
   field Operand Src2ModDPP = getSrcModDPP<Src2VT>.ret;
   field Operand Src0ModVOP3DPP = getSrcModDPP<Src0VT>.ret;
   field Operand Src1ModVOP3DPP = getSrcModDPP<Src1VT>.ret;
   field Operand Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT>.ret;
   field Operand Src0ModSDWA = getSrcModSDWA<Src0VT>.ret;
   field Operand Src1ModSDWA = getSrcModSDWA<Src1VT>.ret;
 
 
+  field bit IsMAI = 0;
+  field bit IsVOP3P = 0;
+  field bit IsDOT = 0;
+  field bit IsSingle = 0;
+  field bit IsWMMA = 0;
+
   field bit HasDst = !ne(DstVT.Value, untyped.Value);
   field bit HasDst32 = HasDst;
   field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case
   field bit EmitDstSel = EmitDst;
   field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
   field bit HasSrc0 = !ne(Src0VT.Value, untyped.Value);
   field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value);
   field bit HasSrc2 = !ne(Src2VT.Value, untyped.Value);
class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
   field bit HasFPClamp = !and(isFloatType<DstVT>.ret, HasClamp);
   field bit HasIntClamp = !if(isFloatType<DstVT>.ret, 0, HasClamp);
   field bit HasClampLo = HasClamp;
   field bit HasClampHi = !and(isPackedType<DstVT>.ret, HasClamp);
   field bit HasHigh = 0;
 
   field bit IsPacked = isPackedType<Src0VT>.ret;
   field bit HasOpSel = IsPacked;
-  field bit HasOMod = !if(HasOpSel, 0, isFloatType<DstVT>.ret);
+  field bit HasOMod = !if(IsVOP3P, 0, isFloatType<DstVT>.ret);
   field bit HasSDWAOMod = isFloatType<DstVT>.ret;
 
   field bit HasModifiers = !or(isModifierType<Src0VT>.ret,
                                isModifierType<Src1VT>.ret,
                                isModifierType<Src2VT>.ret,
                                HasOMod);
 
   field bit HasSrc0Mods = HasModifiers;
   field bit HasSrc1Mods = !if(HasModifiers, !or(HasSrc1FloatMods, HasSrc1IntMods), 0);
   field bit HasSrc2Mods = !if(HasModifiers, !or(HasSrc2FloatMods, HasSrc2IntMods), 0);
 
   field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
   field bit HasExtVOP3DPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
   field bit HasExtDPP = !if(!or(getHasDPP<NumSrcArgs>.ret,
                 HasExtVOP3DPP), 1, 0);
   field bit HasExt32BitDPP = getHasExt32BitDPP<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
   field bit HasExt64BitDPP = getHasExt64BitDPP<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
   field bit HasExtSDWA = getHasSDWA<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
   field bit HasExtSDWA9 = HasExtSDWA;
   field int NeedPatGen = PatGenMode.NoPattern;
 
-  field bit IsMAI = 0;
-  field bit IsVOP3P = 0;
-  field bit IsDOT = 0;
-  field bit IsSingle = 0;
-  field bit IsWMMA = 0;
-
   field Operand Src0PackedMod = !if(HasSrc0FloatMods, PackedF16InputMods, PackedI16InputMods);
   field Operand Src1PackedMod = !if(HasSrc1FloatMods, PackedF16InputMods, PackedI16InputMods);
   field Operand Src2PackedMod = !if(HasSrc2FloatMods, PackedF16InputMods, PackedI16InputMods);
 
   field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
 
   // VOP3b instructions are a special case with a second explicit
   // output. This is manually overridden for them.
class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
   field dag InsVOPDYDeferred = (ins !if(!eq(Src1VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0Y, VGPR_32:$vsrc1Y);
 
 
   field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
   field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasIntClamp, HasModifiers, HasOMod, DstVT>.ret;
   field string AsmVOP3P = getAsmVOP3P<NumSrcArgs, HasModifiers, HasClamp, HasOpSel>.ret;
   field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
                                               HasClamp,
+                                              HasOMod,
                                               HasSrc0FloatMods,
                                               HasSrc1FloatMods,
                                               HasSrc2FloatMods>.ret;
   field string AsmDPP = !if(HasExtDPP,
                             getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret, "");
   field string AsmDPP16 = getAsmDPP16<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
   // DPP8 encoding has no fields for modifiers, and it is enforced by setting
   // the asm operand name via this HasModifiers flag

llvm/lib/Target/AMDGPU/VOP2Instructions.td

let Ins64 = getIns64<Src0RC64, Src1RC64, getRegisterOperandForVT<Src2VT>.ret, 3,
                        0, HasModifiers, HasModifiers, HasOMod,
                        Src0Mod, Src1Mod, Src2Mod>.ret;
   let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
                     getVregSrcForVT<Src2VT>.ret:$src2, // stub argument
                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
   let InsDPP16 = !con(InsDPP, (ins FI:$fi));
-  let InsVOP3Base = getIns64<Src0VOP3DPP, Src1VOP3DPP, RegisterOperand<VGPR_32>, 3,
+  let InsVOP3Base = getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP, RegisterOperand<VGPR_32>, 3,
                        0, HasModifiers, HasModifiers, HasOMod,
-                       Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod>.ret;
+                       Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod, HasOpSel, 0/*IsVOP3P*/>.ret;
   // We need a dummy src2 tied to dst to track the use of that register for s_delay_alu
   let InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X, VGPRSrc_32:$src2X);
   let InsVOPDXDeferred =
     (ins !if(!eq(Src0VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0X,
          VGPR_32:$vsrc1X, VGPRSrc_32:$src2X);
   let InsVOPDY = (ins Src0RC32:$src0Y, Src1RC32:$vsrc1Y, VGPRSrc_32:$src2Y);
   let InsVOPDYDeferred =
     (ins !if(!eq(Src1VT.Size, 32), VSrc_f32_Deferred, VSrc_f16_Deferred):$src0Y,
class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {
   let HasExtSDWA = 1;
   let HasExtSDWA9 = 0;
   let TieRegDPP = "$src2";
 }
 
 def VOP_MAC_F16 : VOP_MAC <f16>;
 def VOP_MAC_F16_t16 : VOP_MAC <f16> {
   let IsTrue16 = 1;
+  let HasOpSel = 1;
+  let AsmVOP3OpSel = getAsmVOP3OpSel<2/*NumSrcArgs*/, HasClamp, HasOMod,
+                        HasSrc0FloatMods, HasSrc1FloatMods, HasSrc2FloatMods>.ret;
   let DstRC = VOPDstOperand<VGPR_32_Lo128>;
   let DstRC64 = VOPDstOperand<VGPR_32>;
   let Src1RC32 = VGPRSrc_32_Lo128;
   let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT_t16<Src2VT>.ret:$src2);
   let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret;
   let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret;
   let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret;
   let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;

llvm/lib/Target/AMDGPU/VOP3Instructions.td

def VOP3_CVT_SR_F8_F32_Profile : VOP3_Profile<VOPProfile<[i32, f32, i32, f32]>,
   let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0,
                           FP32InputMods:$src1_modifiers, Src1RC64:$src1,
                           FP32InputMods:$src2_modifiers, VGPR_32:$src2,
                           op_sel0:$op_sel);
   let HasClamp = 0;
   let HasSrc2 = 0;
   let HasSrc2Mods = 1;
   let AsmVOP3OpSel = !subst(", $src2_modifiers", "",
-                            getAsmVOP3OpSel<3, HasClamp,
+                            getAsmVOP3OpSel<3, HasClamp, HasOMod,
                                             HasSrc0FloatMods, HasSrc1FloatMods,
                                             HasSrc2FloatMods>.ret);
   let HasExtVOP3DPP = 0;
 }
 
 let SubtargetPredicate = isGFX9Plus in {
 let isCommutable = 1, isReMaterializable = 1 in {
   defm V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
class VOP3_DOT_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOP3_Profile<P, Features> {
   let HasSrc1Mods = 1;
   let HasSrc2Mods = 1;
   let Src0ModVOP3DPP = FPVRegInputMods;
   let Src1ModVOP3DPP = FPVRegInputMods;
   let Src2ModVOP3DPP = FP16InputMods;
   let InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
                                      HasClamp, HasOMod, FP16InputMods,
                                      FP16InputMods, FP16InputMods>.ret;
-  let AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs, HasClamp, 1, 1, 1>.ret;
+  let AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs, HasClamp, HasOMod, 1, 1, 1>.ret;
 }
 
 let SubtargetPredicate = isGFX11Plus in {
   defm V_MAXMIN_F32     : VOP3Inst<"v_maxmin_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
   defm V_MINMAX_F32     : VOP3Inst<"v_minmax_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
   defm V_MAXMIN_F16     : VOP3Inst<"v_maxmin_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;
   defm V_MINMAX_F16     : VOP3Inst<"v_minmax_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;
   defm V_MAXMIN_U32     : VOP3Inst<"v_maxmin_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir

body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GCN-LABEL: name: fmed3_s16_vvvv
     ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
-    ; GCN: %6:vgpr_32 = nofpexcept V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
+    ; GCN: %6:vgpr_32 = nofpexcept V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
     ; GCN: S_ENDPGM 0, implicit %6
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s32) = COPY $vgpr2
     %3:vgpr(s16) = G_TRUNC %0
     %4:vgpr(s16) = G_TRUNC %1
     %5:vgpr(s16) = G_TRUNC %2
     %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
body: |
   bb.0:
     liveins: $sgpr0, $vgpr0, $vgpr1
 
     ; GCN-LABEL: name: fmed3_s16_vsvv
     ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-    ; GCN: %6:vgpr_32 = nofpexcept V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
+    ; GCN: %6:vgpr_32 = nofpexcept V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
     ; GCN: S_ENDPGM 0, implicit %6
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s32) = COPY $vgpr0
     %2:vgpr(s32) = COPY $vgpr1
     %3:sgpr(s16) = G_TRUNC %0
     %4:vgpr(s16) = G_TRUNC %1
     %5:vgpr(s16) = G_TRUNC %2
     %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
     S_ENDPGM 0, implicit %6
 ...

llvm/test/CodeGen/AMDGPU/commute-vop3.mir

bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
     ; GFX9-LABEL: name: commute_vop3
     ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
     ; GFX9-NEXT: [[V_XOR3_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR3_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
-    ; GFX9-NEXT: [[V_MED3_F16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
-    ; GFX9-NEXT: [[V_MED3_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MED3_F16_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
+    ; GFX9-NEXT: [[V_MED3_F16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
+    ; GFX9-NEXT: [[V_MED3_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MED3_F16_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
     ; GFX9-NEXT: [[V_MAX3_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX3_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
     ; GFX9-NEXT: [[V_SAD_HI_U8_e64_:%[0-9]+]]:vgpr_32 = V_SAD_HI_U8_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec
     ; GFX9-NEXT: [[V_XAD_U32_e64_:%[0-9]+]]:vgpr_32 = V_XAD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
     ; GFX9-NEXT: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
     ; GFX9-NEXT: [[V_SUB_I32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_I32_e64 [[COPY1]], [[COPY]], 0, implicit $exec
     ; GFX10-LABEL: name: commute_vop3
     ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
     ; GFX10-NEXT: [[V_XOR3_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR3_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
-    ; GFX10-NEXT: [[V_MED3_F16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
-    ; GFX10-NEXT: [[V_MED3_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MED3_F16_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
+    ; GFX10-NEXT: [[V_MED3_F16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
+    ; GFX10-NEXT: [[V_MED3_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MED3_F16_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
     ; GFX10-NEXT: [[V_MAX3_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX3_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
     ; GFX10-NEXT: [[V_SAD_HI_U8_e64_:%[0-9]+]]:vgpr_32 = V_SAD_HI_U8_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec
     ; GFX10-NEXT: [[V_XAD_U32_e64_:%[0-9]+]]:vgpr_32 = V_XAD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
     ; GFX10-NEXT: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
     ; GFX10-NEXT: [[V_SUB_I32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_I32_e64 [[COPY1]], [[COPY]], 0, implicit $exec
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = COPY $vgpr2
     %3:vgpr_32 = V_XOR3_B32_e64 %0, %1, %2, implicit $exec
     %4:vgpr_32 = V_XOR3_B32_e64 %1, %0, %2, implicit $exec
     ; Insts with MayRaiseFPException do not get CSE
-    %5:vgpr_32 = V_MED3_F16_e64 0, %0, 0, %1, 0, %2, 0, 0, implicit $mode, implicit $exec
-    %6:vgpr_32 = V_MED3_F16_e64 0, %1, 0, %0, 0, %2, 0, 0, implicit $mode, implicit $exec
+    %5:vgpr_32 = V_MED3_F16_e64 0, %0, 0, %1, 0, %2, 0, 0, 0, implicit $mode, implicit $exec
+    %6:vgpr_32 = V_MED3_F16_e64 0, %1, 0, %0, 0, %2, 0, 0, 0, implicit $mode, implicit $exec
 
     %7:vgpr_32 = V_MAX3_I32_e64 %0, %1, %2, implicit $exec
     %8:vgpr_32 = V_MAX3_I32_e64 %1, %0, %2, implicit $exec
     %11:vgpr_32 = V_SAD_HI_U8_e64 %0, %1, %2, 0, implicit $exec
     %12:vgpr_32 = V_SAD_HI_U8_e64 %1, %0, %2, 0, implicit $exec
     %13:vgpr_32 = V_XAD_U32_e64 %0, %1, 0, implicit $exec
     %14:vgpr_32 = V_XAD_U32_e64 %1, %0, 0, implicit $exec
     ; Sub should not be commuted
     %15:vgpr_32 = V_SUB_I32_e64 %0, %1, 0, implicit $exec
     %16:vgpr_32 = V_SUB_I32_e64 %1, %0, 0, implicit $exec
 ...

llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll

 ; XUN: llc -mtriple=amdgcn-amd-amdhsa -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,SIVI,VI-DENORM %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,SIVI,VI-FLUSH %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX8_10,GFX10-DENORM %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX8_10,GFX10-FLUSH %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX8_10,GFX10-DENORM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX8_10,GFX11-DENORM %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX8_10,GFX10-FLUSH %s
 
 ; Make sure (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c)) doesn't
 ; make add an instruction if the fadd has more than one use.
 
 declare half @llvm.fabs.f16(half) #1
 declare float @llvm.fabs.f32(float) #1
 

 ; GFX8_10:      v_add_f16_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
 ; GFX8_10:      v_cmp_gt_f16_e64 {{vcc|vcc_lo}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
 ; GFX8_10:      v_cndmask_b32_e32
 ; GFX8_10:      v_add_f16_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
 ; GFX8_10:      v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; VI-FLUSH:     v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
 ; VI-DENORM:    v_fma_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
 ; GFX10-DENORM: v_fma_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
+; GFX11-DENORM: v_fma_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, 1.0
 ; GFX10-FLUSH:  v_sub_f16_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
 define amdgpu_kernel void @multiple_fadd_use_test_f16(ptr addrspace(1) %out, i16 zeroext %x.arg, i16 zeroext %y.arg, i16 zeroext %z.arg) #0 {
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %z = bitcast i16 %z.arg to half
   %a11 = fadd half %y, -1.0
   %a12 = call half @llvm.fabs.f16(half %a11)
   %a13 = fadd half %x, -1.0

 
 ; GCN-LABEL: {{^}}multiple_use_fadd_fmac_f16:
 ; GCN-DAG: v_add_f16_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
 
 ; VI-FLUSH-DAG:     v_mac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0
 ; VI-DENORM-DAG:    v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, v{{[0-9]+}}
 ; GFX10-FLUSH-DAG:  v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
 ; GFX10-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], [[X]], 2.0, s{{[0-9]+}}
+; GFX11-DENORM-DAG: v_fmac_f16_e64 [[MAD:v[0-9]+]], [[X]], 2.0
 
 ; GCN-DAG: buffer_store_{{short|b16}} [[MUL2]]
 ; GCN-DAG: buffer_store_{{short|b16}} [[MAD]]
 ; GCN: s_endpgm
 define amdgpu_kernel void @multiple_use_fadd_fmac_f16(ptr addrspace(1) %out, i16 zeroext %x.arg, i16 zeroext %y.arg) #0 {
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1
   %mul2 = fmul fast half %x, 2.0
   %mad = fadd fast half %mul2, %y
   store volatile half %mul2, ptr addrspace(1) %out
   store volatile half %mad, ptr addrspace(1) %out.gep.1
   ret void
 }
 
 ; GCN-LABEL: {{^}}multiple_use_fadd_fmad_f16:
 ; GCN-DAG: v_add_f16_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
 
 ; VI-FLUSH-DAG:     v_mad_f16 [[MAD:v[0-9]+]], |[[X]]|, 2.0, v{{[0-9]+}}
 ; VI-DENORM-DAG:    v_fma_f16 [[MAD:v[0-9]+]], |[[X]]|, 2.0, v{{[0-9]+}}
 ; GFX10-FLUSH-DAG:  v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
 ; GFX10-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], |[[X]]|, 2.0, s{{[0-9]+}}
+; GFX11-DENORM-DAG: v_fma_f16 [[MAD:v[0-9]+]], |[[X]]|, 2.0, s{{[0-9]+}}
 
 ; GCN-DAG: buffer_store_{{short|b16}} [[MUL2]]
 ; GCN-DAG: buffer_store_{{short|b16}} [[MAD]]
 ; GCN: s_endpgm
 define amdgpu_kernel void @multiple_use_fadd_fmad_f16(ptr addrspace(1) %out, i16 zeroext %x.arg, i16 zeroext %y.arg) #0 {
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1

 
 ; VI-DENORM: v_fma_f16 {{v[0-9]+}}, |[[X:s[0-9]+]]|, 2.0, v{{[0-9]+}}
 ; VI-DENORM: v_fma_f16 {{v[0-9]+}}, |[[X]]|, 2.0, v{{[0-9]+}}
 
 ; GFX10-FLUSH:  v_add_f16_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |{{s[0-9]+}}|
 ; GFX10-FLUSH:  v_add_f16_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[MUL2]]
 ; GFX10-FLUSH:  v_add_f16_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[MUL2]]
 ; GFX10-DENORM: v_fma_f16 {{v[0-9]+}}, |[[X:s[0-9]+]]|, 2.0, s{{[0-9]+}}
+; GFX11-DENORM: v_fma_f16 {{v[0-9]+}}, |[[X:s[0-9]+]]|, 2.0, s{{[0-9]+}}
 ; GFX10-DENORM: v_fma_f16 {{v[0-9]+}}, |[[X]]|, 2.0, s{{[0-9]+}}
+; GFX11-DENORM: v_fma_f16 {{v[0-9]+}}, |[[X]]|, 2.0, s{{[0-9]+}}
 
 define amdgpu_kernel void @multiple_use_fadd_multi_fmad_f16(ptr addrspace(1) %out, i16 zeroext %x.arg, i16 zeroext %y.arg, i16 zeroext %z.arg) #0 {
   %x = bitcast i16 %x.arg to half
   %y = bitcast i16 %y.arg to half
   %z = bitcast i16 %z.arg to half
   %out.gep.1 = getelementptr half, ptr addrspace(1) %out, i32 1
   %x.abs = call half @llvm.fabs.f16(half %x)
   %mul2 = fmul fast half %x.abs, 2.0

llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir

 body:             |
   bb.0:
 
     ; GFX11-LABEL: name: test_fmamk_reg_imm_f16
     ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
     ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
     ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
-    ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, killed [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, killed [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
     %0 = IMPLICIT_DEF
     %1 = COPY %0.sub1
     %2 = COPY %0.sub0
     %3 = V_MOV_B32_e32 1078523331, implicit $exec
-    %4 = V_FMAC_F16_t16_e64 0, killed %2, 0, %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec
+    %4 = V_FMAC_F16_t16_e64 0, killed %2, 0, %3, 0, killed %1, 0, 0, 0, implicit $mode, implicit $exec
 
 ...
 
 ---
 name:            test_fmamk_imm_reg_f16
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
   - { id: 4, class: vgpr_32 }
 body:             |
   bb.0:
 
     ; GFX11-LABEL: name: test_fmamk_imm_reg_f16
     ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
     ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
     ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
-    ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, [[COPY1]], 0, killed [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, [[COPY1]], 0, killed [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
     %0 = IMPLICIT_DEF
     %1 = COPY %0.sub1
     %2 = COPY %0.sub0
     %3 = V_MOV_B32_e32 1078523331, implicit $exec
-    %4 = V_FMAC_F16_t16_e64 0, %2, 0, killed %3, 0, killed %1, 0, 0, implicit $mode, implicit $exec
+    %4 = V_FMAC_F16_t16_e64 0, %2, 0, killed %3, 0, killed %1, 0, 0, 0, implicit $mode, implicit $exec
 
 ...
 
 ---
 name:            test_fmaak_f16
 registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: vgpr_32 }
   - { id: 4, class: vgpr_32 }
 body:             |
   bb.0:
 
     ; GFX11-LABEL: name: test_fmaak_f16
     ; GFX11: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
     ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
     ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
-    ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec
     %0 = IMPLICIT_DEF
     %1 = COPY %0.sub0
     %2 = COPY %0.sub1
     %3 = V_MOV_B32_e32 1078523331, implicit $exec
-    %4 = V_FMAC_F16_t16_e64 0, killed %1, 0, %2, 0, %3, 0, 0, implicit $mode, implicit $exec
+    %4 = V_FMAC_F16_t16_e64 0, killed %1, 0, %2, 0, %3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 
 ---
 name:            test_fmaak_inline_literal_f16
 tracksRegLiveness: true
 liveins:
   - { reg: '$vgpr0', virtual-reg: '%0' }
 body:             |
   bb.0:
     liveins: $vgpr0
 
     ; GFX11-LABEL: name: test_fmaak_inline_literal_f16
     ; GFX11: liveins: $vgpr0
     ; GFX11-NEXT: {{  $}}
     ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
     ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
-    ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec
+    ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec
     ; GFX11-NEXT: S_ENDPGM 0
     %0:vgpr_32 = COPY killed $vgpr0
 
     %1:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
-    %2:vgpr_32 = V_FMAC_F16_t16_e64 0, 16384, 0, killed %0, 0, %1, 0, 0, implicit $mode, implicit $exec
+    %2:vgpr_32 = V_FMAC_F16_t16_e64 0, 16384, 0, killed %0, 0, %1, 0, 0, 0, implicit $mode, implicit $exec
     S_ENDPGM 0
 
 ...
 

llvm/test/CodeGen/AMDGPU/omod.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefixes=SI %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefixes=VI %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s
 
 ; IEEE bit enabled for compute kernel, so shouldn't use.
 define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_signed_zeros(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #4 {
 ; SI-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, 0

 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
   %add = fadd float %a, 1.0
   %div2 = fmul float %add, 2.0
   store float %div2, ptr addrspace(1) undef
   ret void
 }
 
+define amdgpu_ps void @v_omod_mul2_med3(float %x, float %y, float %z) #0 {
+; SI-LABEL: v_omod_mul2_med3:
+; SI:       ; %bb.0:
+; SI-NEXT:    v_med3_f32 v0, v0, v1, v2 mul:2
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT:    s_endpgm
+;
+; VI-LABEL: v_omod_mul2_med3:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_med3_f32 v0, v0, v1, v2 mul:2
+; VI-NEXT:    flat_store_dword v[0:1], v0
+; VI-NEXT:    s_endpgm
+;
+; GFX11-LABEL: v_omod_mul2_med3:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_med3_f32 v0, v0, v1, v2 mul:2
+; GFX11-NEXT:    global_store_b32 v[0:1], v0, off
+; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT:    s_endpgm
+  %fmed3 = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float %z)
+  %div2 = fmul float %fmed3, 2.0
+  store float %div2, float addrspace(1)* undef
+  ret void
+}
+
 define amdgpu_ps void @v_omod_mul2_f64(double %a) #5 {
 ; SI-LABEL: v_omod_mul2_f64:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    v_add_f64 v[0:1], v[0:1], 1.0 mul:2
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm

llvm/test/CodeGen/AMDGPU/shrink-mad-fma.mir

bb.0:
     ; GFX10-NEXT: SI_RETURN implicit $vgpr2
     ; GFX11-LABEL: name: fma_cvv_f16
     ; GFX11: $vgpr0 = IMPLICIT_DEF
     ; GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
     ; GFX11-NEXT: $vgpr2 = V_FMAMK_F16_t16 $vgpr0, 18688, $vgpr1, implicit $mode, implicit $exec
     ; GFX11-NEXT: SI_RETURN implicit $vgpr2
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
-    $vgpr2 = V_FMA_F16_gfx9_e64 0, 18688, 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $mode, implicit $exec
+    $vgpr2 = V_FMA_F16_gfx9_e64 0, 18688, 0, $vgpr0, 0, $vgpr1, 0, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit $vgpr2
 ...
 
 ---
 name: fma_vcv_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: fma_vcv_f16
     ; GFX10: $vgpr0 = IMPLICIT_DEF
     ; GFX10-NEXT: $vgpr1 = IMPLICIT_DEF
     ; GFX10-NEXT: $vgpr2 = V_FMAMK_F16 $vgpr0, 18688, $vgpr1, implicit $mode, implicit $exec
     ; GFX10-NEXT: SI_RETURN implicit $vgpr2
     ; GFX11-LABEL: name: fma_vcv_f16
     ; GFX11: $vgpr0 = IMPLICIT_DEF
     ; GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
     ; GFX11-NEXT: $vgpr2 = V_FMAMK_F16_t16 $vgpr0, 18688, $vgpr1, implicit $mode, implicit $exec
     ; GFX11-NEXT: SI_RETURN implicit $vgpr2
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
-    $vgpr2 = V_FMA_F16_gfx9_e64 0, $vgpr0, 0, 18688, 0, $vgpr1, 0, 0, implicit $mode, implicit $exec
+    $vgpr2 = V_FMA_F16_gfx9_e64 0, $vgpr0, 0, 18688, 0, $vgpr1, 0, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit $vgpr2
 ...
 
 ---
 name: fma_vvc_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: fma_vvc_f16
     ; GFX10: $vgpr0 = IMPLICIT_DEF
     ; GFX10-NEXT: $vgpr1 = IMPLICIT_DEF
     ; GFX10-NEXT: $vgpr2 = V_FMAAK_F16 $vgpr0, $vgpr1, 18688, implicit $mode, implicit $exec
     ; GFX10-NEXT: SI_RETURN implicit $vgpr2
     ; GFX11-LABEL: name: fma_vvc_f16
     ; GFX11: $vgpr0 = IMPLICIT_DEF
     ; GFX11-NEXT: $vgpr1 = IMPLICIT_DEF
     ; GFX11-NEXT: $vgpr2 = V_FMAAK_F16_t16 $vgpr0, $vgpr1, 18688, implicit $mode, implicit $exec
     ; GFX11-NEXT: SI_RETURN implicit $vgpr2
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = IMPLICIT_DEF
-    $vgpr2 = V_FMA_F16_gfx9_e64 0, $vgpr0, 0, $vgpr1, 0, 18688, 0, 0, implicit $mode, implicit $exec
+    $vgpr2 = V_FMA_F16_gfx9_e64 0, $vgpr0, 0, $vgpr1, 0, 18688, 0, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit $vgpr2
 ...
 
 ---
 name: fma_vsc_f16
 body: |
   bb.0:
     ; GFX10-LABEL: name: fma_vsc_f16
     ; GFX10: $vgpr0 = IMPLICIT_DEF
     ; GFX10-NEXT: $sgpr1 = IMPLICIT_DEF
     ; GFX10-NEXT: $vgpr2 = V_FMAAK_F16 $vgpr0, $vgpr1, 18688, implicit $mode, implicit $exec
     ; GFX10-NEXT: SI_RETURN implicit $vgpr2
     ; GFX11-LABEL: name: fma_vsc_f16
     ; GFX11: $vgpr0 = IMPLICIT_DEF
     ; GFX11-NEXT: $sgpr1 = IMPLICIT_DEF
     ; GFX11-NEXT: $vgpr2 = V_FMAAK_F16_t16 $vgpr0, $vgpr1, 18688, implicit $mode, implicit $exec
     ; GFX11-NEXT: SI_RETURN implicit $vgpr2
     $vgpr0 = IMPLICIT_DEF
     $sgpr1 = IMPLICIT_DEF
-    $vgpr2 = V_FMA_F16_gfx9_e64 0, $vgpr0, 0, $vgpr1, 0, 18688, 0, 0, implicit $mode, implicit $exec
+    $vgpr2 = V_FMA_F16_gfx9_e64 0, $vgpr0, 0, $vgpr1, 0, 18688, 0, 0, 0, implicit $mode, implicit $exec
     SI_RETURN implicit $vgpr2
 ...

llvm/test/MC/AMDGPU/gfx11_asm_vop3.s

 // GFX11: encoding: [0x05,0x10,0x54,0xd6,0xf0,0xfa,0xc0,0x43]
 
 v_div_fixup_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
 // GFX11: encoding: [0x05,0x22,0x54,0xd6,0xfd,0xd4,0x04,0x23]
 
 v_div_fixup_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
 // GFX11: encoding: [0xff,0xc3,0x54,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 
+v_div_fixup_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] mul:2
+// GFX11: encoding: [0x05,0x10,0x54,0xd6,0xf0,0xfa,0xc0,0x4b]
+
 v_div_fixup_f32 v5, v1, v2, s3
 // GFX11: encoding: [0x05,0x00,0x27,0xd6,0x01,0x05,0x0e,0x00]
 
 v_div_fixup_f32 v5, v255, s2, s105
 // GFX11: encoding: [0x05,0x00,0x27,0xd6,0xff,0x05,0xa4,0x01]
 
 v_div_fixup_f32 v5, s1, v255, exec_hi
 // GFX11: encoding: [0x05,0x00,0x27,0xd6,0x01,0xfe,0xff,0x01]

 // GFX11: encoding: [0x05,0x10,0x48,0xd6,0xf0,0xfa,0xc0,0x43]
 
 v_fma_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
 // GFX11: encoding: [0x05,0x22,0x48,0xd6,0xfd,0xd4,0x04,0x23]
 
 v_fma_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
 // GFX11: encoding: [0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 
+v_fma_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp div:2
+// GFX11: encoding: [0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00]
+
 v_fma_f32 v5, v1, v2, s3
 // GFX11: encoding: [0x05,0x00,0x13,0xd6,0x01,0x05,0x0e,0x00]
 
 v_fma_f32 v5, v255, s2, s105
 // GFX11: encoding: [0x05,0x00,0x13,0xd6,0xff,0x05,0xa4,0x01]
 
 v_fma_f32 v5, s1, v255, exec_hi
 // GFX11: encoding: [0x05,0x00,0x13,0xd6,0x01,0xfe,0xff,0x01]

 // GFX11: encoding: [0x05,0x10,0x4c,0xd6,0xf0,0xfa,0xc0,0x43]
 
 v_max3_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
 // GFX11: encoding: [0x05,0x22,0x4c,0xd6,0xfd,0xd4,0x04,0x23]
 
 v_max3_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
 // GFX11: encoding: [0xff,0xc3,0x4c,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 
+v_max3_f16 v5, v255, s2, s105 mul:2
+// GFX11: encoding: [0x05,0x00,0x4c,0xd6,0xff,0x05,0xa4,0x09]
+
 v_max3_f32 v5, v1, v2, s3
 // GFX11: encoding: [0x05,0x00,0x1c,0xd6,0x01,0x05,0x0e,0x00]
 
 v_max3_f32 v5, v255, s2, s105
 // GFX11: encoding: [0x05,0x00,0x1c,0xd6,0xff,0x05,0xa4,0x01]
 
 v_max3_f32 v5, s1, v255, exec_hi
 // GFX11: encoding: [0x05,0x00,0x1c,0xd6,0x01,0xfe,0xff,0x01]

 // GFX11: encoding: [0x05,0x10,0x4f,0xd6,0xf0,0xfa,0xc0,0x43]
 
 v_med3_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
 // GFX11: encoding: [0x05,0x22,0x4f,0xd6,0xfd,0xd4,0x04,0x23]
 
 v_med3_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
 // GFX11: encoding: [0xff,0xc3,0x4f,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 
+v_med3_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] div:2
+// GFX11: encoding: [0x05,0x10,0x4f,0xd6,0xf0,0xfa,0xc0,0x5b]
+
 v_med3_f32 v5, v1, v2, s3
 // GFX11: encoding: [0x05,0x00,0x1f,0xd6,0x01,0x05,0x0e,0x00]
 
 v_med3_f32 v5, v255, s2, s105
 // GFX11: encoding: [0x05,0x00,0x1f,0xd6,0xff,0x05,0xa4,0x01]
 
 v_med3_f32 v5, s1, v255, exec_hi
 // GFX11: encoding: [0x05,0x00,0x1f,0xd6,0x01,0xfe,0xff,0x01]

 // GFX11: encoding: [0x05,0x10,0x49,0xd6,0xf0,0xfa,0xc0,0x43]
 
 v_min3_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0]
 // GFX11: encoding: [0x05,0x22,0x49,0xd6,0xfd,0xd4,0x04,0x23]
 
 v_min3_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
 // GFX11: encoding: [0xff,0xc3,0x49,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 
+v_min3_f16 v5, m0, 0.5, m0 clamp mul:4
+// GFX11: encoding: [0x05,0x80,0x49,0xd6,0x7d,0xe0,0xf5,0x11]
+
 v_min3_f32 v5, v1, v2, s3
 // GFX11: encoding: [0x05,0x00,0x19,0xd6,0x01,0x05,0x0e,0x00]
 
 v_min3_f32 v5, v255, s2, s105
 // GFX11: encoding: [0x05,0x00,0x19,0xd6,0xff,0x05,0xa4,0x01]
 
 v_min3_f32 v5, s1, v255, exec_hi
 // GFX11: encoding: [0x05,0x00,0x19,0xd6,0x01,0xfe,0xff,0x01]

llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s

 // CHECK: [0x05,0x40,0xf4,0xd1,0x01,0x05,0x0e,0x04]
 
 v_min3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
 // CHECK: [0x05,0x78,0xf4,0xd1,0x01,0x05,0x0e,0x04]
 
 v_min3_f16 v5, v1, v2, v3 clamp
 // CHECK: [0x05,0x80,0xf4,0xd1,0x01,0x05,0x0e,0x04]
 
+v_min3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] mul:2
+// CHECK: [0x05,0x78,0xf4,0xd1,0x01,0x05,0x0e,0x0c]
+
 v_min3_i16 v5, v1, v2, v3
 // CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
 
 v_min3_i16 v255, v1, v2, v3
 // CHECK: [0xff,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
 
 v_min3_i16 v5, v255, v2, v3
 // CHECK: [0x05,0x00,0xf5,0xd1,0xff,0x05,0x0e,0x04]

 // CHECK: [0x05,0x40,0xf7,0xd1,0x01,0x05,0x0e,0x04]
 
 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
 // CHECK: [0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x04]
 
 v_max3_f16 v5, v1, v2, v3 clamp
 // CHECK: [0x05,0x80,0xf7,0xd1,0x01,0x05,0x0e,0x04]
 
+v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] mul:2
+// CHECK: [0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x0c]
+
 v_max3_i16 v5, v1, v2, v3
 // CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
 
 v_max3_i16 v255, v1, v2, v3
 // CHECK: [0xff,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
 
 v_max3_i16 v5, v255, v2, v3
 // CHECK: [0x05,0x00,0xf8,0xd1,0xff,0x05,0x0e,0x04]

 // CHECK: [0x05,0x40,0xfa,0xd1,0x01,0x05,0x0e,0x04]
 
 v_med3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
 // CHECK: [0x05,0x78,0xfa,0xd1,0x01,0x05,0x0e,0x04]
 
 v_med3_f16 v5, v1, v2, v3 clamp
 // CHECK: [0x05,0x80,0xfa,0xd1,0x01,0x05,0x0e,0x04]
 
+v_med3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] mul:2
+// CHECK: [0x05,0x78,0xfa,0xd1,0x01,0x05,0x0e,0x0c]
+
 v_med3_i16 v5, v1, v2, v3
 // CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
 
 v_med3_i16 v255, v1, v2, v3
 // CHECK: [0xff,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
 
 v_med3_i16 v5, v255, v2, v3
 // CHECK: [0x05,0x00,0xfb,0xd1,0xff,0x05,0x0e,0x04]

 // CHECK: [0x05,0x40,0x03,0xd2,0x01,0x05,0x0e,0x04]
 
 v_mad_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
 // CHECK: [0x05,0x78,0x03,0xd2,0x01,0x05,0x0e,0x04]
 
 v_mad_f16 v5, v1, v2, v3 clamp
 // CHECK: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
 
+v_mad_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] mul:4
+// CHECK: [0x05,0x78,0x03,0xd2,0x01,0x05,0x0e,0x14]
+
 v_mad_u16 v5, v1, v2, v3
 // CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04]
 
 v_mad_u16 v255, v1, v2, v3
 // CHECK: [0xff,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04]
 
 v_mad_u16 v5, v255, v2, v3
 // CHECK: [0x05,0x00,0x04,0xd2,0xff,0x05,0x0e,0x04]

 // CHECK: [0x05,0x40,0x06,0xd2,0x01,0x05,0x0e,0x04]
 
 v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
 // CHECK: [0x05,0x78,0x06,0xd2,0x01,0x05,0x0e,0x04]
 
 v_fma_f16 v5, v1, v2, v3 clamp
 // CHECK: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
 
+v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] clamp mul:2
+// CHECK: [0x05,0xf8,0x06,0xd2,0x01,0x05,0x0e,0x0c]
+
 v_div_fixup_f16 v5, v1, v2, v3
 // CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
 
 v_div_fixup_f16 v255, v1, v2, v3
 // CHECK: [0xff,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
 
 v_div_fixup_f16 v5, v255, v2, v3
 // CHECK: [0x05,0x00,0x07,0xd2,0xff,0x05,0x0e,0x04]

 // CHECK: [0x05,0x20,0x07,0xd2,0x01,0x05,0x0e,0x04]
 
 v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
 // CHECK: [0x05,0x40,0x07,0xd2,0x01,0x05,0x0e,0x04]
 
 v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
 // CHECK: [0x05,0x78,0x07,0xd2,0x01,0x05,0x0e,0x04]
 
+v_div_fixup_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] mul:2
+// CHECK: [0x05,0x10,0x07,0xd2,0xf0,0xf8,0xc0,0x4b]
+
 v_div_fixup_f16 v5, v1, v2, v3 clamp
 // CHECK: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
 
 v_interp_p1ll_f16 v5, v2, attr0.x
 // CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
 
 v_interp_p1ll_f16 v255, v2, attr0.x
 // CHECK: [0xff,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt

 0x05,0x10,0x54,0xd6,0xf0,0xfa,0xc0,0x43
 
 # GFX11: v_div_fixup_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x54,0xd6,0xfd,0xd4,0x04,0x23]
 0x05,0x22,0x54,0xd6,0xfd,0xd4,0x04,0x23
 
 # GFX11: v_div_fixup_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x54,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 0xff,0xc3,0x54,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
 
+# CHECK: v_div_fixup_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] mul:2   ; encoding: [0x05,0x10,0x54,0xd6,0xf0,0xfa,0xc0,0x4b]
+0x05,0x10,0x54,0xd6,0xf0,0xfa,0xc0,0x4b
+
 # GFX11: v_div_fixup_f32 v5, v1, v2, s3          ; encoding: [0x05,0x00,0x27,0xd6,0x01,0x05,0x0e,0x00]
 0x05,0x00,0x27,0xd6,0x01,0x05,0x0e,0x00
 
 # GFX11: v_div_fixup_f32 v5, v255, s2, s105      ; encoding: [0x05,0x00,0x27,0xd6,0xff,0x05,0xa4,0x01]
 0x05,0x00,0x27,0xd6,0xff,0x05,0xa4,0x01
 
 # GFX11: v_div_fixup_f32 v5, s1, v255, exec_hi   ; encoding: [0x05,0x00,0x27,0xd6,0x01,0xfe,0xff,0x01]
 0x05,0x00,0x27,0xd6,0x01,0xfe,0xff,0x01

 0x05,0x10,0x48,0xd6,0xf0,0xfa,0xc0,0x43
 
 # GFX11: v_fma_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x48,0xd6,0xfd,0xd4,0x04,0x23]
 0x05,0x22,0x48,0xd6,0xfd,0xd4,0x04,0x23
 
 # GFX11: v_fma_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
 
+# CHECK: v_fma_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp div:2    ; encoding: [0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00]
+0xff,0xc3,0x48,0xd6,0xff,0xd6,0xf0,0x79,0x0b,0xfe,0x00,0x00
+
 # GFX11: v_fma_f32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x13,0xd6,0x01,0x05,0x0e,0x00]
 0x05,0x00,0x13,0xd6,0x01,0x05,0x0e,0x00
 
 # GFX11: v_fma_f32 v5, v255, s2, s105            ; encoding: [0x05,0x00,0x13,0xd6,0xff,0x05,0xa4,0x01]
 0x05,0x00,0x13,0xd6,0xff,0x05,0xa4,0x01
 
 # GFX11: v_fma_f32 v5, s1, v255, exec_hi         ; encoding: [0x05,0x00,0x13,0xd6,0x01,0xfe,0xff,0x01]
 0x05,0x00,0x13,0xd6,0x01,0xfe,0xff,0x01

 0x05,0x10,0x4c,0xd6,0xf0,0xfa,0xc0,0x43
 
 # GFX11: v_max3_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x4c,0xd6,0xfd,0xd4,0x04,0x23]
 0x05,0x22,0x4c,0xd6,0xfd,0xd4,0x04,0x23
 
 # GFX11: v_max3_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x4c,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 0xff,0xc3,0x4c,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
 
+# CHECK: v_max3_f16 v5, v255, s2, s105 mul:2     ; encoding: [0x05,0x00,0x4c,0xd6,0xff,0x05,0xa4,0x09]
+0x05,0x00,0x4c,0xd6,0xff,0x05,0xa4,0x09
+
 # GFX11: v_max3_f32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x1c,0xd6,0x01,0x05,0x0e,0x00]
 0x05,0x00,0x1c,0xd6,0x01,0x05,0x0e,0x00
 
 # GFX11: v_max3_f32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x1c,0xd6,0xff,0x05,0xa4,0x01]
 0x05,0x00,0x1c,0xd6,0xff,0x05,0xa4,0x01
 
 # GFX11: v_max3_f32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x1c,0xd6,0x01,0xfe,0xff,0x01]
 0x05,0x00,0x1c,0xd6,0x01,0xfe,0xff,0x01

 0x05,0x10,0x4f,0xd6,0xf0,0xfa,0xc0,0x43
 
 # GFX11: v_med3_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x4f,0xd6,0xfd,0xd4,0x04,0x23]
 0x05,0x22,0x4f,0xd6,0xfd,0xd4,0x04,0x23
 
 # GFX11: v_med3_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x4f,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 0xff,0xc3,0x4f,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
 
+# CHECK: v_med3_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] div:2    ; encoding: [0x05,0x10,0x4f,0xd6,0xf0,0xfa,0xc0,0x5b]
+0x05,0x10,0x4f,0xd6,0xf0,0xfa,0xc0,0x5b
+
 # GFX11: v_med3_f32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x1f,0xd6,0x01,0x05,0x0e,0x00]
 0x05,0x00,0x1f,0xd6,0x01,0x05,0x0e,0x00
 
 # GFX11: v_med3_f32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x1f,0xd6,0xff,0x05,0xa4,0x01]
 0x05,0x00,0x1f,0xd6,0xff,0x05,0xa4,0x01
 
 # GFX11: v_med3_f32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x1f,0xd6,0x01,0xfe,0xff,0x01]
 0x05,0x00,0x1f,0xd6,0x01,0xfe,0xff,0x01

 0x05,0x10,0x49,0xd6,0xf0,0xfa,0xc0,0x43
 
 # GFX11: v_min3_f16 v5, -src_scc, |vcc_lo|, -1 op_sel:[0,0,1,0] ; encoding: [0x05,0x22,0x49,0xd6,0xfd,0xd4,0x04,0x23]
 0x05,0x22,0x49,0xd6,0xfd,0xd4,0x04,0x23
 
 # GFX11: v_min3_f16 v255, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x49,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
 0xff,0xc3,0x49,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00
 
+# CHECK: v_min3_f16 v5, m0, 0.5, m0 clamp mul:4  ; encoding: [0x05,0x80,0x49,0xd6,0x7d,0xe0,0xf5,0x11]
+0x05,0x80,0x49,0xd6,0x7d,0xe0,0xf5,0x11
+
 # GFX11: v_min3_f32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x19,0xd6,0x01,0x05,0x0e,0x00]
 0x05,0x00,0x19,0xd6,0x01,0x05,0x0e,0x00
 
 # GFX11: v_min3_f32 v5, v255, s2, s105           ; encoding: [0x05,0x00,0x19,0xd6,0xff,0x05,0xa4,0x01]
 0x05,0x00,0x19,0xd6,0xff,0x05,0xa4,0x01
 
 # GFX11: v_min3_f32 v5, s1, v255, exec_hi        ; encoding: [0x05,0x00,0x19,0xd6,0x01,0xfe,0xff,0x01]
 0x05,0x00,0x19,0xd6,0x01,0xfe,0xff,0x01

llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt

 0x05,0x40,0xf4,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_min3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xf4,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x78,0xf4,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_min3_f16 v5, v1, v2, v3 clamp         ; encoding: [0x05,0x80,0xf4,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x80,0xf4,0xd1,0x01,0x05,0x0e,0x04
 
+# CHECK: v_min3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] mul:2 ; encoding: [0x05,0x78,0xf4,0xd1,0x01,0x05,0x0e,0x0c]
+0x05,0x78,0xf4,0xd1,0x01,0x05,0x0e,0x0c
+
 # CHECK: v_min3_i16 v5, v1, v2, v3               ; encoding: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_min3_i16 v255, v1, v2, v3             ; encoding: [0xff,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
 0xff,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_min3_i16 v5, v255, v2, v3             ; encoding: [0x05,0x00,0xf5,0xd1,0xff,0x05,0x0e,0x04]
 0x05,0x00,0xf5,0xd1,0xff,0x05,0x0e,0x04

 0x05,0x40,0xf7,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_max3_f16 v5, v1, v2, v3 clamp         ; encoding: [0x05,0x80,0xf7,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x80,0xf7,0xd1,0x01,0x05,0x0e,0x04
 
+# CHECK: v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] mul:2 ; encoding: [0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x0c]
+0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x0c
+
 # CHECK: v_max3_i16 v5, v1, v2, v3               ; encoding: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_max3_i16 v255, v1, v2, v3             ; encoding: [0xff,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
 0xff,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_max3_i16 v5, v255, v2, v3             ; encoding: [0x05,0x00,0xf8,0xd1,0xff,0x05,0x0e,0x04]
 0x05,0x00,0xf8,0xd1,0xff,0x05,0x0e,0x04

 0x05,0x40,0xfa,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_med3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xfa,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x78,0xfa,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_med3_f16 v5, v1, v2, v3 clamp         ; encoding: [0x05,0x80,0xfa,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x80,0xfa,0xd1,0x01,0x05,0x0e,0x04
 
+# CHECK: v_med3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] mul:2 ; encoding: [0x05,0x78,0xfa,0xd1,0x01,0x05,0x0e,0x0c]
+0x05,0x78,0xfa,0xd1,0x01,0x05,0x0e,0x0c
+
 # CHECK: v_med3_i16 v5, v1, v2, v3               ; encoding: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_med3_i16 v255, v1, v2, v3             ; encoding: [0xff,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
 0xff,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_med3_i16 v5, v255, v2, v3             ; encoding: [0x05,0x00,0xfb,0xd1,0xff,0x05,0x0e,0x04]
 0x05,0x00,0xfb,0xd1,0xff,0x05,0x0e,0x04

 0x05,0x40,0x07,0xd2,0x01,0x05,0x0e,0x04
 
 # CHECK: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x07,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x78,0x07,0xd2,0x01,0x05,0x0e,0x04
 
 # CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04
 
+# CHECK: v_div_fixup_f16 v5, 0.5, -m0, 0.5 op_sel:[0,1,0,0] mul:2 ; encoding: [0x05,0x10,0x07,0xd2,0xf0,0xf8,0xc0,0x4b]
+0x05,0x10,0x07,0xd2,0xf0,0xf8,0xc0,0x4b
+
 # CHECK: v_interp_p1ll_f16 v5, v2, attr0.x       ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
 0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00
 
 # CHECK: v_interp_p1ll_f16 v255, v2, attr0.x     ; encoding: [0xff,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
 0xff,0x00,0x74,0xd2,0x00,0x04,0x02,0x00
 
 # CHECK: v_interp_p1ll_f16 v5, v2, attr1.x       ; encoding: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
 0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00

 0x05,0x08,0x06,0xd2,0x01,0x05,0x0e,0x04
 
 # CHECK: v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x06,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x78,0x06,0xd2,0x01,0x05,0x0e,0x04
 
 # CHECK: v_fma_f16 v5, v1, v2, v3 clamp          ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04
 
+# CHECK: v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] clamp mul:2 ; encoding: [0x05,0xf8,0x06,0xd2,0x01,0x05,0x0e,0x0c]
+0x05,0xf8,0x06,0xd2,0x01,0x05,0x0e,0x0c
+
 # CHECK: v_fma_legacy_f16 v5, v1, v2, v3         ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04
 
 # CHECK: v_fma_legacy_f16 v5, v1, v2, -v3        ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
 0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84
 
 # CHECK: v_fma_legacy_f16 v5, |v1|, v2, v3       ; encoding: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04