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Differential D139002

[AMDGPU] Remove todo about vector types
ClosedPublic

Authored by sebastian-ne on Nov 30 2022, 4:20 AM.

Details

Reviewers
matejam
dstuttard
foad
Commits
rG53efce306497: [AMDGPU] Remove todo about vector types
Summary

D138205 added all the new vector types, so the todo is fixed now.

Diff Detail

Event Timeline

sebastian-ne created this revision.Nov 30 2022, 4:20 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 30 2022, 4:20 AM
Herald added subscribers: kosarev, kerbowa, hiraditya and 5 others. · View Herald Transcript
sebastian-ne requested review of this revision.Nov 30 2022, 4:20 AM
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foad accepted this revision.Nov 30 2022, 4:57 AM
This revision is now accepted and ready to land.Nov 30 2022, 4:57 AM
This revision was landed with ongoing or failed builds.Nov 30 2022, 5:13 AM
Closed by commit rG53efce306497: [AMDGPU] Remove todo about vector types (authored by sebastian-ne). · Explain Why
This revision was automatically updated to reflect the committed changes.
sebastian-ne added a commit: rG53efce306497: [AMDGPU] Remove todo about vector types.
Harbormaster completed remote builds in B200236: Diff 478892.Nov 30 2022, 5:35 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines

Diff 478906

llvm/lib/Target/AMDGPU/MIMGInstructions.td

Show First 20 Lines • Show All 1,127 Lines • ▼ Show 20 Linesmulticlass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0,
} }
} }
multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample> multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample>
: MIMG_Gather<op, sample, 1>; : MIMG_Gather<op, sample, 1>;
class MIMG_IntersectRay_Helper<bit Is64, bit A16> { class MIMG_IntersectRay_Helper<bit Is64, bit A16> {
int num_addrs = !if(Is64, !if(A16, 9, 12), !if(A16, 8, 11)); int num_addrs = !if(Is64, !if(A16, 9, 12), !if(A16, 8, 11));
// TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple,
// when we only need 9, 11 or 12 depending on A16 field and ptr size.
RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass; RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;
int VAddrDwords = !srl(RegClass.Size, 5); int VAddrDwords = !srl(RegClass.Size, 5);
int gfx11_nsa_addrs = !if(A16, 4, 5); int gfx11_nsa_addrs = !if(A16, 4, 5);
RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32); RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
list<RegisterClass> gfx11_addr_types = list<RegisterClass> gfx11_addr_types =
!if(A16, !if(A16,
[node_ptr_type, VGPR_32, VReg_96, VReg_96], [node_ptr_type, VGPR_32, VReg_96, VReg_96],
▲ Show 20 Lines • Show All 400 Lines • Show Last 20 Lines