[PowerPC] Materialize floats in the range [-16.0, 15.0].

[stefanp]

Summary

Previous to this patch we only materialized 0.0 and all other floating point
values would be loaded from the TOC. This patch adds materialization for the
floating point values that can be represented as integers in [-16.0, 15.0].

For example we will now materialize 3.0 and -5.0 but not 4.7.

[stefanp]

Forgot to do a clang-format.
Updated patch with that.

[nemanjai]

Do we already handle vector constants that are splats (i.e. { 1.0f, 1.0f, 1.0f, 1.0f } or { 3.0, 3.0 })? If not, do we plan to?

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1348

Why do we need custom selection code here? Can't we just implement this in the .td files similarly to how we implemented lowering for Power10 (see nzFPImmAsi32 and getFPAs32BitInt). We just need a version of nzFPImmAsi32 that checks for exact conversion and the result being in the expected range.

1367–1368

This looks wrong. This will produce a pair of 32-bit single precision values in the FP portion of the VSX register. What you want is a 64-bit double precision value in each doubleword.

Don't forget that single precision values on PPC are in registers as double precison but rounded to single precision (i.e. a double precision representation of a single precision value).

I think you should use scalar instructions for scalar values (xscvsxdsp, xscvsxddp).

[stefanp]

Moved the constant materialization to the td file.

[stefanp]

In D138844#3955932, @nemanjai wrote:

Do we already handle vector constants that are splats (i.e. { 1.0f, 1.0f, 1.0f, 1.0f } or { 3.0, 3.0 })? If not, do we plan to?

We don't handle this yet but we should. I think this would be a separate patch though.

[stefanp]

There are some tests failing with this patch. I'm looking into them now...

[stefanp]

Fixed the patch and a number of test cases.

[stefanp]

Removed unnecessary whitespace change.

[stefanp]

I would like to address the following comment because it is not at all obvious why I decided not to go with this approach.

This looks wrong. This will produce a pair of 32-bit single precision values in the FP portion of the VSX register. What you want is a 64-bit double precision value in each doubleword.
Don't forget that single precision values on PPC are in registers as double precison but rounded to single precision (i.e. a double precision representation of a single precision value).
I think you should use scalar instructions for scalar values (xscvsxdsp, xscvsxddp).

The instruction that does the integer splat is vspltisw which puts the same copy of the integer in every word of the vector. The scalar instructions xscvsxdsp, xscvsxddp look at double word entries and not word entries so they cannot be used to convert the word integers into floats.
There is no double word version of an instruction like`vspltisw` to go with xscvsxdsp, xscvsxddp. Likewise, to my knowledge, there is no word instruction for the scalar convert.
To get around this issue the vector word convert was used xvcvsxwdp. This works for both double and single precision because we know exactly which constants we are representing and we know that they can be exactly represented in both float and double.

[lei]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

17182

Previous behavour is "fallthrough" which will result in a return of Imm.isPosZero(). Do we not want the defalut to be same as before?

[stefanp]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

17182

Previous behavour is "fallthrough" which will result in a return of Imm.isPosZero(). Do we not want the defalut to be same as before?

Actually we can now handle negative zero as well for the types f32 and f64 due to this:

def : Pat<(f64 (fpimm0neg)),
          (f64 (XSNEGDP (XXLXORdpz)))>;

def : Pat<(f32 (fpimm0neg)),
          (f32 (COPY_TO_REGCLASS (XSNEGDP (XXLXORdpz)), VSSRC))>;

So, we can safely check for all zeros instead of just positive zero.

[lei]

Thanks! This LGTM

[nemanjai]

LGTM.

[stefanp]

Rebased to top of main branch.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

if (unsigned MinSize = allUsesTruncate(CurDAG, N)) {
     uint64_t SextImm = SignExtend64(Imm, MinSize);
     SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
     if (isInt<16>(SextImm))
       return CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
   }
   return selectI64Imm(CurDAG, dl, Imm);
 }
 
 namespace {
 
 class BitPermutationSelector {
   struct ValueBit {
     SDValue V;
 
     // The bit number in the value, using a convention where bit 0 is the
     // lowest-order bit.
     unsigned Idx;
 
     // ConstZero means a bit we need to mask off.
     // Variable is a bit comes from an input variable.
     // VariableKnownToBeZero is also a bit comes from an input variable,
     // but it is known to be already zero. So we do not need to mask them.
     enum Kind {
       ConstZero,
       Variable,
       VariableKnownToBeZero
     } K;
 
     ValueBit(SDValue V, unsigned I, Kind K = Variable)
       : V(V), Idx(I), K(K) {}
     ValueBit(Kind K = Variable) : Idx(UINT32_MAX), K(K) {}
 
     bool isZero() const {
       return K == ConstZero || K == VariableKnownToBeZero;
     }
 
     bool hasValue() const {
void PPCDAGToDAGISel::Select(SDNode *N) {
   default: break;
 
   case ISD::Constant:
     if (N->getValueType(0) == MVT::i64) {
       ReplaceNode(N, selectI64Imm(CurDAG, N));
       return;
     }
     break;
-
   case ISD::INTRINSIC_VOID: {
     auto IntrinsicID = N->getConstantOperandVal(1);
     if (IntrinsicID != Intrinsic::ppc_tdw && IntrinsicID != Intrinsic::ppc_tw &&
         IntrinsicID != Intrinsic::ppc_trapd &&
         IntrinsicID != Intrinsic::ppc_trap)
         break;
     unsigned Opcode = (IntrinsicID == Intrinsic::ppc_tdw ||
                        IntrinsicID == Intrinsic::ppc_trapd)

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (!VT.isSimple() || !Subtarget.hasVSX())
     return false;
 
   switch(VT.getSimpleVT().SimpleTy) {
   default:
     // For FP types that are currently not supported by PPC backend, return
     // false. Examples: f16, f80.
     return false;
   case MVT::f32:
-  case MVT::f64:
+  case MVT::f64: {
     if (Subtarget.hasPrefixInstrs()) {
       // we can materialize all immediatess via XXSPLTI32DX and XXSPLTIDP.
       return true;
     }
-    [[fallthrough]];
+    bool IsExact;
+    APSInt IntResult(16, false);
+    // The rounding mode doesn't really matter because we only care about floats
+    // that can be converted to integers exactly.
+    Imm.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact);
+    // For exact values in the range [-16, 15] we can materialize the float.
+    if (IsExact && IntResult <= 15 && IntResult >= -16)
+      return true;
+    return Imm.isZero();
+  }
   case MVT::ppcf128:
     return Imm.isPosZero();
   }
 }
 
 // For vector shift operation op, fold
 // (op x, (and y, ((1 << numbits(x)) - 1))) -> (target op x, y)
 static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N,

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 // A floating point immediate that is not a positive zero and can be converted
 // to a single precision floating point non-denormal immediate without loss of
 // information.
 def nzFPImmAsi32 : PatLeaf<(fpimm), [{
   APFloat APFloatOfN = N->getValueAPF();
   return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0);
 }]>;
 
+// A floating point immediate that is exactly an integer (for example 3.0, -5.0)
+// and can be represented in 5 bits (range of [-16, 15]).
+def nzFPImmExactInti5 : PatLeaf<(fpimm), [{
+  APFloat FloatValue = N->getValueAPF();
+  bool IsExact;
+  APSInt IntResult(16, false);
+  FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact);
+  return IsExact && IntResult <= 15 && IntResult >= -16 && !FloatValue.isZero();
+}]>;
+
+def getFPAs5BitExactInt : SDNodeXForm<fpimm, [{
+  APFloat FloatValue = N->getValueAPF();
+  bool IsExact;
+  APSInt IntResult(32, false);
+  FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact);
+  return CurDAG->getTargetConstant(IntResult, SDLoc(N), MVT::i32);
+}]>;
+
 // Convert the floating point immediate into a 32 bit floating point immediate
 // and get a i32 with the resulting bits.
 def getFPAs32BitInt : SDNodeXForm<fpimm, [{
   APFloat APFloatOfN = N->getValueAPF();
   convertToNonDenormSingle(APFloatOfN);
   return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(),
                                    SDLoc(N), MVT::i32);
 }]>;

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 // Valid for any VSX subtarget, regardless of endianness.
 let Predicates = [HasVSX] in {
 def : Pat<(v4i32 (vnot v4i32:$A)),
           (v4i32 (XXLNOR $A, $A))>;
 def : Pat<(v4i32 (or (and (vnot v4i32:$C), v4i32:$A),
                      (and v4i32:$B, v4i32:$C))),
           (v4i32 (XXSEL $A, $B, $C))>;
 
+def : Pat<(f64 (fpimm0neg)),
+          (f64 (XSNEGDP (XXLXORdpz)))>;
+
+def : Pat<(f32 (fpimm0neg)),
+          (f32 (COPY_TO_REGCLASS (XSNEGDP (XXLXORdpz)), VSSRC))>;
+
+def : Pat<(f64 (nzFPImmExactInti5:$A)),
+          (XSCVSXDDP (COPY_TO_REGCLASS
+                     (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSFRC))>;
+
+def : Pat<(f32 (nzFPImmExactInti5:$A)),
+          (XSCVSXDSP (COPY_TO_REGCLASS
+                     (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSFRC))>;
+
 // Additional fnmsub pattern for PPC specific ISD opcode
 def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),
           (XSNMSUBADP $C, $A, $B)>;
 def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),
           (XSMSUBADP $C, $A, $B)>;
 def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),
           (XSNMADDADP $C, $A, $B)>;
 

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 def immZero : Operand<i32> {
   let PrintMethod = "printImmZeroOperand";
   let ParserMatchClass = PPCImmZeroAsmOperand;
   let DecoderMethod = "decodeImmZeroOperand";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
+def fpimm0neg : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>;
 
 def PPCDirectBrAsmOperand : AsmOperandClass {
   let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
   let RenderMethod = "addBranchTargetOperands";
 }
 def directbrtarget : Operand<OtherVT> {
   let PrintMethod = "printBranchOperand";
   let EncoderMethod = "getDirectBrEncoding";

llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll

 
 ; CHECK:     ADJCALLSTACKDOWN 64, 0, implicit-def dead $r1, implicit $r1
 ; CHECK:     [[VECCONSTADDR:%[0-9]+]]:gprc = LWZtoc %const.0, $r2 :: (load (s32) from got)
 ; CHECK:     [[VECCONST:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[VECCONSTADDR]] :: (load (s128) from constant-pool)
 ; CHECK:     [[STACKOFFSET:%[0-9]+]]:gprc = LI 48
 ; CHECK:     STXVW4X killed [[VECCONST]], $r1, killed [[STACKOFFSET]] :: (store (s128))
 ; CHECK-DAG: [[ELEMENT1:%[0-9]+]]:gprc = LWZ 48, $r1 :: (load (s32))
 ; CHECK-DAG: [[ELEMENT2:%[0-9]+]]:gprc = LWZ 52, $r1 :: (load (s32))
-; CHECK:     [[FLOAT1ADDR:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc %const.1, $r2 :: (load (s32) from got)
-; CHECK:     [[FLOAT1:%[0-9]+]]:f4rc = LFS 0, killed [[FLOAT1ADDR]] :: (load (s32) from constant-pool)
-; CHECK:     [[DOUBLE1:%[0-9]+]]:f8rc = COPY [[FLOAT1]]
-; CHECK:     [[FLOAT2ADDR:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc %const.2, $r2 :: (load (s32) from got)
-; CHECK:     [[FLOAT2:%[0-9]+]]:f4rc = LFS 0, killed [[FLOAT2ADDR]] :: (load (s32) from constant-pool)
-; CHECK:     [[DOUBLE2:%[0-9]+]]:f8rc = COPY [[FLOAT2]]
+; CHECK:     [[FLOAT1SPLAT:%[0-9]+]]:vrrc = VSPLTISW 1
+; CHECK:     [[DOUBLE1:%[0-9]+]]:vsrc = XVCVSXWDP killed [[FLOAT1SPLAT]], implicit $rm
+; CHECK:     [[FLOAT2SPLAT:%[0-9]+]]:vrrc = VSPLTISW 2
+; CHECK:     [[DOUBLE2:%[0-9]+]]:vsrc = XVCVSXWDP killed [[FLOAT2SPLAT]], implicit $rm
 
 ; CHECK:     [[DZERO:%[0-9]+]]:vsfrc = XXLXORdpz
 ; CHECK:     [[DTOI1:%[0-9]+]]:gprc = LIS 16368
 ; CHECK:     [[DTOI2:%[0-9]+]]:gprc = LIS 16384
 ; CHECK:     [[IZERO:%[0-9]+]]:gprc = LI 0
 
 ; CHECK-DAG: $f1 = COPY [[DZERO]]
 ; CHECK-DAG: $r3 = COPY [[IZERO]]

llvm/test/CodeGen/PowerPC/elf64-byval-cc.ll

 ; CHECK-LABEL: call_test_byval_mem32_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stdu 1, -32(1)
 ; CHECK-NEXT:    std 0, 48(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addis 3, 2, .LC5@toc@ha
-; CHECK-NEXT:    addis 8, 2, .LCPI20_0@toc@ha
+; CHECK-NEXT:    vspltisw 2, 1
 ; CHECK-NEXT:    ld 3, .LC5@toc@l(3)
-; CHECK-NEXT:    lfs 1, .LCPI20_0@toc@l(8)
+; CHECK-NEXT:    xvcvsxwsp 1, 34
 ; CHECK-NEXT:    ld 7, 24(3)
 ; CHECK-NEXT:    ld 6, 16(3)
 ; CHECK-NEXT:    ld 5, 8(3)
 ; CHECK-NEXT:    ld 4, 0(3)
+; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    bl test_byval_mem32_2
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 1, 1, 32
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   %call = call zeroext i8 @test_byval_mem32_2(float 1.0, ptr byval(%struct_S32) align 1 @gS32)

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stdu 1, -112(1)
 ; CHECK-NEXT:    std 0, 128(1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 112
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addis 3, 2, .LC5@toc@ha
 ; CHECK-NEXT:    li 4, 16
-; CHECK-NEXT:    addis 5, 2, .LCPI22_1@toc@ha
+; CHECK-NEXT:    vspltisw 2, 1
+; CHECK-NEXT:    vspltisw 3, 4
+; CHECK-NEXT:    li 5, 3
 ; CHECK-NEXT:    li 7, 2
 ; CHECK-NEXT:    ld 3, .LC5@toc@l(3)
-; CHECK-NEXT:    lfs 2, .LCPI22_1@toc@l(5)
-; CHECK-NEXT:    li 5, 3
+; CHECK-NEXT:    xvcvsxwdp 2, 35
 ; CHECK-NEXT:    lxvd2x 0, 3, 4
 ; CHECK-NEXT:    li 4, 88
+; CHECK-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; CHECK-NEXT:    stxvd2x 0, 1, 4
 ; CHECK-NEXT:    li 4, 72
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    stxvd2x 0, 1, 4
-; CHECK-NEXT:    addis 4, 2, .LCPI22_0@toc@ha
-; CHECK-NEXT:    lfs 1, .LCPI22_0@toc@l(4)
+; CHECK-NEXT:    xvcvsxwsp 1, 34
 ; CHECK-NEXT:    ld 10, 16(3)
 ; CHECK-NEXT:    ld 9, 8(3)
 ; CHECK-NEXT:    ld 8, 0(3)
 ; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    bl test_byval_mem32_3
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 1, 1, 112
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   %call = call zeroext i8 @test_byval_mem32_3(i64 1, float 1.0, i64 3, double 4.0, i32 2, ptr byval(%struct_S32) align 1 @gS32)

llvm/test/CodeGen/PowerPC/fma-combine.ll

entry:
   %mul = fmul double %fneg1, %b
   %add = fsub double %mul, %a
   ret double %add
 }
 
 define dso_local float @fma_combine_no_ice() {
 ; CHECK-FAST-LABEL: fma_combine_no_ice:
 ; CHECK-FAST:       # %bb.0:
+; CHECK-FAST-NEXT:    vspltisw 2, 1
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-FAST-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
-; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
 ; CHECK-FAST-NEXT:    lfs 2, 0(3)
-; CHECK-FAST-NEXT:    lfs 3, .LCPI4_1@toc@l(3)
-; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_2@toc@ha
-; CHECK-FAST-NEXT:    lfs 1, .LCPI4_2@toc@l(3)
-; CHECK-FAST-NEXT:    xsmaddasp 3, 2, 0
-; CHECK-FAST-NEXT:    xsmaddasp 1, 2, 3
-; CHECK-FAST-NEXT:    xsnmsubasp 1, 3, 2
+; CHECK-FAST-NEXT:    lfs 1, .LCPI4_0@toc@l(3)
+; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
+; CHECK-FAST-NEXT:    xvcvsxwsp 0, 34
+; CHECK-FAST-NEXT:    xsmaddasp 0, 2, 1
+; CHECK-FAST-NEXT:    lfs 1, .LCPI4_1@toc@l(3)
+; CHECK-FAST-NEXT:    xsmaddasp 1, 2, 0
+; CHECK-FAST-NEXT:    xsnmsubasp 1, 0, 2
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_no_ice:
 ; CHECK-FAST-NOVSX:       # %bb.0:
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    lfs 1, 0(3)
 ; CHECK-FAST-NOVSX-NEXT:    lfs 2, .LCPI4_1@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_2@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    fmadds 0, 1, 2, 0
 ; CHECK-FAST-NOVSX-NEXT:    lfs 2, .LCPI4_2@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    fmadds 2, 1, 0, 2
 ; CHECK-FAST-NOVSX-NEXT:    fnmsubs 1, 0, 1, 2
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_no_ice:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisw 2, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
 ; CHECK-NEXT:    lfs 2, 0(3)
-; CHECK-NEXT:    lfs 3, .LCPI4_1@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, .LCPI4_2@toc@ha
-; CHECK-NEXT:    lfs 1, .LCPI4_2@toc@l(3)
-; CHECK-NEXT:    fmr 4, 3
-; CHECK-NEXT:    xsmaddasp 3, 2, 0
-; CHECK-NEXT:    xsnmaddasp 4, 2, 0
-; CHECK-NEXT:    xsmaddasp 1, 2, 3
+; CHECK-NEXT:    lfs 3, .LCPI4_0@toc@l(3)
+; CHECK-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
+; CHECK-NEXT:    lfs 1, .LCPI4_1@toc@l(3)
+; CHECK-NEXT:    xvcvsxwsp 0, 34
+; CHECK-NEXT:    fmr 4, 0
+; CHECK-NEXT:    xsmaddasp 0, 2, 3
+; CHECK-NEXT:    xsnmaddasp 4, 2, 3
+; CHECK-NEXT:    xsmaddasp 1, 2, 0
 ; CHECK-NEXT:    xsmaddasp 1, 4, 2
 ; CHECK-NEXT:    blr
   %tmp = load float, ptr undef, align 4
   %tmp2 = load float, ptr undef, align 4
   %tmp3 = fmul contract reassoc float %tmp, 0x3FE372D780000000
   %tmp4 = fadd contract reassoc float %tmp3, 1.000000e+00
   %tmp5 = fmul contract reassoc float %tmp2, %tmp4
   %tmp6 = load float, ptr undef, align 4
   %tmp7 = load float, ptr undef, align 4
   %tmp8 = fmul contract reassoc float %tmp7, 0x3FE372D780000000
   %tmp9 = fsub contract reassoc nsz float -1.000000e+00, %tmp8
   %tmp10 = fmul contract reassoc float %tmp9, %tmp6
   %tmp11 = fadd contract reassoc float %tmp5, 5.000000e-01
   %tmp12 = fadd contract reassoc float %tmp11, %tmp10
   ret float %tmp12
 }
 
 ; This would crash while trying getNegatedExpression().
 define dso_local double @getNegatedExpression_crash(double %x, double %y) {
 ; CHECK-FAST-LABEL: getNegatedExpression_crash:
 ; CHECK-FAST:       # %bb.0:
-; CHECK-FAST-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
-; CHECK-FAST-NEXT:    lfs 3, .LCPI5_1@toc@l(3)
+; CHECK-FAST-NEXT:    vspltisw 2, -1
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
 ; CHECK-FAST-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
+; CHECK-FAST-NEXT:    xvcvsxwdp 3, 34
 ; CHECK-FAST-NEXT:    xssubdp 0, 1, 3
+; CHECK-FAST-NEXT:    # kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-FAST-NEXT:    xsmaddadp 3, 1, 4
 ; CHECK-FAST-NEXT:    xsmaddadp 0, 3, 2
 ; CHECK-FAST-NEXT:    fmr 1, 0
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: getNegatedExpression_crash:
 ; CHECK-FAST-NOVSX:       # %bb.0:
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    addis 4, 2, .LCPI5_1@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    lfs 0, .LCPI5_0@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    lfs 3, .LCPI5_1@toc@l(4)
 ; CHECK-FAST-NOVSX-NEXT:    fmadd 3, 1, 3, 0
 ; CHECK-FAST-NOVSX-NEXT:    fsub 0, 1, 0
 ; CHECK-FAST-NOVSX-NEXT:    fmadd 1, 3, 2, 0
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: getNegatedExpression_crash:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
-; CHECK-NEXT:    lfs 3, .LCPI5_1@toc@l(3)
+; CHECK-NEXT:    vspltisw 2, -1
 ; CHECK-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
 ; CHECK-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
+; CHECK-NEXT:    xvcvsxwdp 3, 34
 ; CHECK-NEXT:    xssubdp 0, 1, 3
+; CHECK-NEXT:    # kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:    xsmaddadp 3, 1, 4
 ; CHECK-NEXT:    xsmaddadp 0, 3, 2
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
   %neg = fneg reassoc double %x
   %fma = call reassoc nsz double @llvm.fma.f64(double %neg, double 42.0, double -1.0)
   %add = fadd reassoc nsz double %x, 1.0
   %fma1 = call reassoc nsz double @llvm.fma.f64(double %fma, double %y, double %add)

llvm/test/CodeGen/PowerPC/fma-mutate.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
 
 declare double @llvm.sqrt.f64(double)
 
 ; Test several VSX FMA mutation opportunities.
 
 ; This is reasonable transformation since it eliminates extra register copy.
 define double @foo3_fmf(double %a) nounwind {
 ; CHECK-LABEL: foo3_fmf:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xstsqrtdp 0, 1
 ; CHECK-NEXT:    bc 12, 2, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    vspltisw 2, -3
 ; CHECK-NEXT:    xsrsqrtedp 0, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-NEXT:    lfs 3, .LCPI0_0@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; CHECK-NEXT:    lfs 4, .LCPI0_1@toc@l(3)
-; CHECK-NEXT:    xsmuldp 2, 1, 0
-; CHECK-NEXT:    xsmaddmdp 2, 0, 3
+; CHECK-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
+; CHECK-NEXT:    xvcvsxwdp 2, 34
+; CHECK-NEXT:    xsmuldp 3, 1, 0
+; CHECK-NEXT:    fmr 5, 2
+; CHECK-NEXT:    xsmaddadp 5, 3, 0
 ; CHECK-NEXT:    xsmuldp 0, 0, 4
-; CHECK-NEXT:    xsmuldp 0, 0, 2
+; CHECK-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-NEXT:    xsmuldp 1, 1, 0
-; CHECK-NEXT:    xsmaddadp 3, 1, 0
+; CHECK-NEXT:    xsmaddadp 2, 1, 0
 ; CHECK-NEXT:    xsmuldp 0, 1, 4
-; CHECK-NEXT:    xsmuldp 1, 0, 3
+; CHECK-NEXT:    xsmuldp 1, 0, 2
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    xssqrtdp 1, 1
 ; CHECK-NEXT:    blr
   %r = call contract reassoc afn ninf double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn_ieee:'
 ; GLOBALDEBUG:         fmul ninf afn {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_afn_ieee:'
 
 define float @sqrt_afn_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_afn_ieee:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xsabsdp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI11_2@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI11_2@toc@l(3)
+; FMF-NEXT:    addis 3, 2, .LCPI11_1@toc@ha
+; FMF-NEXT:    vspltisw 2, -3
+; FMF-NEXT:    lfs 2, .LCPI11_1@toc@l(3)
 ; FMF-NEXT:    fcmpu 0, 0, 2
+; FMF-NEXT:    xvcvsxwsp 2, 34
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    blt 0, .LBB11_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI11_0@toc@l(3)
-; FMF-NEXT:    addis 3, 2, .LCPI11_1@toc@ha
-; FMF-NEXT:    lfs 3, .LCPI11_1@toc@l(3)
+; FMF-NEXT:    lfs 3, .LCPI11_0@toc@l(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 0
-; FMF-NEXT:    xsmulsp 1, 1, 2
-; FMF-NEXT:    xsaddsp 0, 0, 3
+; FMF-NEXT:    xsmulsp 1, 1, 3
+; FMF-NEXT:    xsaddsp 0, 0, 2
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:  .LBB11_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_afn_ieee:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsabsdp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI11_2@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI11_2@toc@l(3)
+; GLOBAL-NEXT:    addis 3, 2, .LCPI11_1@toc@ha
+; GLOBAL-NEXT:    vspltisw 2, -3
+; GLOBAL-NEXT:    lfs 2, .LCPI11_1@toc@l(3)
 ; GLOBAL-NEXT:    fcmpu 0, 0, 2
+; GLOBAL-NEXT:    xvcvsxwsp 2, 34
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    blt 0, .LBB11_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI11_0@toc@l(3)
-; GLOBAL-NEXT:    addis 3, 2, .LCPI11_1@toc@ha
-; GLOBAL-NEXT:    lfs 3, .LCPI11_1@toc@l(3)
+; GLOBAL-NEXT:    lfs 3, .LCPI11_0@toc@l(3)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB11_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call afn ninf float @llvm.sqrt.f32(float %x)

 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_afn_preserve_sign:'
 ; GLOBALDEBUG:         fmul ninf afn {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_afn_preserve_sign:'
 
 define float @sqrt_afn_preserve_sign(float %x) #1 {
 ; FMF-LABEL: sqrt_afn_preserve_sign:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xxlxor 0, 0, 0
+; FMF-NEXT:    vspltisw 2, -3
 ; FMF-NEXT:    fcmpu 0, 1, 0
+; FMF-NEXT:    xvcvsxwsp 2, 34
 ; FMF-NEXT:    beq 0, .LBB13_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI13_0@toc@l(3)
-; FMF-NEXT:    addis 3, 2, .LCPI13_1@toc@ha
-; FMF-NEXT:    lfs 3, .LCPI13_1@toc@l(3)
+; FMF-NEXT:    lfs 3, .LCPI13_0@toc@l(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 0
-; FMF-NEXT:    xsmulsp 1, 1, 2
-; FMF-NEXT:    xsaddsp 0, 0, 3
+; FMF-NEXT:    xsmulsp 1, 1, 3
+; FMF-NEXT:    xsaddsp 0, 0, 2
 ; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:  .LBB13_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_afn_preserve_sign:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
+; GLOBAL-NEXT:    vspltisw 2, -3
 ; GLOBAL-NEXT:    fcmpu 0, 1, 0
+; GLOBAL-NEXT:    xvcvsxwsp 2, 34
 ; GLOBAL-NEXT:    beq 0, .LBB13_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI13_0@toc@l(3)
-; GLOBAL-NEXT:    addis 3, 2, .LCPI13_1@toc@ha
-; GLOBAL-NEXT:    lfs 3, .LCPI13_1@toc@l(3)
+; GLOBAL-NEXT:    lfs 3, .LCPI13_0@toc@l(3)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB13_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call afn ninf float @llvm.sqrt.f32(float %x)

 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_ieee:'
 ; GLOBALDEBUG:         fmul ninf contract afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_ieee:'
 
 define float @sqrt_fast_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_fast_ieee:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xsabsdp 0, 1
-; FMF-NEXT:    addis 3, 2, .LCPI15_2@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI15_2@toc@l(3)
+; FMF-NEXT:    addis 3, 2, .LCPI15_1@toc@ha
+; FMF-NEXT:    vspltisw 2, -3
+; FMF-NEXT:    lfs 2, .LCPI15_1@toc@l(3)
 ; FMF-NEXT:    fcmpu 0, 0, 2
+; FMF-NEXT:    xvcvsxwsp 2, 34
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    blt 0, .LBB15_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI15_0@toc@l(3)
-; FMF-NEXT:    addis 3, 2, .LCPI15_1@toc@ha
-; FMF-NEXT:    lfs 3, .LCPI15_1@toc@l(3)
+; FMF-NEXT:    lfs 3, .LCPI15_0@toc@l(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmaddasp 2, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 3
 ; FMF-NEXT:    xsmulsp 0, 0, 2
 ; FMF-NEXT:  .LBB15_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_fast_ieee:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsabsdp 0, 1
-; GLOBAL-NEXT:    addis 3, 2, .LCPI15_2@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI15_2@toc@l(3)
+; GLOBAL-NEXT:    addis 3, 2, .LCPI15_1@toc@ha
+; GLOBAL-NEXT:    vspltisw 2, -3
+; GLOBAL-NEXT:    lfs 2, .LCPI15_1@toc@l(3)
 ; GLOBAL-NEXT:    fcmpu 0, 0, 2
+; GLOBAL-NEXT:    xvcvsxwsp 2, 34
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
 ; GLOBAL-NEXT:    blt 0, .LBB15_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI15_0@toc@l(3)
-; GLOBAL-NEXT:    addis 3, 2, .LCPI15_1@toc@ha
-; GLOBAL-NEXT:    lfs 3, .LCPI15_1@toc@l(3)
+; GLOBAL-NEXT:    lfs 3, .LCPI15_0@toc@l(3)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB15_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call contract reassoc afn ninf float @llvm.sqrt.f32(float %x)

 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
 ; GLOBALDEBUG:         fmul ninf contract afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
 
 define float @sqrt_fast_preserve_sign(float %x) #1 {
 ; FMF-LABEL: sqrt_fast_preserve_sign:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xxlxor 0, 0, 0
+; FMF-NEXT:    vspltisw 2, -3
 ; FMF-NEXT:    fcmpu 0, 1, 0
+; FMF-NEXT:    xvcvsxwsp 2, 34
 ; FMF-NEXT:    beq 0, .LBB16_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
-; FMF-NEXT:    lfs 2, .LCPI16_0@toc@l(3)
-; FMF-NEXT:    addis 3, 2, .LCPI16_1@toc@ha
-; FMF-NEXT:    lfs 3, .LCPI16_1@toc@l(3)
+; FMF-NEXT:    lfs 3, .LCPI16_0@toc@l(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmaddasp 2, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 1, 3
 ; FMF-NEXT:    xsmulsp 0, 0, 2
 ; FMF-NEXT:  .LBB16_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_fast_preserve_sign:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
+; GLOBAL-NEXT:    vspltisw 2, -3
 ; GLOBAL-NEXT:    fcmpu 0, 1, 0
+; GLOBAL-NEXT:    xvcvsxwsp 2, 34
 ; GLOBAL-NEXT:    beq 0, .LBB16_2
 ; GLOBAL-NEXT:  # %bb.1:
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
-; GLOBAL-NEXT:    lfs 2, .LCPI16_0@toc@l(3)
-; GLOBAL-NEXT:    addis 3, 2, .LCPI16_1@toc@ha
-; GLOBAL-NEXT:    lfs 3, .LCPI16_1@toc@l(3)
+; GLOBAL-NEXT:    lfs 3, .LCPI16_0@toc@l(3)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB16_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
   %rt = call contract reassoc ninf afn float @llvm.sqrt.f32(float %x)

llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll

 ; P8-NEXT:    stdu r1, -32(r1)
 ; P8-NEXT:    std r0, 48(r1)
 ; P8-NEXT:    bl __gnu_f2h_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    clrldi r3, r3, 48
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
 ; P8-NEXT:    xxlxor f0, f0, f0
+; P8-NEXT:    vspltisw v2, 1
 ; P8-NEXT:    fcmpu cr0, f1, f0
+; P8-NEXT:    xvcvsxwsp vs1, vs34
 ; P8-NEXT:    beq cr0, .LBB20_2
 ; P8-NEXT:  # %bb.1:
-; P8-NEXT:    addis r3, r2, .LCPI20_0@toc@ha
-; P8-NEXT:    lfs f0, .LCPI20_0@toc@l(r3)
+; P8-NEXT:    fmr f0, f1
 ; P8-NEXT:  .LBB20_2:
 ; P8-NEXT:    fmr f1, f0
 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; CHECK-LABEL: PR40273:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdphp f0, f1
+; CHECK-NEXT:    vspltisw v2, 1
 ; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    clrlwi r3, r3, 16
 ; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    xscvhpdp f0, f0
 ; CHECK-NEXT:    fcmpu cr0, f0, f1
+; CHECK-NEXT:    xvcvsxwsp vs0, vs34
 ; CHECK-NEXT:    beqlr cr0
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    addis r3, r2, .LCPI20_0@toc@ha
-; CHECK-NEXT:    lfs f1, .LCPI20_0@toc@l(r3)
+; CHECK-NEXT:    fmr f1, f0
 ; CHECK-NEXT:    blr
 ;
 ; SOFT-LABEL: PR40273:
 ; SOFT:       # %bb.0:
 ; SOFT-NEXT:    mflr r0
 ; SOFT-NEXT:    stdu r1, -32(r1)
 ; SOFT-NEXT:    clrldi r3, r3, 48
 ; SOFT-NEXT:    std r0, 48(r1)

llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 ; Function Attrs: nounwind
 define dso_local void @test(ptr nocapture readonly %Fptr, ptr nocapture %Vptr) local_unnamed_addr #0 !dbg !10 {
 ; CHECK-LABEL: test:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:          #DEBUG_VALUE: test:Fptr <- $x3
-; CHECK-NEXT:          #DEBUG_VALUE: test:Vptr <- $x4
-; CHECK-NEXT:          addis 5, 2, .LCPI0_0@toc@ha
+; CHECK:         .loc 1 1 0 # test.c:1:0
+; CHECK-NEXT:    .cfi_sections .debug_frame
+; CHECK-NEXT:    .cfi_startproc
+; CHECK-NEXT:  .Lfunc_gep0:
+; CHECK-NEXT:    addis 2, 12, .TOC.-.Lfunc_gep0@ha
+; CHECK-NEXT:    addi 2, 2, .TOC.-.Lfunc_gep0@l
+; CHECK-NEXT:  .Lfunc_lep0:
+; CHECK-NEXT:    .localentry test, .Lfunc_lep0-.Lfunc_gep0
+; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    #DEBUG_VALUE: test:Fptr <- $x3
+; CHECK-NEXT:    #DEBUG_VALUE: test:Vptr <- $x4
+; CHECK-NEXT:    vspltisw 2, 1
 ; CHECK-NEXT:  .Ltmp0:
-; CHECK-NEXT:          .loc    1 2 38 prologue_end
-; CHECK-NEXT:          lfs 0, 0(3)
-; CHECK-NEXT:          addis 3, 2, .LCPI0_1@toc@ha
+; CHECK-NEXT:    .loc 1 2 38 prologue_end # test.c:2:38
+; CHECK-NEXT:    lfs 1, 0(3)
+; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:  .Ltmp1:
-; CHECK-NEXT:          .loc    1 0 38 is_stmt 0
-; CHECK-NEXT:          lfs 1, .LCPI0_0@toc@l(5)
-; CHECK-NEXT:          lfd 2, .LCPI0_1@toc@l(3)
-; CHECK-NEXT:          .loc    1 2 27
-; CHECK-NEXT:          xssubdp 1, 1, 0
-; CHECK-NEXT:          .loc    1 2 45
-; CHECK-NEXT:          xsadddp 1, 1, 2
+; CHECK-NEXT:    .loc 1 0 38 is_stmt 0 # test.c:0:38
+; CHECK-NEXT:    lfd 2, .LCPI0_0@toc@l(3)
+; CHECK-NEXT:    xvcvsxwdp 0, 34
+; CHECK-NEXT:    .loc 1 2 27 # test.c:2:27
+; CHECK-NEXT:    xssubdp 0, 0, 1
+; CHECK-NEXT:    .loc 1 2 45 # test.c:2:45
+; CHECK-NEXT:    xsadddp 0, 0, 2
 ; CHECK-NEXT:  .Ltmp2:
-; CHECK-NEXT:          #DEBUG_VALUE: test:Val <- undef
-; CHECK-NEXT:          .loc    1 0 45
-; CHECK-NEXT:          xxlxor 2, 2, 2
-; CHECK-NEXT:          .loc    1 3 26 is_stmt 1
-; CHECK-NEXT:          xxmrghd 0, 0, 2
-; CHECK-NEXT:          xxmrghd 1, 2, 1
-; CHECK-NEXT:          xvcvdpsp 34, 0
-; CHECK-NEXT:          xvcvdpsp 35, 1
-; CHECK-NEXT:          vmrgew 2, 2, 3
-; CHECK-NEXT:          .loc    1 3 9 is_stmt 0
-; CHECK-NEXT:          xxswapd  0, 34
-; CHECK-NEXT:          stxvd2x 0, 0, 4
-; CHECK-NEXT:          .loc    1 4 1 is_stmt 1
-; CHECK-NEXT:          blr
+; CHECK-NEXT:    #DEBUG_VALUE: test:Val <- undef
+; CHECK-NEXT:    .loc 1 0 45 # test.c:0:45
+; CHECK-NEXT:    xxlxor 2, 2, 2
+; CHECK-NEXT:    .loc 1 3 26 is_stmt 1 # test.c:3:26
+; CHECK-NEXT:    xxmrghd 1, 1, 2
+; CHECK-NEXT:    xxmrghd 0, 2, 0
+; CHECK-NEXT:    xvcvdpsp 34, 1
+; CHECK-NEXT:    xvcvdpsp 35, 0
+; CHECK-NEXT:    vmrgew 2, 2, 3
+; CHECK-NEXT:    .loc 1 3 9 is_stmt 0 # test.c:3:9
+; CHECK-NEXT:    xxswapd 0, 34
+; CHECK-NEXT:    stxvd2x 0, 0, 4
+; CHECK-NEXT:    .loc 1 4 1 is_stmt 1 # test.c:4:1
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .Ltmp3:
 entry:
   call void @llvm.dbg.value(metadata ptr %Fptr, metadata !19, metadata !DIExpression()), !dbg !22
   call void @llvm.dbg.value(metadata ptr %Vptr, metadata !20, metadata !DIExpression()), !dbg !22
   %0 = load float, ptr %Fptr, align 4, !dbg !23, !tbaa !24
   %conv = fpext float %0 to double, !dbg !28
   %sub = fsub double 1.000000e+00, %conv, !dbg !29
   %sub1 = fadd double %sub, -4.300000e+00, !dbg !30
   %conv2 = fptrunc double %sub1 to float, !dbg !31

llvm/test/CodeGen/PowerPC/p10-spill-crun.ll

 ; CHECK-NEXT:  .LBB0_13: # %bb42
 ; CHECK-NEXT:    xsmulsp f0, f1, f0
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    b .LBB0_15
 ; CHECK-NEXT:  .LBB0_14: # %bb41
 ; CHECK-NEXT:    # implicit-def: $r3
 ; CHECK-NEXT:  .LBB0_15: # %bb50
+; CHECK-NEXT:    vspltisw v2, -1
 ; CHECK-NEXT:    li r4, 0
-; CHECK-NEXT:    xxspltidp vs3, -1082130432
-; CHECK-NEXT:    xxspltidp vs4, -1082130432
 ; CHECK-NEXT:    extsh r9, r3
 ; CHECK-NEXT:    extsw r6, r28
 ; CHECK-NEXT:    li r5, 0
-; CHECK-NEXT:    li r7, 0
 ; CHECK-NEXT:    std r30, 104(r1)
 ; CHECK-NEXT:    std r29, 96(r1)
+; CHECK-NEXT:    std r4, 152(r1)
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    li r7, 0
 ; CHECK-NEXT:    li r8, 0
 ; CHECK-NEXT:    li r10, 0
 ; CHECK-NEXT:    xxlxor f1, f1, f1
-; CHECK-NEXT:    std r4, 152(r1)
-; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    xvcvsxwsp vs3, v2
 ; CHECK-NEXT:    std r4, 112(r1)
 ; CHECK-NEXT:    li r4, 1024
+; CHECK-NEXT:    fmr f4, f3
 ; CHECK-NEXT:    bl call_4@notoc
 ; CHECK-NEXT:  .LBB0_16: # %bb54
 ; CHECK-NEXT:    bc 12, 4*cr2+un, .LBB0_19
 ; CHECK-NEXT:  # %bb.17: # %bb56
 ; CHECK-NEXT:    ld r30, 208(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r29, 200(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r28, 192(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r27, 184(r1) # 8-byte Folded Reload

 ; CHECK-BE-NEXT:  .LBB0_13: # %bb42
 ; CHECK-BE-NEXT:    xsmulsp f0, f1, f0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    b .LBB0_15
 ; CHECK-BE-NEXT:  .LBB0_14: # %bb41
 ; CHECK-BE-NEXT:    # implicit-def: $r3
 ; CHECK-BE-NEXT:  .LBB0_15: # %bb50
+; CHECK-BE-NEXT:    vspltisw v2, -1
 ; CHECK-BE-NEXT:    li r4, 0
-; CHECK-BE-NEXT:    xxspltidp vs3, -1082130432
-; CHECK-BE-NEXT:    xxspltidp vs4, -1082130432
 ; CHECK-BE-NEXT:    extsh r9, r3
 ; CHECK-BE-NEXT:    extsw r6, r28
 ; CHECK-BE-NEXT:    li r5, 0
-; CHECK-BE-NEXT:    li r7, 0
 ; CHECK-BE-NEXT:    std r30, 120(r1)
 ; CHECK-BE-NEXT:    std r29, 112(r1)
+; CHECK-BE-NEXT:    std r4, 168(r1)
+; CHECK-BE-NEXT:    li r4, -1
+; CHECK-BE-NEXT:    li r7, 0
 ; CHECK-BE-NEXT:    li r8, 0
 ; CHECK-BE-NEXT:    li r10, 0
 ; CHECK-BE-NEXT:    xxlxor f1, f1, f1
-; CHECK-BE-NEXT:    std r4, 168(r1)
-; CHECK-BE-NEXT:    li r4, -1
+; CHECK-BE-NEXT:    xvcvsxwsp vs3, v2
 ; CHECK-BE-NEXT:    std r4, 128(r1)
 ; CHECK-BE-NEXT:    li r4, 1024
+; CHECK-BE-NEXT:    fmr f4, f3
 ; CHECK-BE-NEXT:    bl call_4
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:  .LBB0_16: # %bb54
 ; CHECK-BE-NEXT:    bc 12, 4*cr2+un, .LBB0_19
 ; CHECK-BE-NEXT:  # %bb.17: # %bb56
 ; CHECK-BE-NEXT:    ld r30, 224(r1) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    ld r29, 216(r1) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    ld r28, 208(r1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s
 ; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s
 
 declare float @llvm.pow.f32 (float, float);
 declare double @llvm.pow.f64 (double, double);
 
 ; fast-math powf with 0.25
 ; TODO: pow->sqrt conversion for AIX
 define float @llvmintr_powf_f32_fast025(float %a) #1 {
 ; CHECK-LNX-LABEL: llvmintr_powf_f32_fast025:
 ; CHECK-LNX:       # %bb.0: # %entry
 ; CHECK-LNX-NEXT:    xsrsqrtesp 0, 1
+; CHECK-LNX-NEXT:    vspltisw 2, -3
 ; CHECK-LNX-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-LNX-NEXT:    lfs 3, .LCPI0_0@toc@l(3)
+; CHECK-LNX-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
 ; CHECK-LNX-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; CHECK-LNX-NEXT:    lfs 4, .LCPI0_1@toc@l(3)
-; CHECK-LNX-NEXT:    addis 3, 2, .LCPI0_2@toc@ha
-; CHECK-LNX-NEXT:    lfs 5, .LCPI0_2@toc@l(3)
-; CHECK-LNX-NEXT:    xsmulsp 2, 1, 0
+; CHECK-LNX-NEXT:    lfs 5, .LCPI0_1@toc@l(3)
+; CHECK-LNX-NEXT:    xvcvsxwsp 2, 34
+; CHECK-LNX-NEXT:    xsmulsp 3, 1, 0
 ; CHECK-LNX-NEXT:    xsabsdp 1, 1
-; CHECK-LNX-NEXT:    xsmulsp 0, 2, 0
-; CHECK-LNX-NEXT:    xsmulsp 2, 2, 3
+; CHECK-LNX-NEXT:    xsmulsp 0, 3, 0
+; CHECK-LNX-NEXT:    xsmulsp 3, 3, 4
 ; CHECK-LNX-NEXT:    xssubsp 1, 1, 5
-; CHECK-LNX-NEXT:    xsaddsp 0, 0, 4
-; CHECK-LNX-NEXT:    xsmulsp 0, 2, 0
-; CHECK-LNX-NEXT:    xxlxor 2, 2, 2
-; CHECK-LNX-NEXT:    fsel 0, 1, 0, 2
+; CHECK-LNX-NEXT:    xsaddsp 0, 0, 2
+; CHECK-LNX-NEXT:    xsmulsp 0, 3, 0
+; CHECK-LNX-NEXT:    xxlxor 3, 3, 3
+; CHECK-LNX-NEXT:    fsel 0, 1, 0, 3
 ; CHECK-LNX-NEXT:    xsrsqrtesp 1, 0
 ; CHECK-LNX-NEXT:    xsmulsp 6, 0, 1
 ; CHECK-LNX-NEXT:    xsabsdp 0, 0
 ; CHECK-LNX-NEXT:    xsmulsp 1, 6, 1
-; CHECK-LNX-NEXT:    xsmulsp 3, 6, 3
+; CHECK-LNX-NEXT:    xsmulsp 4, 6, 4
 ; CHECK-LNX-NEXT:    xssubsp 0, 0, 5
-; CHECK-LNX-NEXT:    xsaddsp 1, 1, 4
-; CHECK-LNX-NEXT:    xsmulsp 1, 3, 1
-; CHECK-LNX-NEXT:    fsel 1, 0, 1, 2
+; CHECK-LNX-NEXT:    xsaddsp 1, 1, 2
+; CHECK-LNX-NEXT:    xsmulsp 1, 4, 1
+; CHECK-LNX-NEXT:    fsel 1, 0, 1, 3
 ; CHECK-LNX-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: llvmintr_powf_f32_fast025:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mflr 0
 ; CHECK-AIX-NEXT:    stwu 1, -64(1)
 ; CHECK-AIX-NEXT:    lwz 3, L..C0(2) # %const.0
 ; CHECK-AIX-NEXT:    stw 0, 72(1)
entry:
   ret float %call
 }
 
 ; fast-math pow with 0.25
 ; TODO: pow->sqrt conversion for AIX
 define double @llvmintr_pow_f64_fast025(double %a) #1 {
 ; CHECK-LNX-LABEL: llvmintr_pow_f64_fast025:
 ; CHECK-LNX:       # %bb.0: # %entry
+; CHECK-LNX-NEXT:    vspltisw 2, -3
 ; CHECK-LNX-NEXT:    xstsqrtdp 0, 1
 ; CHECK-LNX-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
-; CHECK-LNX-NEXT:    addis 4, 2, .LCPI1_1@toc@ha
 ; CHECK-LNX-NEXT:    lfs 0, .LCPI1_0@toc@l(3)
-; CHECK-LNX-NEXT:    lfs 2, .LCPI1_1@toc@l(4)
+; CHECK-LNX-NEXT:    xvcvsxwdp 2, 34
 ; CHECK-LNX-NEXT:    bc 12, 2, .LBB1_3
 ; CHECK-LNX-NEXT:  # %bb.1: # %entry
 ; CHECK-LNX-NEXT:    xsrsqrtedp 3, 1
 ; CHECK-LNX-NEXT:    xsmuldp 4, 1, 3
 ; CHECK-LNX-NEXT:    xsmuldp 4, 4, 3
 ; CHECK-LNX-NEXT:    xsmuldp 3, 3, 0
 ; CHECK-LNX-NEXT:    xsadddp 4, 4, 2
 ; CHECK-LNX-NEXT:    xsmuldp 3, 3, 4

 }
 
 ; fast-math powf with 0.75
 ; TODO: pow->sqrt conversion for AIX
 define float @llvmintr_powf_f32_fast075(float %a) #1 {
 ; CHECK-LNX-LABEL: llvmintr_powf_f32_fast075:
 ; CHECK-LNX:       # %bb.0: # %entry
 ; CHECK-LNX-NEXT:    xsrsqrtesp 0, 1
+; CHECK-LNX-NEXT:    vspltisw 2, -3
 ; CHECK-LNX-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
-; CHECK-LNX-NEXT:    lfs 3, .LCPI2_0@toc@l(3)
+; CHECK-LNX-NEXT:    lfs 4, .LCPI2_0@toc@l(3)
 ; CHECK-LNX-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
-; CHECK-LNX-NEXT:    lfs 4, .LCPI2_1@toc@l(3)
-; CHECK-LNX-NEXT:    addis 3, 2, .LCPI2_2@toc@ha
-; CHECK-LNX-NEXT:    lfs 5, .LCPI2_2@toc@l(3)
-; CHECK-LNX-NEXT:    xsmulsp 2, 1, 0
+; CHECK-LNX-NEXT:    lfs 5, .LCPI2_1@toc@l(3)
+; CHECK-LNX-NEXT:    xvcvsxwsp 2, 34
+; CHECK-LNX-NEXT:    xsmulsp 3, 1, 0
 ; CHECK-LNX-NEXT:    xsabsdp 1, 1
-; CHECK-LNX-NEXT:    xsmulsp 0, 2, 0
-; CHECK-LNX-NEXT:    xsmulsp 2, 2, 3
+; CHECK-LNX-NEXT:    xsmulsp 0, 3, 0
+; CHECK-LNX-NEXT:    xsmulsp 3, 3, 4
 ; CHECK-LNX-NEXT:    xssubsp 1, 1, 5
-; CHECK-LNX-NEXT:    xsaddsp 0, 0, 4
-; CHECK-LNX-NEXT:    xsmulsp 0, 2, 0
-; CHECK-LNX-NEXT:    xxlxor 2, 2, 2
-; CHECK-LNX-NEXT:    fsel 0, 1, 0, 2
+; CHECK-LNX-NEXT:    xsaddsp 0, 0, 2
+; CHECK-LNX-NEXT:    xsmulsp 0, 3, 0
+; CHECK-LNX-NEXT:    xxlxor 3, 3, 3
+; CHECK-LNX-NEXT:    fsel 0, 1, 0, 3
 ; CHECK-LNX-NEXT:    xsrsqrtesp 1, 0
 ; CHECK-LNX-NEXT:    xsmulsp 6, 0, 1
 ; CHECK-LNX-NEXT:    xsmulsp 1, 6, 1
-; CHECK-LNX-NEXT:    xsmulsp 3, 6, 3
-; CHECK-LNX-NEXT:    xsaddsp 1, 1, 4
-; CHECK-LNX-NEXT:    xsabsdp 4, 0
-; CHECK-LNX-NEXT:    xsmulsp 1, 3, 1
-; CHECK-LNX-NEXT:    xssubsp 3, 4, 5
-; CHECK-LNX-NEXT:    fsel 1, 3, 1, 2
+; CHECK-LNX-NEXT:    xsmulsp 4, 6, 4
+; CHECK-LNX-NEXT:    xsaddsp 1, 1, 2
+; CHECK-LNX-NEXT:    xsabsdp 2, 0
+; CHECK-LNX-NEXT:    xsmulsp 1, 4, 1
+; CHECK-LNX-NEXT:    xssubsp 2, 2, 5
+; CHECK-LNX-NEXT:    fsel 1, 2, 1, 3
 ; CHECK-LNX-NEXT:    xsmulsp 1, 0, 1
 ; CHECK-LNX-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: llvmintr_powf_f32_fast075:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mflr 0
 ; CHECK-AIX-NEXT:    stwu 1, -64(1)
 ; CHECK-AIX-NEXT:    lwz 3, L..C2(2) # %const.0
entry:
   ret float %call
 }
 
 ; fast-math pow with 0.75
 ; TODO: pow->sqrt conversion for AIX
 define double @llvmintr_pow_f64_fast075(double %a) #1 {
 ; CHECK-LNX-LABEL: llvmintr_pow_f64_fast075:
 ; CHECK-LNX:       # %bb.0: # %entry
+; CHECK-LNX-NEXT:    vspltisw 2, -3
 ; CHECK-LNX-NEXT:    xstsqrtdp 0, 1
 ; CHECK-LNX-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-LNX-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
 ; CHECK-LNX-NEXT:    lfs 0, .LCPI3_0@toc@l(3)
-; CHECK-LNX-NEXT:    lfs 2, .LCPI3_1@toc@l(4)
+; CHECK-LNX-NEXT:    xvcvsxwdp 2, 34
 ; CHECK-LNX-NEXT:    bc 12, 2, .LBB3_3
 ; CHECK-LNX-NEXT:  # %bb.1: # %entry
 ; CHECK-LNX-NEXT:    xsrsqrtedp 3, 1
 ; CHECK-LNX-NEXT:    xsmuldp 4, 1, 3
 ; CHECK-LNX-NEXT:    xsmuldp 4, 4, 3
 ; CHECK-LNX-NEXT:    xsmuldp 3, 3, 0
 ; CHECK-LNX-NEXT:    xsadddp 4, 4, 2
 ; CHECK-LNX-NEXT:    xsmuldp 3, 3, 4

llvm/test/CodeGen/PowerPC/recipest.ll

 ; CHECK-P7-NEXT:    fmadd 2, 2, 0, 4
 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo_fmf:
 ; CHECK-P8:       # %bb.0:
+; CHECK-P8-NEXT:    vspltisw 2, -3
 ; CHECK-P8-NEXT:    xsrsqrtedp 0, 2
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; CHECK-P8-NEXT:    lfs 5, .LCPI0_1@toc@l(3)
-; CHECK-P8-NEXT:    fmr 6, 4
-; CHECK-P8-NEXT:    xsmuldp 3, 2, 0
-; CHECK-P8-NEXT:    xsmaddadp 6, 3, 0
+; CHECK-P8-NEXT:    lfs 5, .LCPI0_0@toc@l(3)
+; CHECK-P8-NEXT:    xvcvsxwdp 3, 34
+; CHECK-P8-NEXT:    xsmuldp 4, 2, 0
+; CHECK-P8-NEXT:    fmr 6, 3
+; CHECK-P8-NEXT:    xsmaddadp 6, 4, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 6
 ; CHECK-P8-NEXT:    xsmuldp 2, 2, 0
-; CHECK-P8-NEXT:    xsmaddadp 4, 2, 0
+; CHECK-P8-NEXT:    xsmaddadp 3, 2, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
-; CHECK-P8-NEXT:    xsmuldp 0, 0, 4
+; CHECK-P8-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P8-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foo_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsrsqrtedp 0, 2
+; CHECK-P9-NEXT:    vspltisw 2, -3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    lfs 4, .LCPI0_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
 ; CHECK-P9-NEXT:    xsmuldp 3, 2, 0
+; CHECK-P9-NEXT:    xvcvsxwdp 4, 34
 ; CHECK-P9-NEXT:    fmr 5, 4
 ; CHECK-P9-NEXT:    xsmaddadp 5, 3, 0
-; CHECK-P9-NEXT:    lfs 3, .LCPI0_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 3, .LCPI0_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P9-NEXT:    xsmuldp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    blr

 ; CHECK-P7-NEXT:    fmuls 0, 0, 4
 ; CHECK-P7-NEXT:    fmuls 0, 0, 2
 ; CHECK-P7-NEXT:    fmul 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foof_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 2
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI3_1@toc@l(3)
+; CHECK-P8-NEXT:    vspltisw 2, -3
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; CHECK-P8-NEXT:    lfs 4, .LCPI3_0@toc@l(3)
+; CHECK-P8-NEXT:    xvcvsxwsp 3, 34
 ; CHECK-P8-NEXT:    xsmulsp 2, 2, 0
-; CHECK-P8-NEXT:    xsmulsp 3, 0, 3
-; CHECK-P8-NEXT:    xsmaddasp 4, 2, 0
-; CHECK-P8-NEXT:    xsmulsp 0, 3, 4
+; CHECK-P8-NEXT:    xsmaddasp 3, 2, 0
+; CHECK-P8-NEXT:    xsmulsp 0, 0, 4
+; CHECK-P8-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P8-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foof_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsrsqrtesp 0, 2
+; CHECK-P9-NEXT:    vspltisw 2, -3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
-; CHECK-P9-NEXT:    lfs 3, .LCPI3_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
 ; CHECK-P9-NEXT:    xsmulsp 2, 2, 0
+; CHECK-P9-NEXT:    xvcvsxwsp 3, 34
 ; CHECK-P9-NEXT:    xsmaddasp 3, 2, 0
-; CHECK-P9-NEXT:    lfs 2, .LCPI3_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, .LCPI3_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
   %x = call contract reassoc arcp float @llvm.sqrt.f32(float %b)
   %y = fpext float %x to double
   %r = fdiv contract reassoc arcp double %a, %y
   ret double %r

 ; CHECK-P7-NEXT:    fmul 0, 0, 5
 ; CHECK-P7-NEXT:    fmul 0, 0, 2
 ; CHECK-P7-NEXT:    frsp 0, 0
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: food_fmf:
 ; CHECK-P8:       # %bb.0:
+; CHECK-P8-NEXT:    vspltisw 2, -3
 ; CHECK-P8-NEXT:    xsrsqrtedp 0, 2
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
-; CHECK-P8-NEXT:    lfs 5, .LCPI5_1@toc@l(3)
-; CHECK-P8-NEXT:    fmr 6, 4
-; CHECK-P8-NEXT:    xsmuldp 3, 2, 0
-; CHECK-P8-NEXT:    xsmaddadp 6, 3, 0
+; CHECK-P8-NEXT:    lfs 5, .LCPI5_0@toc@l(3)
+; CHECK-P8-NEXT:    xvcvsxwdp 3, 34
+; CHECK-P8-NEXT:    xsmuldp 4, 2, 0
+; CHECK-P8-NEXT:    fmr 6, 3
+; CHECK-P8-NEXT:    xsmaddadp 6, 4, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 6
 ; CHECK-P8-NEXT:    xsmuldp 2, 2, 0
-; CHECK-P8-NEXT:    xsmaddadp 4, 2, 0
+; CHECK-P8-NEXT:    xsmaddadp 3, 2, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
-; CHECK-P8-NEXT:    xsmuldp 0, 0, 4
+; CHECK-P8-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P8-NEXT:    xsrsp 0, 0
 ; CHECK-P8-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: food_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsrsqrtedp 0, 2
+; CHECK-P9-NEXT:    vspltisw 2, -3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-P9-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
 ; CHECK-P9-NEXT:    xsmuldp 3, 2, 0
+; CHECK-P9-NEXT:    xvcvsxwdp 4, 34
 ; CHECK-P9-NEXT:    fmr 5, 4
 ; CHECK-P9-NEXT:    xsmaddadp 5, 3, 0
-; CHECK-P9-NEXT:    lfs 3, .LCPI5_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 3, .LCPI5_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P9-NEXT:    xsmuldp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsrsp 0, 0
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0

 ; CHECK-P7-NEXT:    fmuls 0, 0, 4
 ; CHECK-P7-NEXT:    fmuls 0, 0, 2
 ; CHECK-P7-NEXT:    fmuls 1, 1, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: goo_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 2
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI7_1@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI7_1@toc@l(3)
+; CHECK-P8-NEXT:    vspltisw 2, -3
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
 ; CHECK-P8-NEXT:    lfs 4, .LCPI7_0@toc@l(3)
+; CHECK-P8-NEXT:    xvcvsxwsp 3, 34
 ; CHECK-P8-NEXT:    xsmulsp 2, 2, 0
-; CHECK-P8-NEXT:    xsmulsp 3, 0, 3
-; CHECK-P8-NEXT:    xsmaddasp 4, 2, 0
-; CHECK-P8-NEXT:    xsmulsp 0, 3, 4
+; CHECK-P8-NEXT:    xsmaddasp 3, 2, 0
+; CHECK-P8-NEXT:    xsmulsp 0, 0, 4
+; CHECK-P8-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P8-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: goo_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsrsqrtesp 0, 2
+; CHECK-P9-NEXT:    vspltisw 2, -3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; CHECK-P9-NEXT:    lfs 3, .LCPI7_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI7_1@toc@ha
 ; CHECK-P9-NEXT:    xsmulsp 2, 2, 0
+; CHECK-P9-NEXT:    xvcvsxwsp 3, 34
 ; CHECK-P9-NEXT:    xsmaddasp 3, 2, 0
-; CHECK-P9-NEXT:    lfs 2, .LCPI7_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, .LCPI7_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
   %x = call contract reassoc arcp float @llvm.sqrt.f32(float %b)
   %r = fdiv contract reassoc arcp float %a, %x
   ret float %r
 }

 ; CHECK-P7-NEXT:    fnmsubs 0, 2, 4, 0
 ; CHECK-P7-NEXT:    fmadds 0, 1, 0, 4
 ; CHECK-P7-NEXT:    fmuls 1, 3, 0
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: rsqrt_fmul_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 1
+; CHECK-P8-NEXT:    vspltisw 2, -3
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI10_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI10_1@toc@ha
-; CHECK-P8-NEXT:    lfs 5, .LCPI10_1@toc@l(3)
+; CHECK-P8-NEXT:    lfs 5, .LCPI10_0@toc@l(3)
+; CHECK-P8-NEXT:    xvcvsxwsp 4, 34
 ; CHECK-P8-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P8-NEXT:    xsmaddasp 4, 1, 0
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 5
 ; CHECK-P8-NEXT:    xsresp 1, 2
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmulsp 4, 0, 1
 ; CHECK-P8-NEXT:    xsnmsubasp 0, 2, 4
 ; CHECK-P8-NEXT:    xsmaddasp 4, 1, 0
 ; CHECK-P8-NEXT:    xsmulsp 1, 3, 4
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: rsqrt_fmul_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsrsqrtesp 0, 1
+; CHECK-P9-NEXT:    vspltisw 2, -3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI10_0@toc@ha
-; CHECK-P9-NEXT:    lfs 4, .LCPI10_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI10_1@toc@ha
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
+; CHECK-P9-NEXT:    xvcvsxwsp 4, 34
 ; CHECK-P9-NEXT:    xsmaddasp 4, 1, 0
-; CHECK-P9-NEXT:    lfs 1, .LCPI10_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 1, .LCPI10_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 1
 ; CHECK-P9-NEXT:    xsresp 1, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmulsp 4, 0, 1
 ; CHECK-P9-NEXT:    xsnmsubasp 0, 2, 4
 ; CHECK-P9-NEXT:    xsmaddasp 4, 1, 0
 ; CHECK-P9-NEXT:    xsmulsp 1, 3, 4
 ; CHECK-P9-NEXT:    blr

 ; CHECK-P7-NEXT:    fnmsub 0, 0, 3, 0
 ; CHECK-P7-NEXT:    fmul 3, 1, 0
 ; CHECK-P7-NEXT:    fnmsub 1, 2, 3, 1
 ; CHECK-P7-NEXT:    fmadd 1, 0, 1, 3
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo2_fmf:
 ; CHECK-P8:       # %bb.0:
+; CHECK-P8-NEXT:    vspltisw 2, -1
 ; CHECK-P8-NEXT:    xsredp 3, 2
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
-; CHECK-P8-NEXT:    lfs 0, .LCPI14_0@toc@l(3)
+; CHECK-P8-NEXT:    xvcvsxwdp 0, 34
 ; CHECK-P8-NEXT:    xsmaddadp 0, 2, 3
 ; CHECK-P8-NEXT:    xsnmsubadp 3, 3, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 1, 3
 ; CHECK-P8-NEXT:    xsnmsubadp 1, 2, 0
 ; CHECK-P8-NEXT:    xsmaddadp 0, 3, 1
 ; CHECK-P8-NEXT:    fmr 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foo2_fmf:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI14_0@toc@ha
+; CHECK-P9-NEXT:    vspltisw 2, -1
 ; CHECK-P9-NEXT:    xsredp 3, 2
-; CHECK-P9-NEXT:    lfs 0, .LCPI14_0@toc@l(3)
+; CHECK-P9-NEXT:    xvcvsxwdp 0, 34
 ; CHECK-P9-NEXT:    xsmaddadp 0, 2, 3
 ; CHECK-P9-NEXT:    xsnmsubadp 3, 3, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 3
 ; CHECK-P9-NEXT:    xsnmsubadp 1, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 0, 3, 1
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
   %r = fdiv contract reassoc arcp nsz ninf double %a, %b

 ; CHECK-P7-NEXT:    fsqrt 1, 1
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo3_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xstsqrtdp 0, 1
 ; CHECK-P8-NEXT:    bc 12, 2, .LBB20_2
 ; CHECK-P8-NEXT:  # %bb.1:
+; CHECK-P8-NEXT:    vspltisw 2, -3
 ; CHECK-P8-NEXT:    xsrsqrtedp 0, 1
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI20_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI20_1@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI20_1@toc@l(3)
-; CHECK-P8-NEXT:    fmr 5, 3
-; CHECK-P8-NEXT:    xsmuldp 2, 1, 0
-; CHECK-P8-NEXT:    xsmaddadp 5, 2, 0
+; CHECK-P8-NEXT:    lfs 4, .LCPI20_0@toc@l(3)
+; CHECK-P8-NEXT:    xvcvsxwdp 2, 34
+; CHECK-P8-NEXT:    xsmuldp 3, 1, 0
+; CHECK-P8-NEXT:    fmr 5, 2
+; CHECK-P8-NEXT:    xsmaddadp 5, 3, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 1, 1, 0
-; CHECK-P8-NEXT:    xsmaddadp 3, 1, 0
+; CHECK-P8-NEXT:    xsmaddadp 2, 1, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 1, 4
-; CHECK-P8-NEXT:    xsmuldp 1, 0, 3
+; CHECK-P8-NEXT:    xsmuldp 1, 0, 2
 ; CHECK-P8-NEXT:    blr
 ; CHECK-P8-NEXT:  .LBB20_2:
 ; CHECK-P8-NEXT:    xssqrtdp 1, 1
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foo3_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xstsqrtdp 0, 1
 ; CHECK-P9-NEXT:    bc 12, 2, .LBB20_2
 ; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    xsrsqrtedp 0, 1
+; CHECK-P9-NEXT:    vspltisw 2, -3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-P9-NEXT:    lfs 3, .LCPI20_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI20_1@toc@ha
 ; CHECK-P9-NEXT:    xsmuldp 2, 1, 0
+; CHECK-P9-NEXT:    xvcvsxwdp 3, 34
 ; CHECK-P9-NEXT:    fmr 4, 3
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
-; CHECK-P9-NEXT:    lfs 2, .LCPI20_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, .LCPI20_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 2
 ; CHECK-P9-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB20_2:

 ; CHECK-P7-NEXT:    blr
 ; CHECK-P7-NEXT:  .LBB21_2:
 ; CHECK-P7-NEXT:    fsqrt 1, 1
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: foo3_fmf_crbits_off:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsabsdp 0, 1
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI21_2@toc@ha
-; CHECK-P8-NEXT:    lfd 2, .LCPI21_2@toc@l(3)
+; CHECK-P8-NEXT:    addis 3, 2, .LCPI21_1@toc@ha
+; CHECK-P8-NEXT:    lfd 2, .LCPI21_1@toc@l(3)
 ; CHECK-P8-NEXT:    xscmpudp 0, 0, 2
 ; CHECK-P8-NEXT:    blt 0, .LBB21_2
 ; CHECK-P8-NEXT:  # %bb.1:
+; CHECK-P8-NEXT:    vspltisw 2, -3
 ; CHECK-P8-NEXT:    xsrsqrtedp 0, 1
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI21_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI21_1@toc@ha
-; CHECK-P8-NEXT:    lfs 4, .LCPI21_1@toc@l(3)
-; CHECK-P8-NEXT:    fmr 5, 3
-; CHECK-P8-NEXT:    xsmuldp 2, 1, 0
-; CHECK-P8-NEXT:    xsmaddadp 5, 2, 0
+; CHECK-P8-NEXT:    lfs 4, .LCPI21_0@toc@l(3)
+; CHECK-P8-NEXT:    xvcvsxwdp 2, 34
+; CHECK-P8-NEXT:    xsmuldp 3, 1, 0
+; CHECK-P8-NEXT:    fmr 5, 2
+; CHECK-P8-NEXT:    xsmaddadp 5, 3, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P8-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P8-NEXT:    xsmuldp 1, 1, 0
-; CHECK-P8-NEXT:    xsmaddadp 3, 1, 0
+; CHECK-P8-NEXT:    xsmaddadp 2, 1, 0
 ; CHECK-P8-NEXT:    xsmuldp 0, 1, 4
-; CHECK-P8-NEXT:    xsmuldp 1, 0, 3
+; CHECK-P8-NEXT:    xsmuldp 1, 0, 2
 ; CHECK-P8-NEXT:    blr
 ; CHECK-P8-NEXT:  .LBB21_2:
 ; CHECK-P8-NEXT:    xssqrtdp 1, 1
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: foo3_fmf_crbits_off:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI21_2@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI21_1@toc@ha
 ; CHECK-P9-NEXT:    xsabsdp 0, 1
-; CHECK-P9-NEXT:    lfd 2, .LCPI21_2@toc@l(3)
+; CHECK-P9-NEXT:    lfd 2, .LCPI21_1@toc@l(3)
 ; CHECK-P9-NEXT:    xscmpudp 0, 0, 2
 ; CHECK-P9-NEXT:    blt 0, .LBB21_2
 ; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    xsrsqrtedp 0, 1
+; CHECK-P9-NEXT:    vspltisw 2, -3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-P9-NEXT:    lfs 3, .LCPI21_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI21_1@toc@ha
 ; CHECK-P9-NEXT:    xsmuldp 2, 1, 0
+; CHECK-P9-NEXT:    xvcvsxwdp 3, 34
 ; CHECK-P9-NEXT:    fmr 4, 3
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
-; CHECK-P9-NEXT:    lfs 2, .LCPI21_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 2, .LCPI21_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 2
 ; CHECK-P9-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB21_2:

 ; CHECK-P7-NEXT:  .LBB23_2:
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI23_3@toc@ha
 ; CHECK-P7-NEXT:    lfs 1, .LCPI23_3@toc@l(3)
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: goo3_fmf:
 ; CHECK-P8:       # %bb.0:
 ; CHECK-P8-NEXT:    xsabsdp 0, 1
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI23_2@toc@ha
-; CHECK-P8-NEXT:    lfs 2, .LCPI23_2@toc@l(3)
+; CHECK-P8-NEXT:    addis 3, 2, .LCPI23_1@toc@ha
+; CHECK-P8-NEXT:    vspltisw 2, -3
+; CHECK-P8-NEXT:    lfs 2, .LCPI23_1@toc@l(3)
 ; CHECK-P8-NEXT:    fcmpu 0, 0, 2
+; CHECK-P8-NEXT:    xvcvsxwsp 2, 34
 ; CHECK-P8-NEXT:    xxlxor 0, 0, 0
 ; CHECK-P8-NEXT:    blt 0, .LBB23_2
 ; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xsrsqrtesp 0, 1
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-P8-NEXT:    lfs 2, .LCPI23_0@toc@l(3)
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI23_1@toc@ha
-; CHECK-P8-NEXT:    lfs 3, .LCPI23_1@toc@l(3)
+; CHECK-P8-NEXT:    lfs 3, .LCPI23_0@toc@l(3)
 ; CHECK-P8-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P8-NEXT:    xsmaddasp 2, 1, 0
 ; CHECK-P8-NEXT:    xsmulsp 0, 1, 3
 ; CHECK-P8-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P8-NEXT:  .LBB23_2:
 ; CHECK-P8-NEXT:    fmr 1, 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: goo3_fmf:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI23_2@toc@ha
+; CHECK-P9-NEXT:    addis 3, 2, .LCPI23_1@toc@ha
+; CHECK-P9-NEXT:    vspltisw 2, -3
 ; CHECK-P9-NEXT:    xsabsdp 0, 1
-; CHECK-P9-NEXT:    lfs 2, .LCPI23_2@toc@l(3)
-; CHECK-P9-NEXT:    fcmpu 0, 0, 2
+; CHECK-P9-NEXT:    lfs 3, .LCPI23_1@toc@l(3)
+; CHECK-P9-NEXT:    xvcvsxwsp 2, 34
+; CHECK-P9-NEXT:    fcmpu 0, 0, 3
 ; CHECK-P9-NEXT:    xxlxor 0, 0, 0
 ; CHECK-P9-NEXT:    blt 0, .LBB23_2
 ; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    xsrsqrtesp 0, 1
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-P9-NEXT:    lfs 2, .LCPI23_0@toc@l(3)
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI23_1@toc@ha
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddasp 2, 1, 0
-; CHECK-P9-NEXT:    lfs 0, .LCPI23_1@toc@l(3)
+; CHECK-P9-NEXT:    lfs 0, .LCPI23_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 1, 0
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:  .LBB23_2:
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
   %r = call contract reassoc ninf afn float @llvm.sqrt.f32(float %a)
   ret float %r
 }

llvm/test/CodeGen/PowerPC/scalar_cmp.ll

entry:
   %cond = select i1 %cmp, double %c, double %d
   ret double %cond
 }
 
 ; Test RHS is 1.000000e+00
 define double @onecmp1(double %a, double %y, double %z) {
 ; FAST-P8-LABEL: onecmp1:
 ; FAST-P8:       # %bb.0: # %entry
-; FAST-P8-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; FAST-P8-NEXT:    lfs f0, .LCPI24_0@toc@l(r3)
-; FAST-P8-NEXT:    xssubdp f0, f1, f0
+; FAST-P8-NEXT:    vspltisw v2, -1
+; FAST-P8-NEXT:    xscvsxddp f0, vs34
+; FAST-P8-NEXT:    xsadddp f0, f1, f0
 ; FAST-P8-NEXT:    fsel f1, f0, f2, f3
 ; FAST-P8-NEXT:    blr
 ;
 ; FAST-P9-LABEL: onecmp1:
 ; FAST-P9:       # %bb.0: # %entry
-; FAST-P9-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; FAST-P9-NEXT:    lfs f0, .LCPI24_0@toc@l(r3)
-; FAST-P9-NEXT:    xssubdp f0, f1, f0
+; FAST-P9-NEXT:    vspltisw v2, -1
+; FAST-P9-NEXT:    xscvsxddp f0, vs34
+; FAST-P9-NEXT:    xsadddp f0, f1, f0
 ; FAST-P9-NEXT:    fsel f1, f0, f2, f3
 ; FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: onecmp1:
 ; NO-FAST-P8:       # %bb.0: # %entry
-; NO-FAST-P8-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; NO-FAST-P8-NEXT:    lfs f0, .LCPI24_0@toc@l(r3)
+; NO-FAST-P8-NEXT:    vspltisw v2, 1
+; NO-FAST-P8-NEXT:    xscvsxddp f0, vs34
 ; NO-FAST-P8-NEXT:    fcmpu cr0, f1, f0
-; NO-FAST-P8-NEXT:    cror 4*cr5+lt, lt, un
-; NO-FAST-P8-NEXT:    bc 12, 4*cr5+lt, .LBB24_2
+; NO-FAST-P8-NEXT:    bc 12, lt, .LBB24_3
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
+; NO-FAST-P8-NEXT:    fcmpu cr0, f1, f1
+; NO-FAST-P8-NEXT:    bc 12, un, .LBB24_3
+; NO-FAST-P8-NEXT:  # %bb.2: # %entry
 ; NO-FAST-P8-NEXT:    fmr f3, f2
-; NO-FAST-P8-NEXT:  .LBB24_2: # %entry
+; NO-FAST-P8-NEXT:  .LBB24_3: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f3
 ; NO-FAST-P8-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: onecmp1:
 ; NO-FAST-P9:       # %bb.0: # %entry
-; NO-FAST-P9-NEXT:    addis r3, r2, .LCPI24_0@toc@ha
-; NO-FAST-P9-NEXT:    lfs f0, .LCPI24_0@toc@l(r3)
+; NO-FAST-P9-NEXT:    vspltisw v2, 1
+; NO-FAST-P9-NEXT:    xscvsxddp f0, vs34
 ; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f0
-; NO-FAST-P9-NEXT:    cror 4*cr5+lt, lt, un
-; NO-FAST-P9-NEXT:    bc 12, 4*cr5+lt, .LBB24_2
+; NO-FAST-P9-NEXT:    bc 12, lt, .LBB24_3
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
+; NO-FAST-P9-NEXT:    fcmpu cr0, f1, f1
+; NO-FAST-P9-NEXT:    bc 12, un, .LBB24_3
+; NO-FAST-P9-NEXT:  # %bb.2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f3, f2
-; NO-FAST-P9-NEXT:  .LBB24_2: # %entry
+; NO-FAST-P9-NEXT:  .LBB24_3: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f3
 ; NO-FAST-P9-NEXT:    blr
 entry:
   %cmp = fcmp ult double %a, 1.000000e+00
   %z.y = select i1 %cmp, double %z, double %y
   ret double %z.y
 }
 
 define double @onecmp2(double %a, double %y, double %z) {
 ; FAST-P8-LABEL: onecmp2:
 ; FAST-P8:       # %bb.0: # %entry
-; FAST-P8-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; FAST-P8-NEXT:    lfs f0, .LCPI25_0@toc@l(r3)
+; FAST-P8-NEXT:    vspltisw v2, 1
+; FAST-P8-NEXT:    xscvsxddp f0, vs34
 ; FAST-P8-NEXT:    xssubdp f0, f0, f1
 ; FAST-P8-NEXT:    fsel f1, f0, f3, f2
 ; FAST-P8-NEXT:    blr
 ;
 ; FAST-P9-LABEL: onecmp2:
 ; FAST-P9:       # %bb.0: # %entry
-; FAST-P9-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; FAST-P9-NEXT:    lfs f0, .LCPI25_0@toc@l(r3)
+; FAST-P9-NEXT:    vspltisw v2, 1
+; FAST-P9-NEXT:    xscvsxddp f0, vs34
 ; FAST-P9-NEXT:    xssubdp f0, f0, f1
 ; FAST-P9-NEXT:    fsel f1, f0, f3, f2
 ; FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: onecmp2:
 ; NO-FAST-P8:       # %bb.0: # %entry
-; NO-FAST-P8-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; NO-FAST-P8-NEXT:    lfs f0, .LCPI25_0@toc@l(r3)
+; NO-FAST-P8-NEXT:    vspltisw v2, 1
+; NO-FAST-P8-NEXT:    xscvsxddp f0, vs34
 ; NO-FAST-P8-NEXT:    xscmpudp cr0, f1, f0
 ; NO-FAST-P8-NEXT:    fmr f1, f2
 ; NO-FAST-P8-NEXT:    bgtlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f3
 ; NO-FAST-P8-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: onecmp2:
 ; NO-FAST-P9:       # %bb.0: # %entry
-; NO-FAST-P9-NEXT:    addis r3, r2, .LCPI25_0@toc@ha
-; NO-FAST-P9-NEXT:    lfs f0, .LCPI25_0@toc@l(r3)
+; NO-FAST-P9-NEXT:    vspltisw v2, 1
+; NO-FAST-P9-NEXT:    xscvsxddp f0, vs34
 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f0
 ; NO-FAST-P9-NEXT:    bgt cr0, .LBB25_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f2, f3
 ; NO-FAST-P9-NEXT:  .LBB25_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f2
 ; NO-FAST-P9-NEXT:    blr
 entry:
   %cmp = fcmp ogt double %a, 1.000000e+00
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 }
 
 define double @onecmp3(double %a, double %y, double %z) {
 ; FAST-P8-LABEL: onecmp3:
 ; FAST-P8:       # %bb.0: # %entry
-; FAST-P8-NEXT:    addis r3, r2, .LCPI26_0@toc@ha
-; FAST-P8-NEXT:    lfs f0, .LCPI26_0@toc@l(r3)
-; FAST-P8-NEXT:    xssubdp f0, f1, f0
+; FAST-P8-NEXT:    vspltisw v2, -1
+; FAST-P8-NEXT:    xscvsxddp f0, vs34
+; FAST-P8-NEXT:    xsadddp f0, f1, f0
 ; FAST-P8-NEXT:    xsnegdp f1, f0
 ; FAST-P8-NEXT:    fsel f0, f0, f2, f3
 ; FAST-P8-NEXT:    fsel f1, f1, f0, f3
 ; FAST-P8-NEXT:    blr
 ;
 ; FAST-P9-LABEL: onecmp3:
 ; FAST-P9:       # %bb.0: # %entry
-; FAST-P9-NEXT:    addis r3, r2, .LCPI26_0@toc@ha
-; FAST-P9-NEXT:    lfs f0, .LCPI26_0@toc@l(r3)
-; FAST-P9-NEXT:    xssubdp f0, f1, f0
+; FAST-P9-NEXT:    vspltisw v2, -1
+; FAST-P9-NEXT:    xscvsxddp f0, vs34
+; FAST-P9-NEXT:    xsadddp f0, f1, f0
 ; FAST-P9-NEXT:    fsel f1, f0, f2, f3
 ; FAST-P9-NEXT:    xsnegdp f0, f0
 ; FAST-P9-NEXT:    fsel f1, f0, f1, f3
 ; FAST-P9-NEXT:    blr
 ;
 ; NO-FAST-P8-LABEL: onecmp3:
 ; NO-FAST-P8:       # %bb.0: # %entry
-; NO-FAST-P8-NEXT:    addis r3, r2, .LCPI26_0@toc@ha
-; NO-FAST-P8-NEXT:    lfs f0, .LCPI26_0@toc@l(r3)
+; NO-FAST-P8-NEXT:    vspltisw v2, 1
+; NO-FAST-P8-NEXT:    xscvsxddp f0, vs34
 ; NO-FAST-P8-NEXT:    xscmpudp cr0, f1, f0
 ; NO-FAST-P8-NEXT:    fmr f1, f2
 ; NO-FAST-P8-NEXT:    beqlr cr0
 ; NO-FAST-P8-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P8-NEXT:    fmr f1, f3
 ; NO-FAST-P8-NEXT:    blr
 ;
 ; NO-FAST-P9-LABEL: onecmp3:
 ; NO-FAST-P9:       # %bb.0: # %entry
-; NO-FAST-P9-NEXT:    addis r3, r2, .LCPI26_0@toc@ha
-; NO-FAST-P9-NEXT:    lfs f0, .LCPI26_0@toc@l(r3)
+; NO-FAST-P9-NEXT:    vspltisw v2, 1
+; NO-FAST-P9-NEXT:    xscvsxddp f0, vs34
 ; NO-FAST-P9-NEXT:    xscmpudp cr0, f1, f0
 ; NO-FAST-P9-NEXT:    beq cr0, .LBB26_2
 ; NO-FAST-P9-NEXT:  # %bb.1: # %entry
 ; NO-FAST-P9-NEXT:    fmr f2, f3
 ; NO-FAST-P9-NEXT:  .LBB26_2: # %entry
 ; NO-FAST-P9-NEXT:    fmr f1, f2
 ; NO-FAST-P9-NEXT:    blr
 entry:
   %cmp = fcmp oeq double %a, 1.000000e+00
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 }

llvm/test/CodeGen/PowerPC/select_const.ll

 ; ALL:       # %bb.0:
 ; ALL-NEXT:    andi. 3, 3, 1
 ; ALL-NEXT:    bc 12, 1, .LBB48_2
 ; ALL-NEXT:  # %bb.1:
 ; ALL-NEXT:    addis 3, 2, .LCPI48_0@toc@ha
 ; ALL-NEXT:    lfd 1, .LCPI48_0@toc@l(3)
 ; ALL-NEXT:    blr
 ; ALL-NEXT:  .LBB48_2:
-; ALL-NEXT:    addis 3, 2, .LCPI48_1@toc@ha
-; ALL-NEXT:    lfs 1, .LCPI48_1@toc@l(3)
+; ALL-NEXT:    vspltisw 2, -4
+; ALL-NEXT:    xscvsxddp 1, 34
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = frem double %sel, 5.1
   ret double %bo
 }
 
 define double @frem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: frem_constant_sel_constants:

llvm/test/CodeGen/PowerPC/toc-float.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s
 
 ; As the constant could be represented as float, a float is
 ; loaded from constant pool.
 define double @doubleConstant1() {
 ; CHECK-P9-LABEL: doubleConstant1:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
+; CHECK-P9-NEXT:    vspltisw 2, 14
+; CHECK-P9-NEXT:    xscvsxddp 1, 34
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: doubleConstant1:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; CHECK-P8-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
+; CHECK-P8-NEXT:    vspltisw 2, 14
+; CHECK-P8-NEXT:    xscvsxddp 1, 34
 ; CHECK-P8-NEXT:    blr
   ret double 1.400000e+01
 }
 
 ; As the constant couldn't be represented as float, a double is
 ; loaded from constant pool.
 define double @doubleConstant2() {
 ; CHECK-P9-LABEL: doubleConstant2:

llvm/test/CodeGen/PowerPC/vec_extract_p9.ll

 }
 
 define double @test10(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LE-LABEL: test10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
 ; CHECK-LE-NEXT:    lxv 0, 0(3)
-; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
-; CHECK-LE-NEXT:    lfs 1, .LCPI9_1@toc@l(3)
 ; CHECK-LE-NEXT:    xxperm 35, 34, 0
+; CHECK-LE-NEXT:    vspltisw 2, 1
+; CHECK-LE-NEXT:    xscvsxddp 1, 34
 ; CHECK-LE-NEXT:    xxswapd 0, 35
 ; CHECK-LE-NEXT:    xsadddp 1, 0, 1
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test10:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
 ; CHECK-BE-NEXT:    lxv 0, 0(3)
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
 ; CHECK-BE-NEXT:    xxperm 34, 35, 0
-; CHECK-BE-NEXT:    lfs 0, .LCPI9_1@toc@l(3)
+; CHECK-BE-NEXT:    vspltisw 3, 1
+; CHECK-BE-NEXT:    xscvsxddp 0, 35
 ; CHECK-BE-NEXT:    xsadddp 1, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 2, i32 3, i32 7>
   %cast = bitcast <4 x i32> %shuffle to <2 x double>
   %extract = extractelement <2 x double> %cast, i32 0
   %add = fadd double %extract, 1.0000
   ret double %add
 }