[ScheduleDAG] Support REQ_SEQUENCE unscheduling

[fzhinkin]

Summary

REG_SEQUENCE node requires special treatment during the
unscheduling because the node is untyped and neither its
class, nor cost could be retrieved the same way as for
typed nodes.

Related issue: https://github.com/llvm/llvm-project/issues/58911

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Cleanup

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Rebase

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ping

[efriedma]

LGTM.

It's not really clear to me why unscheduling isn't using GetCostForDef(), but I don't really want to make more complex changes to this code; it tends to be fragile.

[barannikov88]

Just a note.
I see other targets just override getRepRegClassFor for MVT::Untyped. Might it be better to do the same for ARM?

[fzhinkin]

In D138837#4016110, @barannikov88 wrote:

Just a note.
I see other targets just override getRepRegClassFor for MVT::Untyped. Might it be better to do the same for ARM?

@barannikov88 even if getRepRegClassFor will return some non-null value, getRepRegClassCostFor may return value that differs from 1 returned by GetCostForDef for REG_SEQUENCE, so it wouldn't be sufficient to only override getRepRegClassFor.

I looked at how it works for SystemZ target and getRepRegClassFor returns SystemZ::ADDR128BitRegClass for MVT::Untyped, but corresponding cost returned by getRepRegClassCostFor is 0.

It also seems like the only targets handling MVT::Untyped in getRepRegClassFor are MIPS and SystemZ, so a change should be made not only in the ARM target, but in all other targets too.

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

private:
   /// need actual latency information but the hybrid scheduler does.
   bool forceUnitLatencies() const override {
     return !NeedLatency;
   }
 };
 
 }  // end anonymous namespace
 
+static constexpr unsigned RegSequenceCost = 1;
+
 /// GetCostForDef - Looks up the register class and cost for a given definition.
 /// Typically this just means looking up the representative register class,
 /// but for untyped values (MVT::Untyped) it means inspecting the node's
 /// opcode to determine what register class is being generated.
 static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
                           const TargetLowering *TLI,
                           const TargetInstrInfo *TII,
                           const TargetRegisterInfo *TRI,
if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
       return;
     }
 
     unsigned Opcode = Node->getMachineOpcode();
     if (Opcode == TargetOpcode::REG_SEQUENCE) {
       unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
       const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
       RegClass = RC->getID();
-      Cost = 1;
+      Cost = RegSequenceCost;
       return;
     }
 
     unsigned Idx = RegDefPos.GetIdx();
     const MCInstrDesc Desc = TII->get(Opcode);
     const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
     assert(RC && "Not a valid register class");
     RegClass = RC->getID();
for (const SDep &Pred : SU->Preds) {
     if (POpc == TargetOpcode::EXTRACT_SUBREG ||
         POpc == TargetOpcode::INSERT_SUBREG ||
         POpc == TargetOpcode::SUBREG_TO_REG) {
       MVT VT = PN->getSimpleValueType(0);
       unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
       RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
       continue;
     }
+    if (POpc == TargetOpcode::REG_SEQUENCE) {
+      unsigned DstRCIdx =
+          cast<ConstantSDNode>(PN->getOperand(0))->getZExtValue();
+      const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
+      unsigned RCId = RC->getID();
+      // REG_SEQUENCE is untyped, so getRepRegClassCostFor could not be used
+      // here. Instead use the same constant as in GetCostForDef.
+      RegPressure[RCId] += RegSequenceCost;
+      continue;
+    }
     unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
     for (unsigned i = 0; i != NumDefs; ++i) {
       MVT VT = PN->getSimpleValueType(i);
       if (!PN->hasAnyUseOfValue(i))
         continue;
       unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
       if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
         // Register pressure tracking is imprecise. This can happen.

llvm/test/CodeGen/ARM/unschedule-reg-sequence.ll

+; RUN: llc -verify-machineinstrs < %s
+; Regression test for https://github.com/llvm/llvm-project/issues/58911
+
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7-none-unknown-eabi"
+
+@a = dso_local global i64 0, align 8
+@d = dso_local local_unnamed_addr global i32 0, align 4
+
+define dso_local void @f() nounwind {
+entry:
+  store volatile i64 0, ptr @a, align 8
+  %0 = load i32, ptr @d, align 4
+  %tobool.not = icmp eq i32 %0, 0
+  %conv = zext i32 %0 to i64
+  %sub = sub nsw i64 0, %conv
+  %cond = select i1 %tobool.not, i64 0, i64 %sub
+  store volatile i64 %cond, ptr @a, align 8
+  ret void
+}
+