[PowerPC] Fix vperm codegen

[maryammo]

Summary

Commit rG934d5fa2b8672695c335deed0e19d0e777c98403 changed the vperm codegen
for cases that vperm is not replaced by xxperm, this patch is to revert that.

[stefanp]

Thank you for fixing this.
I do have a couple of comments related to the fix.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10204

I don't think you need to bother with this extra ternary operator.
Everywhere you use V1HasXXSWAPD or V2HasXXSWAPD seems to already be guarded by Opcode == PPCISD::XXPERM so it doesn't matter what value those two bool values have in cases when you are not using the XXPERM oeprand.

10261

Is it possible to have a swap on both sides?

10271

For this section how about:

if (Opcode == PPCISD::XXPERM && (V1HasXXSWAPD || V2HasXXSWAPD)) {
  /// Same code as above but you don't need to check that (V1HasXXSWAPD || V2HasXXSWAPD)
}

You don't need to go into the if statement at all if there isn't at least one XXSWAPD.

[maryammo]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10261

I have not see such a case.
btw, this patch is to address the vperm issue, so we can look at the swap on both sides for xxperm if needed separately. Thanks.

[maryammo]

Address the review comments

[stefanp]

Thank you for fixing this!
LGTM.

[maryammo]

Address the review comments

[RKSimon]

@maryammo Please can you take a look at https://github.com/llvm/llvm-project/issues/61315 - it looks related to this patch (and D133700)

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.isISA3_0() && (V1->hasOneUse() || V2->hasOneUse())) {
     // if V2 is dead, then we swap V1 and V2 so we can
     // use V2 as the destination instead.
     if (!V1->hasOneUse() && V2->hasOneUse()) {
       std::swap(V1, V2);
       NeedSwap = !NeedSwap;
     }
   }
 
-  bool V1HasXXSWAPD = V1->getOperand(0)->getOpcode() == PPCISD::XXSWAPD;
-  bool V2HasXXSWAPD = V2->getOperand(0)->getOpcode() == PPCISD::XXSWAPD;
-
   // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
   // that it is in input element units, not in bytes.  Convert now.
 
   // For little endian, the order of the input vectors is reversed, and
   // the permutation mask is complemented with respect to 31.  This is
   // necessary to produce proper semantics with the big-endian-based vperm
   // instruction.
   EVT EltVT = V1.getValueType().getVectorElementType();
   unsigned BytesPerElement = EltVT.getSizeInBits() / 8;
 
+  bool V1HasXXSWAPD = Opcode == PPCISD::XXPERM
+                          ? V1->getOperand(0)->getOpcode() == PPCISD::XXSWAPD
+                          : false;
+  bool V2HasXXSWAPD = Opcode == PPCISD::XXPERM
+                          ? V2->getOperand(0)->getOpcode() == PPCISD::XXSWAPD
+                          : false;
+
   /*
   Vectors will be appended like so: [ V1 | v2 ]
   XXSWAPD on V1:
   [   A   |   B   |   C   |   D   ] -> [   C   |   D   |   A   |   B   ]
      0-3     4-7     8-11   12-15         0-3     4-7     8-11   12-15
   i.e.  index of A, B += 8, and index of C, D -= 8.
   XXSWAPD on V2:
   [   E   |   F   |   G   |   H   ] -> [   G   |   H   |   E   |   F   ]
     16-19   20-23   24-27   28-31        16-19   20-23   24-27   28-31
   i.e.  index of E, F += 8, index of G, H -= 8
   Swap V1 and V2:
   [   V1   |   V2  ] -> [   V2   |   V1   ]
      0-15     16-31        0-15     16-31
   i.e.  index of V1 += 16, index of V2 -= 16
   */
 
   SmallVector<SDValue, 16> ResultMask;
   for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
     unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
 
+    if (Opcode == PPCISD::XXPERM) {
       if (V1HasXXSWAPD) {
         if (SrcElt < 8)
           SrcElt += 8;
         else if (SrcElt < 16)
           SrcElt -= 8;
       }
       if (V2HasXXSWAPD) {
         if (SrcElt > 23)
           SrcElt -= 8;
         else if (SrcElt > 15)
           SrcElt += 8;
       }
       if (NeedSwap) {
         if (SrcElt < 16)
           SrcElt += 16;
         else
           SrcElt -= 16;
       }
+    }
+
     for (unsigned j = 0; j != BytesPerElement; ++j)
       if (isLittleEndian)
         ResultMask.push_back(
             DAG.getConstant(31 - (SrcElt * BytesPerElement + j), dl, MVT::i32));
       else
         ResultMask.push_back(
             DAG.getConstant(SrcElt * BytesPerElement + j, dl, MVT::i32));
   }
 
+  if (Opcode == PPCISD::XXPERM) {
     if (V1HasXXSWAPD) {
       dl = SDLoc(V1->getOperand(0));
       V1 = V1->getOperand(0)->getOperand(1);
     }
     if (V2HasXXSWAPD) {
       dl = SDLoc(V2->getOperand(0));
       V2 = V2->getOperand(0)->getOperand(1);
     }
-
-  if (V1HasXXSWAPD || V2HasXXSWAPD || Opcode == PPCISD::XXPERM) {
+    if (V1HasXXSWAPD || V2HasXXSWAPD) {
       if (isPPC64 && ValType != MVT::v2f64)
         V1 = DAG.getBitcast(MVT::v2f64, V1);
       if (isPPC64 && V2.getValueType() != MVT::v2f64)
         V2 = DAG.getBitcast(MVT::v2f64, V2);
     }
+  }
 
   ShufflesHandledWithVPERM++;
   SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask);
   LLVM_DEBUG({
     ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
     if (Opcode == PPCISD::XXPERM) {
       dbgs() << "Emitting a XXPERM for the following shuffle:\n";
     } else {

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

 ; P8BE-NEXT:    addi r3, r3, -12
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarDi:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
 ; P8LE-NEXT:    sldi r4, r4, 2
-; P8LE-NEXT:    addi r5, r5, .LCPI9_0@toc@l
+; P8LE-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
 ; P8LE-NEXT:    add r3, r3, r4
-; P8LE-NEXT:    lxvd2x vs0, 0, r5
+; P8LE-NEXT:    addi r4, r5, .LCPI9_0@toc@l
 ; P8LE-NEXT:    addi r3, r3, -12
-; P8LE-NEXT:    lxvd2x v2, 0, r3
-; P8LE-NEXT:    xxswapd v3, vs0
+; P8LE-NEXT:    lxvd2x vs1, 0, r4
+; P8LE-NEXT:    lxvd2x vs0, 0, r3
+; P8LE-NEXT:    xxswapd v3, vs1
+; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    blr
 entry:
   %idxprom = sext i32 %elem to i64
   %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
   %0 = load i32, ptr %arrayidx, align 4
   %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
   %sub = add nsw i32 %elem, -1

 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    xvcvspsxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemConsDConvftoi:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r4, r2, .LCPI18_0@toc@ha
-; P8LE-NEXT:    lxvd2x v2, 0, r3
+; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    addi r4, r4, .LCPI18_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r4
-; P8LE-NEXT:    xxswapd v3, vs0
+; P8LE-NEXT:    lxvd2x vs1, 0, r4
+; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    xvcvspsxws v2, v2
 ; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
   %0 = load float, ptr %arrayidx, align 4
   %conv = fptosi float %0 to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0

 ; P8BE-NEXT:    addi r3, r3, -12
 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemVarDui:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    addis r5, r2, .LCPI41_0@toc@ha
 ; P8LE-NEXT:    sldi r4, r4, 2
-; P8LE-NEXT:    addi r5, r5, .LCPI41_0@toc@l
+; P8LE-NEXT:    addis r5, r2, .LCPI41_0@toc@ha
 ; P8LE-NEXT:    add r3, r3, r4
-; P8LE-NEXT:    lxvd2x vs0, 0, r5
+; P8LE-NEXT:    addi r4, r5, .LCPI41_0@toc@l
 ; P8LE-NEXT:    addi r3, r3, -12
-; P8LE-NEXT:    lxvd2x v2, 0, r3
-; P8LE-NEXT:    xxswapd v3, vs0
+; P8LE-NEXT:    lxvd2x vs1, 0, r4
+; P8LE-NEXT:    lxvd2x vs0, 0, r3
+; P8LE-NEXT:    xxswapd v3, vs1
+; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    blr
 entry:
   %idxprom = sext i32 %elem to i64
   %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
   %0 = load i32, ptr %arrayidx, align 4
   %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
   %sub = add nsw i32 %elem, -1

 ; P8BE-NEXT:    lxvw4x v3, 0, r4
 ; P8BE-NEXT:    vperm v2, v2, v2, v3
 ; P8BE-NEXT:    xvcvspuxws v2, v2
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fromDiffMemConsDConvftoui:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r4, r2, .LCPI50_0@toc@ha
-; P8LE-NEXT:    lxvd2x v2, 0, r3
+; P8LE-NEXT:    lxvd2x vs0, 0, r3
 ; P8LE-NEXT:    addi r4, r4, .LCPI50_0@toc@l
-; P8LE-NEXT:    lxvd2x vs0, 0, r4
-; P8LE-NEXT:    xxswapd v3, vs0
+; P8LE-NEXT:    lxvd2x vs1, 0, r4
+; P8LE-NEXT:    xxswapd v2, vs0
+; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    vperm v2, v2, v2, v3
 ; P8LE-NEXT:    xvcvspuxws v2, v2
 ; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
   %0 = load float, ptr %arrayidx, align 4
   %conv = fptoui float %0 to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: testmrglb3:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    lxsd v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
-; CHECK-P9-BE-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-P9-BE-NEXT:    xxlxor vs1, vs1, vs1
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI12_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv vs1, 0(r3)
-; CHECK-P9-BE-NEXT:    xxperm v2, vs0, vs1
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-P9-BE-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrglb3:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vxor v2, v2, v2
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI12_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI12_0@toc@l

llvm/test/CodeGen/PowerPC/ppc-shufflevector-combine.ll

 ; LE-32-NEXT:    xxperm v3, v2, vs0
 ; LE-32-NEXT:    vinsw v3, r3, 4
 ; LE-32-NEXT:    vpkuwum v2, v3, v3
 ; LE-32-NEXT:    blr
 ;
 ; BE-LABEL: shufflevector_combine:
 ; BE:       # %bb.0: # %newFuncRoot
 ; BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; BE-NEXT:    xxlxor vs0, vs0, vs0
+; BE-NEXT:    xxlxor vs1, vs1, vs1
 ; BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; BE-NEXT:    lxv vs1, 0(r3)
+; BE-NEXT:    lxv vs0, 0(r3)
 ; BE-NEXT:    li r3, 0
-; BE-NEXT:    xxperm v2, vs0, vs1
+; BE-NEXT:    xxperm v2, vs1, vs0
 ; BE-NEXT:    vinsw v2, r3, 8
 ; BE-NEXT:    vpkuwum v2, v2, v2
 ; BE-NEXT:    blr
 ;
 ; BE-32-LABEL: shufflevector_combine:
 ; BE-32:       # %bb.0: # %newFuncRoot
 ; BE-32-NEXT:    li r3, .LCPI0_0@l
 ; BE-32-NEXT:    lis r4, .LCPI0_0@ha

llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

 ; P9LE-NEXT:    stxv 0, 0(3)
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: test64:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add 5, 3, 4
 ; P9BE-NEXT:    lxsdx 2, 3, 4
 ; P9BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
-; P9BE-NEXT:    xxlxor 0, 0, 0
+; P9BE-NEXT:    xxlxor 1, 1, 1
 ; P9BE-NEXT:    vspltisw 4, 8
 ; P9BE-NEXT:    lxsd 3, 4(5)
 ; P9BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
 ; P9BE-NEXT:    vadduwm 4, 4, 4
-; P9BE-NEXT:    lxv 1, 0(3)
+; P9BE-NEXT:    lxv 0, 0(3)
 ; P9BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
 ; P9BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
-; P9BE-NEXT:    xxperm 2, 0, 1
+; P9BE-NEXT:    xxperm 2, 1, 0
 ; P9BE-NEXT:    lxv 0, 0(3)
 ; P9BE-NEXT:    xxperm 3, 3, 0
 ; P9BE-NEXT:    vnegw 3, 3
 ; P9BE-NEXT:    vslw 3, 3, 4
 ; P9BE-NEXT:    vsubuwm 2, 3, 2
 ; P9BE-NEXT:    xxswapd 0, 2
 ; P9BE-NEXT:    stxv 0, 0(3)
 ; P9BE-NEXT:    blr

 ; P9BE-NEXT:    mtvsrwz 2, 6
 ; P9BE-NEXT:    vmr 3, 2
 ; P9BE-NEXT:    vsplth 4, 2, 3
 ; P9BE-NEXT:    xxperm 3, 0, 1
 ; P9BE-NEXT:    lxsihzx 0, 3, 4
 ; P9BE-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
 ; P9BE-NEXT:    addi 3, 3, .LCPI2_1@toc@l
 ; P9BE-NEXT:    xxperm 2, 0, 1
-; P9BE-NEXT:    lxv 1, 0(3)
+; P9BE-NEXT:    lxv 0, 0(3)
 ; P9BE-NEXT:    li 3, 0
-; P9BE-NEXT:    xxmrghw 0, 4, 2
-; P9BE-NEXT:    xxperm 3, 0, 1
+; P9BE-NEXT:    xxmrghw 2, 4, 2
+; P9BE-NEXT:    xxperm 3, 2, 0
 ; P9BE-NEXT:    xxspltw 2, 3, 1
 ; P9BE-NEXT:    vadduwm 2, 3, 2
 ; P9BE-NEXT:    vextuwlx 3, 3, 2
 ; P9BE-NEXT:    cmpw 3, 5
 ; P9BE-NEXT:    bgelr+ 0
 ; P9BE-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-AIX-LABEL: test16:
 ; P9BE-AIX:       # %bb.0: # %entry
 ; P9BE-AIX-NEXT:    sldi 4, 4, 1
 ; P9BE-AIX-NEXT:    li 7, 16
 ; P9BE-AIX-NEXT:    add 6, 3, 4
 ; P9BE-AIX-NEXT:    lxsihzx 0, 6, 7
 ; P9BE-AIX-NEXT:    ld 6, L..C3(2) # %const.0
 ; P9BE-AIX-NEXT:    lxv 1, 0(6)
 ; P9BE-AIX-NEXT:    li 6, 0
 ; P9BE-AIX-NEXT:    mtvsrwz 2, 6
 ; P9BE-AIX-NEXT:    vmr 3, 2
 ; P9BE-AIX-NEXT:    vsplth 4, 2, 3
 ; P9BE-AIX-NEXT:    xxperm 3, 0, 1
 ; P9BE-AIX-NEXT:    lxsihzx 0, 3, 4
 ; P9BE-AIX-NEXT:    ld 3, L..C4(2) # %const.1
 ; P9BE-AIX-NEXT:    xxperm 2, 0, 1
-; P9BE-AIX-NEXT:    lxv 1, 0(3)
+; P9BE-AIX-NEXT:    lxv 0, 0(3)
 ; P9BE-AIX-NEXT:    li 3, 0
-; P9BE-AIX-NEXT:    xxmrghw 0, 4, 2
-; P9BE-AIX-NEXT:    xxperm 3, 0, 1
+; P9BE-AIX-NEXT:    xxmrghw 2, 4, 2
+; P9BE-AIX-NEXT:    xxperm 3, 2, 0
 ; P9BE-AIX-NEXT:    xxspltw 2, 3, 1
 ; P9BE-AIX-NEXT:    vadduwm 2, 3, 2
 ; P9BE-AIX-NEXT:    vextuwlx 3, 3, 2
 ; P9BE-AIX-NEXT:    cmpw 3, 5
 ; P9BE-AIX-NEXT:    bgelr+ 0
 ; P9BE-AIX-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-AIX32-LABEL: test16:

 ; P9LE-NEXT:    mtvsrd 3, 3
 ; P9LE-NEXT:    li 3, 8
 ; P9LE-NEXT:    lxsibzx 5, 6, 3
 ; P9LE-NEXT:    vspltb 4, 3, 7
 ; P9LE-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; P9LE-NEXT:    vmrghb 2, 3, 2
 ; P9LE-NEXT:    addi 3, 3, .LCPI3_0@toc@l
 ; P9LE-NEXT:    vmrglh 2, 2, 4
-; P9LE-NEXT:    lxv 1, 0(3)
+; P9LE-NEXT:    lxv 0, 0(3)
 ; P9LE-NEXT:    li 3, 0
 ; P9LE-NEXT:    vmrghb 3, 3, 5
 ; P9LE-NEXT:    xxmrglw 2, 2, 4
 ; P9LE-NEXT:    vmrglh 3, 3, 4
-; P9LE-NEXT:    xxmrglw 0, 4, 3
-; P9LE-NEXT:    xxperm 2, 0, 1
+; P9LE-NEXT:    xxmrglw 3, 4, 3
+; P9LE-NEXT:    xxperm 2, 3, 0
 ; P9LE-NEXT:    xxspltw 3, 2, 2
 ; P9LE-NEXT:    vadduwm 2, 2, 3
 ; P9LE-NEXT:    vextuwrx 3, 3, 2
 ; P9LE-NEXT:    cmpw 3, 5
 ; P9LE-NEXT:    bgelr+ 0
 ; P9LE-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test8:

llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll

entry:
   %vecins = insertelement <16 x i8> %a, i8 %b, i32 0
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @test_none_v16i8(i8 %arg, ptr nocapture noundef readonly %b) {
 ; CHECK-LE-P8-LABEL: test_none_v16i8:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
-; CHECK-LE-P8-NEXT:    lxvd2x v2, 0, r4
+; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-LE-P8-NEXT:    mtvsrd v4, r3
 ; CHECK-LE-P8-NEXT:    addi r5, r5, .LCPI2_0@toc@l
-; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r5
-; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
+; CHECK-LE-P8-NEXT:    lxvd2x vs1, 0, r5
+; CHECK-LE-P8-NEXT:    xxswapd v2, vs0
+; CHECK-LE-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v16i8:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    mtfprd f0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-LE-P9-NEXT:    lxv v2, 0(r4)
entry:
   %shuffle = shufflevector <16 x i8> %lhs, <16 x i8> %rhs, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i8> %shuffle
 }
 
 define <16 x i8> @test_none_v8i16(i16 %arg, ptr nocapture noundef readonly %b) {
 ; CHECK-LE-P8-LABEL: test_none_v8i16:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r5, r2, .LCPI5_0@toc@ha
-; CHECK-LE-P8-NEXT:    lxvd2x v2, 0, r4
+; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-LE-P8-NEXT:    mtvsrd v4, r3
 ; CHECK-LE-P8-NEXT:    addi r5, r5, .LCPI5_0@toc@l
-; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r5
-; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
+; CHECK-LE-P8-NEXT:    lxvd2x vs1, 0, r5
+; CHECK-LE-P8-NEXT:    xxswapd v2, vs0
+; CHECK-LE-P8-NEXT:    xxswapd v3, vs1
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_none_v8i16:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    mtfprd f0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-LE-P9-NEXT:    lxv v2, 0(r4)

llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll

 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v4i32_none:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-LE-P9-NEXT:    xxlxor vs1, vs1, vs1
+; CHECK-LE-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv vs2, 0(r3)
-; CHECK-LE-P9-NEXT:    xxperm vs0, vs1, vs2
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm vs0, vs2, vs1
 ; CHECK-LE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v4i32_none:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-BE-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-P8-NEXT:    addi r4, r4, .LCPI3_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v4i32_none:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-BE-P9-NEXT:    xxlxor vs1, vs1, vs1
+; CHECK-BE-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv vs2, 0(r3)
-; CHECK-BE-P9-NEXT:    xxperm vs0, vs1, vs2
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm vs0, vs2, vs1
 ; CHECK-BE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v4i32_none:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C5(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsiwzx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    xxlxor v4, v4, v4
entry:
   store <4 x i32> %2, ptr undef, align 16
   ret void
 }
 
 define void @test_none_v2i64(ptr nocapture readonly %ptr1, ptr nocapture readonly %ptr2) {
 ; CHECK-LE-P8-LABEL: test_none_v2i64:
 ; CHECK-LE-P8:       # %bb.0: # %entry
 ; CHECK-LE-P8-NEXT:    addis r5, r2, .LCPI4_0@toc@ha
+; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-LE-P8-NEXT:    lxsdx v2, 0, r3
-; CHECK-LE-P8-NEXT:    lxvd2x v3, 0, r4
 ; CHECK-LE-P8-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
 ; CHECK-LE-P8-NEXT:    addi r5, r5, .LCPI4_0@toc@l
 ; CHECK-LE-P8-NEXT:    addi r3, r3, .LCPI4_1@toc@l
-; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r5
-; CHECK-LE-P8-NEXT:    xxswapd v4, vs0
+; CHECK-LE-P8-NEXT:    lxvd2x vs1, 0, r5
+; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-LE-P8-NEXT:    xxswapd v4, vs1
 ; CHECK-LE-P8-NEXT:    vperm v2, v2, v3, v4
 ; CHECK-LE-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-LE-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-LE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;

 ; CHECK-AIX-64-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-64-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    blr
 ;
 ; CHECK-AIX-64-P9-LABEL: test_none_v2i64:
 ; CHECK-AIX-64-P9:       # %bb.0: # %entry
 ; CHECK-AIX-64-P9-NEXT:    lxsd v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    ld r3, L..C5(r2) # %const.0
-; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r4)
+; CHECK-AIX-64-P9-NEXT:    lxv vs0, 0(r4)
 ; CHECK-AIX-64-P9-NEXT:    xxlxor v3, v3, v3
-; CHECK-AIX-64-P9-NEXT:    lxv vs0, 0(r3)
-; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs1, vs0
+; CHECK-AIX-64-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-AIX-64-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-AIX-64-P9-NEXT:    stxv v2, 0(r3)
 ; CHECK-AIX-64-P9-NEXT:    blr
 ;
 ; CHECK-AIX-32-P8-LABEL: test_none_v2i64:
 ; CHECK-AIX-32-P8:       # %bb.0: # %entry
 ; CHECK-AIX-32-P8-NEXT:    lwz r5, L..C5(r2) # %const.0
 ; CHECK-AIX-32-P8-NEXT:    lxsiwzx v2, 0, r3

 ; CHECK-LE-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-LE-P8-NEXT:    blr
 ;
 ; CHECK-LE-P9-LABEL: test_v2i64_none:
 ; CHECK-LE-P9:       # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-LE-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-LE-P9-NEXT:    xxlxor vs1, vs1, vs1
+; CHECK-LE-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-LE-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-LE-P9-NEXT:    lxv vs2, 0(r3)
-; CHECK-LE-P9-NEXT:    xxperm vs0, vs1, vs2
+; CHECK-LE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT:    xxperm vs0, vs2, vs1
 ; CHECK-LE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-LE-P9-NEXT:    blr
 ;
 ; CHECK-BE-P8-LABEL: test_v2i64_none:
 ; CHECK-BE-P8:       # %bb.0: # %entry
 ; CHECK-BE-P8-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-P8-NEXT:    lxsdx v2, 0, r3
 ; CHECK-BE-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-P8-NEXT:    addi r4, r4, .LCPI5_0@toc@l
 ; CHECK-BE-P8-NEXT:    lxvw4x v3, 0, r4
 ; CHECK-BE-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-P8-NEXT:    stxvw4x v2, 0, r3
 ; CHECK-BE-P8-NEXT:    blr
 ;
 ; CHECK-BE-P9-LABEL: test_v2i64_none:
 ; CHECK-BE-P9:       # %bb.0: # %entry
 ; CHECK-BE-P9-NEXT:    lfd f0, 0(r3)
 ; CHECK-BE-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-BE-P9-NEXT:    xxlxor vs1, vs1, vs1
+; CHECK-BE-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-BE-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-P9-NEXT:    lxv vs2, 0(r3)
-; CHECK-BE-P9-NEXT:    xxperm vs0, vs1, vs2
+; CHECK-BE-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-P9-NEXT:    xxperm vs0, vs2, vs1
 ; CHECK-BE-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-P9-NEXT:    blr
 ;
 ; CHECK-AIX-64-P8-LABEL: test_v2i64_none:
 ; CHECK-AIX-64-P8:       # %bb.0: # %entry
 ; CHECK-AIX-64-P8-NEXT:    ld r4, L..C7(r2) # %const.0
 ; CHECK-AIX-64-P8-NEXT:    lxsdx v2, 0, r3
 ; CHECK-AIX-64-P8-NEXT:    xxlxor v4, v4, v4

llvm/test/CodeGen/PowerPC/vec-itofp.ll

 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv vs1, 0(r4)
+; CHECK-P9-NEXT:    lxv vs0, 0(r4)
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-P9-NEXT:    lxv vs2, 0(r4)
-; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
-; CHECK-P9-NEXT:    xvcvuxddp vs0, vs1
+; CHECK-P9-NEXT:    lxv vs1, 0(r4)
+; CHECK-P9-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-P9-NEXT:    xvcvuxddp vs0, vs0
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtfprd f1, r3
+; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-BE-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv vs2, 0(r3)
-; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
-; CHECK-BE-NEXT:    xvcvuxwsp v2, vs1
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-BE-NEXT:    xvcvuxwsp v2, vs0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <4 x i16>
   %1 = uitofp <4 x i16> %0 to <4 x float>
   ret <4 x float> %1
 }
 
 define void @test8elt(ptr noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtfprwz f1, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-P9-NEXT:    lxv vs2, 0(r3)
-; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
-; CHECK-P9-NEXT:    xvcvuxddp v2, vs1
+; CHECK-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-P9-NEXT:    xvcvuxddp v2, vs0
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-BE-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv vs2, 0(r3)
-; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
-; CHECK-BE-NEXT:    xvcvuxddp v2, vs1
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-BE-NEXT:    xvcvuxddp v2, vs0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = uitofp <2 x i16> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt(ptr noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtfprwz f1, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-P9-NEXT:    lxv vs2, 0(r3)
-; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
-; CHECK-P9-NEXT:    xvcvuxwsp v2, vs1
+; CHECK-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-P9-NEXT:    xvcvuxwsp v2, vs0
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-BE-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv vs2, 0(r3)
-; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
-; CHECK-BE-NEXT:    xvcvuxwsp v2, vs1
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-BE-NEXT:    xvcvuxwsp v2, vs0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = uitofp <4 x i8> %0 to <4 x float>
   ret <4 x float> %1
 }
 
 define void @test8elt(ptr noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtfprwz f1, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-P9-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-P9-NEXT:    lxv vs2, 0(r3)
-; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
-; CHECK-P9-NEXT:    xvcvuxddp v2, vs1
+; CHECK-P9-NEXT:    lxv vs1, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-P9-NEXT:    xvcvuxddp v2, vs0
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-BE-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv vs2, 0(r3)
-; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
-; CHECK-BE-NEXT:    xvcvuxddp v2, vs1
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs0, vs2, vs1
+; CHECK-BE-NEXT:    xvcvuxddp v2, vs0
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = uitofp <2 x i8> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt(ptr noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

 ; PC64LE-NEXT:    xxswapd 35, 0
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    xvcvuxddp 34, 34
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI173_0@toc@ha
-; PC64LE9-NEXT:    xxlxor 0, 0, 0
+; PC64LE9-NEXT:    xxlxor 1, 1, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI173_0@toc@l
-; PC64LE9-NEXT:    lxv 1, 0(3)
-; PC64LE9-NEXT:    xxperm 34, 0, 1
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    xvcvuxddp 34, 34
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x double> %result