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[LLDB][RISCV] Add RV32F instruction support for EmulateInstructionRISCV
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Authored by Emmmer on Nov 21 2022, 9:29 AM.

Details

Summary

Add:

  • RV32F instruction set.
  • corresponding unittests.

Further work:

  • RV32FC, RV64F and RV64FC instructions support.
  • update execution exceptions to fcsr register in RVM instructions.

Diff Detail

Event Timeline

Emmmer created this revision.Nov 21 2022, 9:29 AM
Emmmer requested review of this revision.Nov 21 2022, 9:29 AM

I am no floating point expert but the structure seems fine and the use of APFloat means most of it looks right on the surface.

Just some minor comments.

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
475

static void here and for the other test helpers.

528

Add another test where they are not equal.

Emmmer updated this revision to Diff 477215.Nov 22 2022, 8:40 AM

address review comments.

DavidSpickett accepted this revision.Nov 23 2022, 3:07 AM

This LGTM.

This revision is now accepted and ready to land.Nov 23 2022, 3:07 AM