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Differential D138106

[AMDGPU][GISel] Add lshr/add -> uaddo combine
AbandonedPublic

Authored by Pierre-vh on Nov 16 2022, 2:11 AM.

Details

Reviewers
arsenm
foad
Summary

GISel equivalent for D137705

Depends on D137705

Diff Detail

Event Timeline

Pierre-vh created this revision.Nov 16 2022, 2:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 16 2022, 2:11 AM
Herald added subscribers: kosarev, kerbowa, hiraditya and 5 others. · View Herald Transcript
Pierre-vh requested review of this revision.Nov 16 2022, 2:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 16 2022, 2:11 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B197942: Diff 475734.Nov 16 2022, 3:16 AM
Pierre-vh abandoned this revision.Nov 28 2022, 6:57 AM

D138814

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
11 lines
3 lines
73 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
264 lines
292 lines

Diff 475734

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
def foldable_fneg_matchdata : GIDefMatchData<"MachineInstr *">; def foldable_fneg_matchdata : GIDefMatchData<"MachineInstr *">;
def foldable_fneg : GICombineRule< def foldable_fneg : GICombineRule<
(defs root:$ffn, foldable_fneg_matchdata:$matchinfo), (defs root:$ffn, foldable_fneg_matchdata:$matchinfo),
(match (wip_match_opcode G_FNEG):$ffn, (match (wip_match_opcode G_FNEG):$ffn,
[{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]), [{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]),
(apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>; (apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>;
def shr_add_to_uaddo_matchdata : GIDefMatchData<"MachineInstr *">;
def shr_add_to_uaddo : GICombineRule<
(defs root:$op, shr_add_to_uaddo_matchdata:$matchinfo),
(match (wip_match_opcode G_LSHR, G_UNMERGE_VALUES):$op,
[{ return Helper.matchShrAddToUAddo(*${op}, ${matchinfo}); }]),
(apply [{ Helper.applyShrAddToUAddo(*${op}, ${matchinfo}); }])>;
// Combines which should only apply on SI/VI // Combines which should only apply on SI/VI
def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>; def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper< def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
"AMDGPUGenPreLegalizerCombinerHelper", "AMDGPUGenPreLegalizerCombinerHelper",
[all_combines, clamp_i64_to_i16, foldable_fneg]> { [all_combines, clamp_i64_to_i16, foldable_fneg, shr_add_to_uaddo]> {
let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule"; let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule";
let StateClass = "AMDGPUPreLegalizerCombinerHelperState"; let StateClass = "AMDGPUPreLegalizerCombinerHelperState";
let AdditionalArguments = []; let AdditionalArguments = [];
} }
def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper< def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
"AMDGPUGenPostLegalizerCombinerHelper", "AMDGPUGenPostLegalizerCombinerHelper",
[all_combines, gfx6gfx7_combines, [all_combines, gfx6gfx7_combines,
uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg, uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
rcp_sqrt_to_rsq]> { rcp_sqrt_to_rsq, shr_add_to_uaddo]> {
let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule"; let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
let StateClass = "AMDGPUPostLegalizerCombinerHelperState"; let StateClass = "AMDGPUPostLegalizerCombinerHelperState";
let AdditionalArguments = []; let AdditionalArguments = [];
} }
def AMDGPURegBankCombinerHelper : GICombinerHelper< def AMDGPURegBankCombinerHelper : GICombinerHelper<
"AMDGPUGenRegBankCombinerHelper", "AMDGPUGenRegBankCombinerHelper",
[zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain, [zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain,
fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp]> { fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp]> {
let DisableRuleOption = "amdgpuregbankcombiner-disable-rule"; let DisableRuleOption = "amdgpuregbankcombiner-disable-rule";
let StateClass = "AMDGPURegBankCombinerHelperState"; let StateClass = "AMDGPURegBankCombinerHelperState";
let AdditionalArguments = []; let AdditionalArguments = [];
} }

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h

Show All 17 Lines
using namespace llvm; using namespace llvm;
class AMDGPUCombinerHelper : public CombinerHelper { class AMDGPUCombinerHelper : public CombinerHelper {
public: public:
using CombinerHelper::CombinerHelper; using CombinerHelper::CombinerHelper;
bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo); bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo); void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
bool matchShrAddToUAddo(MachineInstr &MI, MachineInstr *&MatchInfo);
void applyShrAddToUAddo(MachineInstr &MI, MachineInstr *&MatchInfo);
}; };

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp

//=== lib/CodeGen/GlobalISel/AMDGPUCombinerHelper.cpp ---------------------===// //=== lib/CodeGen/GlobalISel/AMDGPUCombinerHelper.cpp ---------------------===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "AMDGPUCombinerHelper.h" #include "AMDGPUCombinerHelper.h"
#include "GCNSubtarget.h" #include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/IR/IntrinsicsAMDGPU.h" #include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
using namespace llvm; using namespace llvm;
using namespace MIPatternMatch; using namespace MIPatternMatch;
LLVM_READNONE LLVM_READNONE
▲ Show 20 Lines • Show All 355 Lines • ▼ Show 20 Lines if (MRI.hasOneNonDBGUse(MatchInfoDst)) {
// Recreate non negated value for other uses of old MatchInfoDst // Recreate non negated value for other uses of old MatchInfoDst
auto NextInst = ++MatchInfo->getIterator(); auto NextInst = ++MatchInfo->getIterator();
Builder.setInstrAndDebugLoc(*NextInst); Builder.setInstrAndDebugLoc(*NextInst);
Builder.buildFNeg(MatchInfoDst, NegatedMatchInfo, MI.getFlags()); Builder.buildFNeg(MatchInfoDst, NegatedMatchInfo, MI.getFlags());
} }
MI.eraseFromParent(); MI.eraseFromParent();
} }
bool AMDGPUCombinerHelper::matchShrAddToUAddo(MachineInstr &MI,
MachineInstr *&MatchInfo) {
// fold (i64 (shr (add a, b), 32))
// -> (i64 (zext (uaddo (i32 (trunc a)), (i32 (trunc b)).overflow))
// iff a/b have >= 32 leading zeroes
// (usually a/b are i32->i64 zexts)
//
// NOTE: After legalization, we may not have LSHR anymore but instead a
// G_UNMERGE_VALUES.
// This combine could be adapted to support this variant as well if needed,
// but the cases we're interested in should be already present
// pre-legalization (coming from user code) so that variant is currently not
// implemented.
Register Dst = MI.getOperand(0).getReg();
LLT S64 = LLT::scalar(64);
LLT S32 = LLT::scalar(32);
if (MRI.getType(Dst) != S64)
return false;
Register A, B;
Optional<ValueAndVReg> ShiftAmt;
if (!mi_match(MI, MRI,
m_GLShr(m_GAdd(m_Reg(A), m_Reg(B)), m_GCst(ShiftAmt))) ||
ShiftAmt->Value != 32)
return false;
GISelKnownBits *KB = getKnownBits();
if (KB->getKnownBits(A).countMinLeadingZeros() < 32 ||
KB->getKnownBits(B).countMinLeadingZeros() < 32)
return false;
// Also check the users of the add. We only perform the combine if all users
// are either the LSHR, or truncs to i32.
for (MachineInstr &User :
MRI.use_nodbg_instructions(MI.getOperand(1).getReg())) {
if (&User != &MI && (User.getOpcode() != AMDGPU::G_TRUNC ||
MRI.getType(User.getOperand(0).getReg()) != S32))
return false;
}
MatchInfo = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI);
return true;
}
void AMDGPUCombinerHelper::applyShrAddToUAddo(MachineInstr &MI,
MachineInstr *&MatchInfo) {
// add -> (i64 (zext (uaddo (i32 (trunc a)), (i32 (trunc b)))))
// lshr -> (i64 (zext uaddo.overflow))
//
// Note that since we checked in the "match" function that the add's users
// are all truncs to i32, the zext of the uaddo will be folded out.
Register Dst = MI.getOperand(0).getReg();
Register AddDst = MatchInfo->getOperand(0).getReg();
Register LHS = MatchInfo->getOperand(1).getReg();
Register RHS = MatchInfo->getOperand(2).getReg();
LLT S32 = LLT::scalar(32);
LLT S1 = LLT::scalar(1);
Builder.setInstrAndDebugLoc(MI);
LHS = Builder.buildTrunc(S32, LHS).getReg(0);
RHS = Builder.buildTrunc(S32, RHS).getReg(0);
MachineInstr *UAddo = Builder.buildUAddo(S32, S1, LHS, RHS);
Builder.buildZExt(AddDst, UAddo->getOperand(0).getReg());
Builder.buildZExt(Dst, UAddo->getOperand(1).getReg());
MI.eraseFromParent();
MatchInfo->eraseFromParent();
}
No newline at end of file

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-add-to-uaddo.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,PRE
# RUN: llc -march=amdgcn -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,POST
---
name: good_zext_src
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: good_zext_src
; CHECK: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a32:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b32:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO %a32, %b32
; CHECK-NEXT: %truclshr:_(s32) = G_ZEXT [[UADDO1]](s1)
; CHECK-NEXT: $vgpr0 = COPY [[UADDO]](s32)
; CHECK-NEXT: $vgpr1 = COPY %truclshr(s32)
%a32:_(s32) = COPY $vgpr0
%b32:_(s32) = COPY $vgpr1
%a64:_(s64) = G_ZEXT %a32
%b64:_(s64) = G_ZEXT %b32
%add:_(s64) = G_ADD %a64, %b64
%c32:_(s64) = G_CONSTANT i64 32
%lshr:_(s64) = G_LSHR %add, %c32
%truncadd:_(s32) = G_TRUNC %add
%truclshr:_(s32) = G_TRUNC %lshr
$vgpr0 = COPY %truncadd
$vgpr1 = COPY %truclshr
...
---
name: good_constant_src
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: good_constant_src
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a32:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b64:_(s64) = G_CONSTANT i64 4294967290
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %b64(s64)
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO %a32, [[TRUNC]]
; CHECK-NEXT: %truclshr:_(s32) = G_ZEXT [[UADDO1]](s1)
; CHECK-NEXT: $vgpr0 = COPY [[UADDO]](s32)
; CHECK-NEXT: $vgpr1 = COPY %truclshr(s32)
%a32:_(s32) = COPY $vgpr0
%a64:_(s64) = G_ZEXT %a32
%b64:_(s64) = G_CONSTANT i64 4294967290 ; 0xFFFFFFFA
%add:_(s64) = G_ADD %a64, %b64
%c32:_(s64) = G_CONSTANT i64 32
%lshr:_(s64) = G_LSHR %add, %c32
%truncadd:_(s32) = G_TRUNC %add
%truclshr:_(s32) = G_TRUNC %lshr
$vgpr0 = COPY %truncadd
$vgpr1 = COPY %truclshr
...
---
name: good_multi_users
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: good_multi_users
; CHECK: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a32:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b32:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO %a32, %b32
; CHECK-NEXT: %truclshr:_(s32) = G_ZEXT [[UADDO1]](s1)
; CHECK-NEXT: $vgpr0 = COPY [[UADDO]](s32)
; CHECK-NEXT: $vgpr1 = COPY %truclshr(s32)
; CHECK-NEXT: $vgpr2 = COPY [[UADDO]](s32)
%a32:_(s32) = COPY $vgpr0
%b32:_(s32) = COPY $vgpr1
%a64:_(s64) = G_ZEXT %a32
%b64:_(s64) = G_ZEXT %b32
%add:_(s64) = G_ADD %a64, %b64
%c32:_(s64) = G_CONSTANT i64 32
%lshr:_(s64) = G_LSHR %add, %c32
%truncadd:_(s32) = G_TRUNC %add
%truncadd2:_(s32) = G_TRUNC %add
%truclshr:_(s32) = G_TRUNC %lshr
$vgpr0 = COPY %truncadd
$vgpr1 = COPY %truclshr
$vgpr2 = COPY %truncadd2
...
---
name: bad_src
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; PRE-LABEL: name: bad_src
; PRE: liveins: $vgpr0_vgpr1, $vgpr2
; PRE-NEXT: {{ $}}
; PRE-NEXT: %a64:_(s64) = COPY $vgpr0_vgpr1
; PRE-NEXT: %b32:_(s32) = COPY $vgpr2
; PRE-NEXT: %b64:_(s64) = G_ZEXT %b32(s32)
; PRE-NEXT: %add:_(s64) = G_ADD %a64, %b64
; PRE-NEXT: %c32:_(s64) = G_CONSTANT i64 33
; PRE-NEXT: %lshr:_(s64) = G_LSHR %add, %c32(s64)
; PRE-NEXT: %truncadd:_(s32) = G_TRUNC %add(s64)
; PRE-NEXT: %truncadd2:_(s32) = G_TRUNC %add(s64)
; PRE-NEXT: %truclshr:_(s32) = G_TRUNC %lshr(s64)
; PRE-NEXT: $vgpr0 = COPY %truncadd(s32)
; PRE-NEXT: $vgpr1 = COPY %truclshr(s32)
; PRE-NEXT: $vgpr2 = COPY %truncadd2(s32)
; POST-LABEL: name: bad_src
; POST: liveins: $vgpr0_vgpr1, $vgpr2
; POST-NEXT: {{ $}}
; POST-NEXT: %a64:_(s64) = COPY $vgpr0_vgpr1
; POST-NEXT: %b32:_(s32) = COPY $vgpr2
; POST-NEXT: %b64:_(s64) = G_ZEXT %b32(s32)
; POST-NEXT: %add:_(s64) = G_ADD %a64, %b64
; POST-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %add(s64)
; POST-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; POST-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; POST-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; POST-NEXT: %lshr:_(s64) = G_MERGE_VALUES [[LSHR]](s32), [[C1]](s32)
; POST-NEXT: %truncadd:_(s32) = G_TRUNC %add(s64)
; POST-NEXT: %truncadd2:_(s32) = G_TRUNC %add(s64)
; POST-NEXT: %truclshr:_(s32) = G_TRUNC %lshr(s64)
; POST-NEXT: $vgpr0 = COPY %truncadd(s32)
; POST-NEXT: $vgpr1 = COPY %truclshr(s32)
; POST-NEXT: $vgpr2 = COPY %truncadd2(s32)
%a64:_(s64) = COPY $vgpr0_vgpr1
%b32:_(s32) = COPY $vgpr2
%b64:_(s64) = G_ZEXT %b32
%add:_(s64) = G_ADD %a64, %b64
%c32:_(s64) = G_CONSTANT i64 33
%lshr:_(s64) = G_LSHR %add, %c32
%truncadd:_(s32) = G_TRUNC %add
%truncadd2:_(s32) = G_TRUNC %add
%truclshr:_(s32) = G_TRUNC %lshr
$vgpr0 = COPY %truncadd
$vgpr1 = COPY %truclshr
$vgpr2 = COPY %truncadd2
...
---
name: bad_constant_src
body: |
bb.0:
liveins: $vgpr0
; PRE-LABEL: name: bad_constant_src
; PRE: liveins: $vgpr0
; PRE-NEXT: {{ $}}
; PRE-NEXT: %a64:_(s64) = G_CONSTANT i64 8589934591
; PRE-NEXT: %b32:_(s32) = COPY $vgpr0
; PRE-NEXT: %b64:_(s64) = G_ZEXT %b32(s32)
; PRE-NEXT: %add:_(s64) = G_ADD %a64, %b64
; PRE-NEXT: %c32:_(s64) = G_CONSTANT i64 32
; PRE-NEXT: %lshr:_(s64) = G_LSHR %add, %c32(s64)
; PRE-NEXT: %truncadd:_(s32) = G_TRUNC %add(s64)
; PRE-NEXT: %truclshr:_(s32) = G_TRUNC %lshr(s64)
; PRE-NEXT: $vgpr0 = COPY %truncadd(s32)
; PRE-NEXT: $vgpr1 = COPY %truclshr(s32)
; POST-LABEL: name: bad_constant_src
; POST: liveins: $vgpr0
; POST-NEXT: {{ $}}
; POST-NEXT: %a64:_(s64) = G_CONSTANT i64 8589934591
; POST-NEXT: %b32:_(s32) = COPY $vgpr0
; POST-NEXT: %b64:_(s64) = G_ZEXT %b32(s32)
; POST-NEXT: %add:_(s64) = G_ADD %a64, %b64
; POST-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %add(s64)
; POST-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; POST-NEXT: %lshr:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[C]](s32)
; POST-NEXT: %truncadd:_(s32) = G_TRUNC %add(s64)
; POST-NEXT: %truclshr:_(s32) = G_TRUNC %lshr(s64)
; POST-NEXT: $vgpr0 = COPY %truncadd(s32)
; POST-NEXT: $vgpr1 = COPY %truclshr(s32)
%a64:_(s64) = G_CONSTANT i64 8589934591 ; 0x1FFFFFFFF
%b32:_(s32) = COPY $vgpr0
%b64:_(s64) = G_ZEXT %b32
%add:_(s64) = G_ADD %a64, %b64
%c32:_(s64) = G_CONSTANT i64 32
%lshr:_(s64) = G_LSHR %add, %c32
%truncadd:_(s32) = G_TRUNC %add
%truclshr:_(s32) = G_TRUNC %lshr
$vgpr0 = COPY %truncadd
$vgpr1 = COPY %truclshr
...
---
name: bad_shift_amt_33
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; PRE-LABEL: name: bad_shift_amt_33
; PRE: liveins: $vgpr0, $vgpr1
; PRE-NEXT: {{ $}}
; PRE-NEXT: %a32:_(s32) = COPY $vgpr0
; PRE-NEXT: %b32:_(s32) = COPY $vgpr1
; PRE-NEXT: %a64:_(s64) = G_ZEXT %a32(s32)
; PRE-NEXT: %b64:_(s64) = G_ZEXT %b32(s32)
; PRE-NEXT: %add:_(s64) = G_ADD %a64, %b64
; PRE-NEXT: %c32:_(s64) = G_CONSTANT i64 33
; PRE-NEXT: %lshr:_(s64) = G_LSHR %add, %c32(s64)
; PRE-NEXT: %truncadd:_(s32) = G_TRUNC %add(s64)
; PRE-NEXT: %truclshr:_(s32) = G_TRUNC %lshr(s64)
; PRE-NEXT: $vgpr0 = COPY %truncadd(s32)
; PRE-NEXT: $vgpr1 = COPY %truclshr(s32)
; POST-LABEL: name: bad_shift_amt_33
; POST: liveins: $vgpr0, $vgpr1
; POST-NEXT: {{ $}}
; POST-NEXT: %a32:_(s32) = COPY $vgpr0
; POST-NEXT: %b32:_(s32) = COPY $vgpr1
; POST-NEXT: %a64:_(s64) = G_ZEXT %a32(s32)
; POST-NEXT: %b64:_(s64) = G_ZEXT %b32(s32)
; POST-NEXT: %add:_(s64) = G_ADD %a64, %b64
; POST-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %add(s64)
; POST-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; POST-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; POST-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; POST-NEXT: %lshr:_(s64) = G_MERGE_VALUES [[LSHR]](s32), [[C1]](s32)
; POST-NEXT: %truncadd:_(s32) = G_TRUNC %add(s64)
; POST-NEXT: %truclshr:_(s32) = G_TRUNC %lshr(s64)
; POST-NEXT: $vgpr0 = COPY %truncadd(s32)
; POST-NEXT: $vgpr1 = COPY %truclshr(s32)
%a32:_(s32) = COPY $vgpr0
%b32:_(s32) = COPY $vgpr1
%a64:_(s64) = G_ZEXT %a32
%b64:_(s64) = G_ZEXT %b32
%add:_(s64) = G_ADD %a64, %b64
%c32:_(s64) = G_CONSTANT i64 33
%lshr:_(s64) = G_LSHR %add, %c32
%truncadd:_(s32) = G_TRUNC %add
%truclshr:_(s32) = G_TRUNC %lshr
$vgpr0 = COPY %truncadd
$vgpr1 = COPY %truclshr
...
---
name: bad_shift_amt_31
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: bad_shift_amt_31
; CHECK: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a32:_(s32) = COPY $vgpr0
; CHECK-NEXT: %b32:_(s32) = COPY $vgpr1
; CHECK-NEXT: %a64:_(s64) = G_ZEXT %a32(s32)
; CHECK-NEXT: %b64:_(s64) = G_ZEXT %b32(s32)
; CHECK-NEXT: %add:_(s64) = G_ADD %a64, %b64
; CHECK-NEXT: %c32:_(s64) = G_CONSTANT i64 31
; CHECK-NEXT: %lshr:_(s64) = G_LSHR %add, %c32(s64)
; CHECK-NEXT: %truncadd:_(s32) = G_TRUNC %add(s64)
; CHECK-NEXT: %truclshr:_(s32) = G_TRUNC %lshr(s64)
; CHECK-NEXT: $vgpr0 = COPY %truncadd(s32)
; CHECK-NEXT: $vgpr1 = COPY %truclshr(s32)
%a32:_(s32) = COPY $vgpr0
%b32:_(s32) = COPY $vgpr1
%a64:_(s64) = G_ZEXT %a32
%b64:_(s64) = G_ZEXT %b32
%add:_(s64) = G_ADD %a64, %b64
%c32:_(s64) = G_CONSTANT i64 31
%lshr:_(s64) = G_LSHR %add, %c32
%truncadd:_(s32) = G_TRUNC %add
%truclshr:_(s32) = G_TRUNC %lshr
$vgpr0 = COPY %truncadd
$vgpr1 = COPY %truclshr
...

llvm/test/CodeGen/AMDGPU/add_shr_carry.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefixes=VI,SDAG-VI %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefixes=VI,SDAG-VI %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9,SDAG-GFX9 %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9,SDAG-GFX9 %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10,SDAG-GFX10 %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10,SDAG-GFX10 %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11,SDAG-GFX11 %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11,SDAG-GFX11 %s
; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefixes=VI,GISEL-VI %s ; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefixes=VI,GISEL-VI %s
; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s ; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10,GISEL-GFX10 %s ; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10,GISEL-GFX10 %s
; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11,GISEL-GFX11 %s ; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11,GISEL-GFX11 %s
define i64 @basic_zext(i32 %a, i32 %b, i64 %c) { define i64 @basic_zext(i32 %a, i32 %b, i64 %c) {
; SDAG-VI-LABEL: basic_zext: ; VI-LABEL: basic_zext:
; SDAG-VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; SDAG-VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; SDAG-VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX9-LABEL: basic_zext: ; GFX9-LABEL: basic_zext:
; SDAG-GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; SDAG-GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX10-LABEL: basic_zext: ; GFX10-LABEL: basic_zext:
; SDAG-GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; SDAG-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX10-NEXT: v_add_co_u32 v0, s4, v0, v1 ; GFX10-NEXT: v_add_co_u32 v0, s4, v0, v1
; SDAG-GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX11-LABEL: basic_zext: ; GFX11-LABEL: basic_zext:
; SDAG-GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX11-NEXT: v_add_co_u32 v0, s0, v0, v1 ; GFX11-NEXT: v_add_co_u32 v0, s0, v0, v1
; SDAG-GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: basic_zext:
; GISEL-VI: ; %bb.0: ; %entry
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GISEL-VI-NEXT: v_addc_u32_e64 v0, s[4:5], 0, 0, vcc
; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX9-LABEL: basic_zext:
; GISEL-GFX9: ; %bb.0: ; %entry
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GISEL-GFX9-NEXT: v_addc_co_u32_e64 v0, s[4:5], 0, 0, vcc
; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX10-LABEL: basic_zext:
; GISEL-GFX10: ; %bb.0: ; %entry
; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX10-NEXT: v_add_co_u32 v0, s4, v0, v1
; GISEL-GFX10-NEXT: v_add_co_ci_u32_e64 v0, s4, 0, 0, s4
; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-LABEL: basic_zext:
; GISEL-GFX11: ; %bb.0: ; %entry
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX11-NEXT: v_add_co_u32 v0, s0, v0, v1
; GISEL-GFX11-NEXT: v_add_co_ci_u32_e64 v0, null, 0, 0, s0
; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%a.zext = zext i32 %a to i64 %a.zext = zext i32 %a to i64
%b.zext = zext i32 %b to i64 %b.zext = zext i32 %b to i64
%add.a.b = add i64 %a.zext, %b.zext %add.a.b = add i64 %a.zext, %b.zext
%shr = lshr i64 %add.a.b, 32 %shr = lshr i64 %add.a.b, 32
ret i64 %shr ret i64 %shr
} }
define i64 @basic_cst_32leadingzeroes(i32 %b, i64 %c) { define i64 @basic_cst_32leadingzeroes(i32 %b, i64 %c) {
; SDAG-VI-LABEL: basic_cst_32leadingzeroes: ; VI-LABEL: basic_cst_32leadingzeroes:
; SDAG-VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
; SDAG-VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; SDAG-VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX9-LABEL: basic_cst_32leadingzeroes: ; GFX9-LABEL: basic_cst_32leadingzeroes:
; SDAG-GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX9-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0
; SDAG-GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX10-LABEL: basic_cst_32leadingzeroes: ; SDAG-GFX10-LABEL: basic_cst_32leadingzeroes:
; SDAG-GFX10: ; %bb.0: ; %entry ; SDAG-GFX10: ; %bb.0: ; %entry
; SDAG-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SDAG-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; SDAG-GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX10-NEXT: v_add_co_u32 v0, s4, v0, -1 ; SDAG-GFX10-NEXT: v_add_co_u32 v0, s4, v0, -1
; SDAG-GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 ; SDAG-GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX10-NEXT: s_setpc_b64 s[30:31] ; SDAG-GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX11-LABEL: basic_cst_32leadingzeroes: ; SDAG-GFX11-LABEL: basic_cst_32leadingzeroes:
; SDAG-GFX11: ; %bb.0: ; %entry ; SDAG-GFX11: ; %bb.0: ; %entry
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; SDAG-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX11-NEXT: v_add_co_u32 v0, s0, v0, -1 ; SDAG-GFX11-NEXT: v_add_co_u32 v0, s0, v0, -1
; SDAG-GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; SDAG-GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] ; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
; ;
; GISEL-VI-LABEL: basic_cst_32leadingzeroes:
; GISEL-VI: ; %bb.0: ; %entry
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
; GISEL-VI-NEXT: v_addc_u32_e64 v0, s[4:5], 0, 0, vcc
; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX9-LABEL: basic_cst_32leadingzeroes:
; GISEL-GFX9: ; %bb.0: ; %entry
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX9-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0
; GISEL-GFX9-NEXT: v_addc_co_u32_e64 v0, s[4:5], 0, 0, vcc
; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX10-LABEL: basic_cst_32leadingzeroes: ; GISEL-GFX10-LABEL: basic_cst_32leadingzeroes:
; GISEL-GFX10: ; %bb.0: ; %entry ; GISEL-GFX10: ; %bb.0: ; %entry
; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GISEL-GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX10-NEXT: v_add_co_u32 v0, s4, -1, v0 ; GISEL-GFX10-NEXT: v_add_co_u32 v0, s4, -1, v0
; GISEL-GFX10-NEXT: v_add_co_ci_u32_e64 v0, s4, 0, 0, s4 ; GISEL-GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX10-NEXT: s_setpc_b64 s[30:31] ; GISEL-GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GISEL-GFX11-LABEL: basic_cst_32leadingzeroes: ; GISEL-GFX11-LABEL: basic_cst_32leadingzeroes:
; GISEL-GFX11: ; %bb.0: ; %entry ; GISEL-GFX11: ; %bb.0: ; %entry
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX11-NEXT: v_add_co_u32 v0, s0, -1, v0 ; GISEL-GFX11-NEXT: v_add_co_u32 v0, s0, -1, v0
; GISEL-GFX11-NEXT: v_add_co_ci_u32_e64 v0, null, 0, 0, s0 ; GISEL-GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] ; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%b.zext = zext i32 %b to i64 %b.zext = zext i32 %b to i64
%add.a.b = add i64 4294967295, %b.zext ; 0xFFFFFFFF %add.a.b = add i64 4294967295, %b.zext ; 0xFFFFFFFF
%shr = lshr i64 %add.a.b, 32 %shr = lshr i64 %add.a.b, 32
ret i64 %shr ret i64 %shr
} }
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
entry: entry:
%b.zext = zext i32 %b to i64 %b.zext = zext i32 %b to i64
%add.a.b = add i64 8589934591, %b.zext ; 0x1FFFFFFFF %add.a.b = add i64 8589934591, %b.zext ; 0x1FFFFFFFF
%shr = lshr i64 %add.a.b, 32 %shr = lshr i64 %add.a.b, 32
ret i64 %shr ret i64 %shr
} }
define <3 x i32> @add3_i96(<3 x i32> %0, <3 x i32> %1) { define <3 x i32> @add3_i96(<3 x i32> %0, <3 x i32> %1) {
; SDAG-VI-LABEL: add3_i96: ; VI-LABEL: add3_i96:
; SDAG-VI: ; %bb.0: ; VI: ; %bb.0:
; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-VI-NEXT: v_add_u32_e32 v1, vcc, v4, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v4, v1
; SDAG-VI-NEXT: v_addc_u32_e64 v4, s[4:5], 0, 0, vcc ; VI-NEXT: v_addc_u32_e64 v4, s[4:5], 0, 0, vcc
; SDAG-VI-NEXT: v_add_u32_e32 v0, vcc, v3, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, v3, v0
; SDAG-VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SDAG-VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; SDAG-VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; SDAG-VI-NEXT: v_add_u32_e32 v2, vcc, v5, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, v5, v2
; SDAG-VI-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; SDAG-VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX9-LABEL: add3_i96: ; GFX9-LABEL: add3_i96:
; SDAG-GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v4, v1 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v4, v1
; SDAG-GFX9-NEXT: v_addc_co_u32_e64 v4, s[4:5], 0, 0, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v4, s[4:5], 0, 0, vcc
; SDAG-GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; SDAG-GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; SDAG-GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3
; SDAG-GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; SDAG-GFX9-NEXT: v_add3_u32 v2, v5, v2, v3 ; GFX9-NEXT: v_add3_u32 v2, v5, v2, v3
; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX10-LABEL: add3_i96: ; GFX10-LABEL: add3_i96:
; SDAG-GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; SDAG-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX10-NEXT: v_add_co_u32 v0, s4, v3, v0 ; GFX10-NEXT: v_add_co_u32 v0, s4, v3, v0
; SDAG-GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; SDAG-GFX10-NEXT: v_add_co_u32 v1, s4, v4, v1 ; GFX10-NEXT: v_add_co_u32 v1, s4, v4, v1
; SDAG-GFX10-NEXT: v_add_co_ci_u32_e64 v4, s4, 0, 0, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s4, 0, 0, s4
; SDAG-GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; SDAG-GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
; SDAG-GFX10-NEXT: v_add3_u32 v2, v5, v2, v3 ; GFX10-NEXT: v_add3_u32 v2, v5, v2, v3
; SDAG-GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; SDAG-GFX11-LABEL: add3_i96: ; GFX11-LABEL: add3_i96:
; SDAG-GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX11-NEXT: v_add_co_u32 v0, s0, v3, v0 ; GFX11-NEXT: v_add_co_u32 v0, s0, v3, v0
; SDAG-GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; SDAG-GFX11-NEXT: v_add_co_u32 v1, s0, v4, v1 ; GFX11-NEXT: v_add_co_u32 v1, s0, v4, v1
; SDAG-GFX11-NEXT: v_add_co_ci_u32_e64 v4, null, 0, 0, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v4, null, 0, 0, s0
; SDAG-GFX11-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3 ; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; SDAG-GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
; SDAG-GFX11-NEXT: v_add3_u32 v2, v5, v2, v3 ; GFX11-NEXT: v_add3_u32 v2, v5, v2, v3
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: add3_i96:
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-VI-NEXT: v_add_u32_e32 v0, vcc, v3, v0
; GISEL-VI-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
; GISEL-VI-NEXT: v_add_u32_e32 v1, vcc, v4, v1
; GISEL-VI-NEXT: v_addc_u32_e64 v4, s[4:5], 0, 0, vcc
; GISEL-VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GISEL-VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; GISEL-VI-NEXT: v_add_u32_e32 v2, vcc, v5, v2
; GISEL-VI-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX9-LABEL: add3_i96:
; GISEL-GFX9: ; %bb.0:
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; GISEL-GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; GISEL-GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v4, v1
; GISEL-GFX9-NEXT: v_addc_co_u32_e64 v4, s[4:5], 0, 0, vcc
; GISEL-GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3
; GISEL-GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GISEL-GFX9-NEXT: v_add3_u32 v2, v5, v2, v3
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX10-LABEL: add3_i96:
; GISEL-GFX10: ; %bb.0:
; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX10-NEXT: v_add_co_u32 v0, s4, v3, v0
; GISEL-GFX10-NEXT: v_add_co_ci_u32_e64 v3, s4, 0, 0, s4
; GISEL-GFX10-NEXT: v_add_co_u32 v1, s4, v4, v1
; GISEL-GFX10-NEXT: v_add_co_ci_u32_e64 v4, s4, 0, 0, s4
; GISEL-GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GISEL-GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
; GISEL-GFX10-NEXT: v_add3_u32 v2, v5, v2, v3
; GISEL-GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-LABEL: add3_i96:
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX11-NEXT: v_add_co_u32 v0, s0, v3, v0
; GISEL-GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s0
; GISEL-GFX11-NEXT: v_add_co_u32 v1, s0, v4, v1
; GISEL-GFX11-NEXT: v_add_co_ci_u32_e64 v4, null, 0, 0, s0
; GISEL-GFX11-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GISEL-GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
; GISEL-GFX11-NEXT: v_add3_u32 v2, v5, v2, v3
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
%3 = extractelement <3 x i32> %0, i64 0 %3 = extractelement <3 x i32> %0, i64 0
%4 = zext i32 %3 to i64 %4 = zext i32 %3 to i64
%5 = extractelement <3 x i32> %1, i64 0 %5 = extractelement <3 x i32> %1, i64 0
%6 = zext i32 %5 to i64 %6 = zext i32 %5 to i64
%7 = add nuw nsw i64 %6, %4 %7 = add nuw nsw i64 %6, %4
%8 = extractelement <3 x i32> %0, i64 1 %8 = extractelement <3 x i32> %0, i64 1
%9 = zext i32 %8 to i64 %9 = zext i32 %8 to i64
%10 = extractelement <3 x i32> %1, i64 1 %10 = extractelement <3 x i32> %1, i64 1
Show All 9 Lines; GFX11-NEXT: s_setpc_b64 s[30:31]
%20 = add i32 %17, %19 %20 = add i32 %17, %19
%21 = trunc i64 %7 to i32 %21 = trunc i64 %7 to i32
%22 = insertelement <3 x i32> undef, i32 %21, i32 0 %22 = insertelement <3 x i32> undef, i32 %21, i32 0
%23 = trunc i64 %14 to i32 %23 = trunc i64 %14 to i32
%24 = insertelement <3 x i32> %22, i32 %23, i32 1 %24 = insertelement <3 x i32> %22, i32 %23, i32 1
%25 = insertelement <3 x i32> %24, i32 %20, i32 2 %25 = insertelement <3 x i32> %24, i32 %20, i32 2
ret <3 x i32> %25 ret <3 x i32> %25
} }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX10: {{.*}}
; GFX11: {{.*}}
; GFX9: {{.*}}
; VI: {{.*}}