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Differential D138104

[AMDGPU] Precommit add_shr_carry test
AbandonedPublic

Authored by Pierre-vh on Nov 16 2022, 1:00 AM.

Details

Reviewers
arsenm
Summary

Precommit a test for a future DAG/GISel combine.

Diff Detail

Event Timeline

Pierre-vh created this revision.Nov 16 2022, 1:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 16 2022, 1:00 AM
Herald added subscribers: kosarev, kerbowa, tpr and 4 others. · View Herald Transcript
Pierre-vh requested review of this revision.Nov 16 2022, 1:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 16 2022, 1:00 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Pierre-vh mentioned this in D137705: [AMDGPU] Add DAG Combine for right-shift carry add to uaddo.Nov 16 2022, 1:00 AM
Harbormaster completed remote builds in B197934: Diff 475722.Nov 16 2022, 1:40 AM
Pierre-vh added a child revision: D137705: [AMDGPU] Add DAG Combine for right-shift carry add to uaddo.Nov 16 2022, 2:10 AM
arsenm added inline comments.Nov 16 2022, 8:37 AM
llvm/test/CodeGen/AMDGPU/add_shr_carry.ll
53

Add some negative cases where the shift amount is wrong, and the type sizes aren't right

188

I guess this is OK, but also add an actual i96 test if we don't have that already?

241–242

Use named values

arsenm requested changes to this revision.Nov 16 2022, 2:57 PM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/add_shr_carry.ll
53

Also as noted in the other review, multi use test?

This revision now requires changes to proceed.Nov 16 2022, 2:57 PM
Pierre-vh abandoned this revision.Nov 28 2022, 6:57 AM

D138814

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
263 lines

Diff 475722

llvm/test/CodeGen/AMDGPU/add_shr_carry.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefixes=VI,SDAG-VI %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9,SDAG-GFX9 %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10,SDAG-GFX10 %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11,SDAG-GFX11 %s
; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefixes=VI,GISEL-VI %s
; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10,GISEL-GFX10 %s
; RUN: llc -global-isel < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11,GISEL-GFX11 %s
define i64 @basic_zext(i32 %a, i32 %b, i64 %c) {
; VI-LABEL: basic_zext:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; VI-NEXT: v_addc_u32_e64 v0, s[4:5], 0, 0, vcc
; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: basic_zext:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e64 v0, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: basic_zext:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_co_u32 v0, s4, v0, v1
; GFX10-NEXT: v_add_co_ci_u32_e64 v0, s4, 0, 0, s4
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: basic_zext:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_add_co_u32 v0, s0, v0, v1
; GFX11-NEXT: v_add_co_ci_u32_e64 v0, null, 0, 0, s0
; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%a.zext = zext i32 %a to i64
%b.zext = zext i32 %b to i64
%add.a.b = add i64 %a.zext, %b.zext
%shr = lshr i64 %add.a.b, 32
ret i64 %shr
}
arsenmUnsubmitted
Not Done
ReplyInline Actions

Add some negative cases where the shift amount is wrong, and the type sizes aren't right

arsenm: Add some negative cases where the shift amount is wrong, and the type sizes aren't right
arsenmUnsubmitted
Not Done
ReplyInline Actions

Also as noted in the other review, multi use test?

arsenm: Also as noted in the other review, multi use test?
define i64 @basic_cst_32leadingzeroes(i32 %b, i64 %c) {
; VI-LABEL: basic_cst_32leadingzeroes:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
; VI-NEXT: v_addc_u32_e64 v0, s[4:5], 0, 0, vcc
; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: basic_cst_32leadingzeroes:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0
; GFX9-NEXT: v_addc_co_u32_e64 v0, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX10-LABEL: basic_cst_32leadingzeroes:
; SDAG-GFX10: ; %bb.0: ; %entry
; SDAG-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX10-NEXT: v_add_co_u32 v0, s4, v0, -1
; SDAG-GFX10-NEXT: v_add_co_ci_u32_e64 v0, s4, 0, 0, s4
; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX10-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX11-LABEL: basic_cst_32leadingzeroes:
; SDAG-GFX11: ; %bb.0: ; %entry
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX11-NEXT: v_add_co_u32 v0, s0, v0, -1
; SDAG-GFX11-NEXT: v_add_co_ci_u32_e64 v0, null, 0, 0, s0
; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX10-LABEL: basic_cst_32leadingzeroes:
; GISEL-GFX10: ; %bb.0: ; %entry
; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX10-NEXT: v_add_co_u32 v0, s4, -1, v0
; GISEL-GFX10-NEXT: v_add_co_ci_u32_e64 v0, s4, 0, 0, s4
; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-LABEL: basic_cst_32leadingzeroes:
; GISEL-GFX11: ; %bb.0: ; %entry
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX11-NEXT: v_add_co_u32 v0, s0, -1, v0
; GISEL-GFX11-NEXT: v_add_co_ci_u32_e64 v0, null, 0, 0, s0
; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%b.zext = zext i32 %b to i64
%add.a.b = add i64 4294967295, %b.zext ; 0xFFFFFFFF
%shr = lshr i64 %add.a.b, 32
ret i64 %shr
}
define i64 @basic_cst_no32leadingzeroes(i32 %b, i64 %c) {
; SDAG-VI-LABEL: basic_cst_no32leadingzeroes:
; SDAG-VI: ; %bb.0: ; %entry
; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
; SDAG-VI-NEXT: v_addc_u32_e64 v0, s[4:5], 0, 1, vcc
; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX9-LABEL: basic_cst_no32leadingzeroes:
; SDAG-GFX9: ; %bb.0: ; %entry
; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX9-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0
; SDAG-GFX9-NEXT: v_addc_co_u32_e64 v0, s[4:5], 0, 1, vcc
; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX10-LABEL: basic_cst_no32leadingzeroes:
; SDAG-GFX10: ; %bb.0: ; %entry
; SDAG-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX10-NEXT: v_add_co_u32 v0, s4, v0, -1
; SDAG-GFX10-NEXT: v_add_co_ci_u32_e64 v0, s4, 0, 1, s4
; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX10-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX11-LABEL: basic_cst_no32leadingzeroes:
; SDAG-GFX11: ; %bb.0: ; %entry
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; SDAG-GFX11-NEXT: v_add_co_u32 v0, s0, v0, -1
; SDAG-GFX11-NEXT: v_add_co_ci_u32_e64 v0, null, 0, 1, s0
; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-VI-LABEL: basic_cst_no32leadingzeroes:
; GISEL-VI: ; %bb.0: ; %entry
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
; GISEL-VI-NEXT: v_addc_u32_e64 v0, s[4:5], 1, 0, vcc
; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX9-LABEL: basic_cst_no32leadingzeroes:
; GISEL-GFX9: ; %bb.0: ; %entry
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX9-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0
; GISEL-GFX9-NEXT: v_addc_co_u32_e64 v0, s[4:5], 1, 0, vcc
; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX10-LABEL: basic_cst_no32leadingzeroes:
; GISEL-GFX10: ; %bb.0: ; %entry
; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX10-NEXT: v_add_co_u32 v0, s4, -1, v0
; GISEL-GFX10-NEXT: v_add_co_ci_u32_e64 v0, s4, 1, 0, s4
; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-LABEL: basic_cst_no32leadingzeroes:
; GISEL-GFX11: ; %bb.0: ; %entry
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GISEL-GFX11-NEXT: v_add_co_u32 v0, s0, -1, v0
; GISEL-GFX11-NEXT: v_add_co_ci_u32_e64 v0, null, 1, 0, s0
; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%b.zext = zext i32 %b to i64
%add.a.b = add i64 8589934591, %b.zext ; 0x1FFFFFFFF
%shr = lshr i64 %add.a.b, 32
ret i64 %shr
}
define <3 x i32> @add3_i96(<3 x i32> %0, <3 x i32> %1) {
arsenmUnsubmitted
Not Done
ReplyInline Actions

I guess this is OK, but also add an actual i96 test if we don't have that already?

arsenm: I guess this is OK, but also add an actual i96 test if we don't have that already?
; VI-LABEL: add3_i96:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, v3, v0
; VI-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, v4, v1
; VI-NEXT: v_addc_u32_e64 v4, s[4:5], 0, 0, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, v5, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: add3_i96:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v4, v1
; GFX9-NEXT: v_addc_co_u32_e64 v4, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
; GFX9-NEXT: v_add3_u32 v2, v5, v2, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: add3_i96:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_co_u32 v0, s4, v3, v0
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s4, 0, 0, s4
; GFX10-NEXT: v_add_co_u32 v1, s4, v4, v1
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s4, 0, 0, s4
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
; GFX10-NEXT: v_add3_u32 v2, v5, v2, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: add3_i96:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_add_co_u32 v0, s0, v3, v0
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s0
; GFX11-NEXT: v_add_co_u32 v1, s0, v4, v1
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, null, 0, 0, s0
; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
; GFX11-NEXT: v_add3_u32 v2, v5, v2, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%3 = extractelement <3 x i32> %0, i64 0
%4 = zext i32 %3 to i64
%5 = extractelement <3 x i32> %1, i64 0
%6 = zext i32 %5 to i64
arsenmUnsubmitted
Not Done
ReplyInline Actions

Use named values

arsenm: Use named values
%7 = add nuw nsw i64 %6, %4
%8 = extractelement <3 x i32> %0, i64 1
%9 = zext i32 %8 to i64
%10 = extractelement <3 x i32> %1, i64 1
%11 = zext i32 %10 to i64
%12 = add nuw nsw i64 %11, %9
%13 = lshr i64 %7, 32
%14 = add nuw nsw i64 %12, %13
%15 = extractelement <3 x i32> %0, i64 2
%16 = extractelement <3 x i32> %1, i64 2
%17 = add i32 %16, %15
%18 = lshr i64 %14, 32
%19 = trunc i64 %18 to i32
%20 = add i32 %17, %19
%21 = trunc i64 %7 to i32
%22 = insertelement <3 x i32> undef, i32 %21, i32 0
%23 = trunc i64 %14 to i32
%24 = insertelement <3 x i32> %22, i32 %23, i32 1
%25 = insertelement <3 x i32> %24, i32 %20, i32 2
ret <3 x i32> %25
}