[ARM][AArch64] Use StringRef in TargetParser structs

[tmatheson]

Summary

The invalid case is now represented by an empty StringRef rather than
a nullptr.

Previously ARCH_FEATURE was build from SUB_ARCH by prepending "+".
This is now reverse, so that the "+arch-feature" is now visible in
the .def, which is a bit clearer. This meant converting one StringSwitch
into a loop.

Removed getters which are now mostly unnecessary.

Removed some old FIXMEs.

[pratlucas]

llvm/include/llvm/Support/AArch64TargetParser.def

20–21

Having the lone "+" as arch_feature here looks a bit off. Could we remove the "invalid" entries from the def file completely?
Would it make sense to use the INVALID enum entries by themselves to handle unsuccessful parsing, or maybe use optional returns on the relevant methods?

[tmatheson]

llvm/include/llvm/Support/AArch64TargetParser.def

20–21

It does indeed look weird, but that's what it is already doing internally so there is NFC. This patch is already quite large so refactoring the invalid entries would be best done in a follow up.

[lenary]

I'm happy with this, and happy for the invalid case to be sorted in a follow-up.

[tmatheson]

Rebase after 8.9/9.4

[DavidSpickett]

This is now reverse, so that the "+arch-feature" is now visible in the .def, which is a bit clearer.

Clearer for what exactly.

llvm/lib/Support/AArch64TargetParser.cpp

110–111

Maybe this is just me but "!empty()" could just be "size()".

I know sometimes containers make empty cheaper but here it's just == 0 vs != 0.

[tmatheson]

In D138026#3933447, @DavidSpickett wrote:

This is now reverse, so that the "+arch-feature" is now visible in the .def, which is a bit clearer.

Clearer for what exactly.

Previously the string literal you would see in the ArmTargetParser.def was 'xyz', which would be stored on the struct as '+xyz' (a string literal created by a macro) and on the command line you would write +xyz. Now that it is written +xyz in the .def file, the correspondence between the three is more obvious, imho. Searching for +xyz will actually lead you to where it is defined.

llvm/lib/Support/AArch64TargetParser.cpp

110–111

For checking that "the feature is not the empty string", !empty() makes a lot more sense to me semantically than an implicit cast<bool>(size()). I'm trying to move away from the C-style code :) I would hope (haven't checked) that they compile to basically the same thing.

[DavidSpickett]

Searching for +xyz will actually lead you to where it is defined.

Sure, that makes sense (especially in the current state where the .def is the only documentation).

llvm/lib/Support/AArch64TargetParser.cpp

110–111

Agree to disagree, keep it as you prefer.

[tmatheson]

Rebase for CI

[tmatheson]

Update unittest TargetParserTest.cpp

[tschuett]

Optional<StringRef> is too verbose to model the invalid case?

[tmatheson]

In D138026#3934392, @tschuett wrote:

Optional<StringRef> is too verbose to model the invalid case?

Sorry I missed this before I pushed. Optional is a potential option (heh), it wasn't done here simply because I'm trying to keep the changes incremental. I will make a follow up patch if I can find something reasonable that works.

llvm/include/llvm/Support/AArch64TargetParser.h

enum ArchExtKind : uint64_t {
   AEK_SME2 =        1ULL << 43, // FEAT_SME2
   AEK_SVE2p1 =      1ULL << 44, // FEAT_SVE2p1
   AEK_SME2p1 =      1ULL << 45, // FEAT_SME2p1
   AEK_B16B16 =      1ULL << 46, // FEAT_B16B16
   AEK_SMEF16F16 =   1ULL << 47  // FEAT_SMEF16F16
 };
 
 enum class ArchKind {
-#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT) ID,
+#define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) ID,
 #include "AArch64TargetParser.def"
 };
 
 struct ArchNames {
-  const char *NameCStr;
-  size_t NameLength;
-  const char *SubArchCStr;
-  size_t SubArchLength;
+  StringRef Name;
+  StringRef ArchFeature;
   uint64_t ArchBaseExtensions;
   ArchKind ID;
 
-  StringRef getName() const { return StringRef(NameCStr, NameLength); }
-
-  // Sub-Arch name.
-  StringRef getSubArch() const {
-    return getArchFeature().substr(1, SubArchLength);
-  }
-
-  // Arch Feature name.
-  StringRef getArchFeature() const {
-    return StringRef(SubArchCStr, SubArchLength);
-  }
+  // Return ArchFeature without the leading "+".
+  StringRef getSubArch() const { return ArchFeature.substr(1); }
 };
 
 const ArchNames AArch64ARCHNames[] = {
-#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT)                        \
-  {NAME,          sizeof(NAME) - 1,     "+" SUB_ARCH, sizeof(SUB_ARCH),        \
-   ARCH_BASE_EXT, AArch64::ArchKind::ID},
+#define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT)                    \
+  {NAME, ARCH_FEATURE, ARCH_BASE_EXT, AArch64::ArchKind::ID},
 #include "AArch64TargetParser.def"
 };
 
 // List of Arch Extension names.
 struct ExtName {
-  const char *NameCStr;
-  size_t NameLength;
+  StringRef Name;
   uint64_t ID;
-  const char *Feature;
-  const char *NegFeature;
-
-  StringRef getName() const { return StringRef(NameCStr, NameLength); }
+  StringRef Feature;
+  StringRef NegFeature;
 };
 
 const ExtName AArch64ARCHExtNames[] = {
 #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                   \
-  {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE},
+  {NAME, ID, FEATURE, NEGFEATURE},
 #include "AArch64TargetParser.def"
 };
 
 // List of CPU names and their arches.
 // The same CPU can have multiple arches and can be default on multiple arches.
 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
 // When this becomes table-generated, we'd probably need two tables.
 struct CpuNames {
-  const char *NameCStr;
-  size_t NameLength;
+  StringRef Name;
   ArchKind ArchID;
   bool Default; // is $Name the default CPU for $ArchID ?
   uint64_t DefaultExtensions;
-
-  StringRef getName() const { return StringRef(NameCStr, NameLength); }
 };
 
 const CpuNames AArch64CPUNames[] = {
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)       \
-  {NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
+  {NAME, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
 #include "AArch64TargetParser.def"
 };
 
 const struct {
-  const char *Alias;
-  size_t AliasLength;
-  const char *Name;
-  size_t NameLength;
-
-  StringRef getAlias() const { return StringRef(Alias, AliasLength); }
-  StringRef getName() const { return StringRef(Name, NameLength); }
+  StringRef Alias;
+  StringRef Name;
 } AArch64CPUAliases[] = {
-#define AARCH64_CPU_ALIAS(ALIAS,NAME)                                          \
-  {ALIAS, sizeof(ALIAS) - 1, NAME, sizeof(NAME) - 1},
+#define AARCH64_CPU_ALIAS(ALIAS, NAME) {ALIAS, NAME},
 #include "AArch64TargetParser.def"
 };
 
 const ArchKind ArchKinds[] = {
-#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT) ArchKind::ID,
+#define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) ArchKind::ID,
 #include "AArch64TargetParser.def"
 };
 
 inline ArchKind &operator--(ArchKind &Kind) {
   if ((Kind == ArchKind::INVALID) || (Kind == ArchKind::ARMV8A) ||
       (Kind == ArchKind::ARMV9A) || (Kind == ArchKind::ARMV8R))
     Kind = ArchKind::INVALID;
   else {

llvm/include/llvm/Support/AArch64TargetParser.def

 //===- AARCH64TargetParser.def - AARCH64 target parsing defines ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides defines to build up the AARCH64 target parser's logic.
 //
 //===----------------------------------------------------------------------===//
 
 // NOTE: NO INCLUDE GUARD DESIRED!
 
 #ifndef AARCH64_ARCH
-#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT)
+#define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT)
 #endif
 // NOTE: The order and the grouping of the elements matter to make ArchKind iterable.
 // List is organised as armv8a -> armv8n-a, armv9a -> armv9m-a and armv8-r.
-AARCH64_ARCH("invalid", INVALID, "",
+AARCH64_ARCH("invalid", INVALID, "+",
              AArch64::AEK_NONE)
-AARCH64_ARCH("armv8-a", ARMV8A, "v8a",
+AARCH64_ARCH("armv8-a", ARMV8A, "+v8a",
              (AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD))
-AARCH64_ARCH("armv8.1-a", ARMV8_1A, "v8.1a",
+AARCH64_ARCH("armv8.1-a", ARMV8_1A, "+v8.1a",
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RDM))
-AARCH64_ARCH("armv8.2-a", ARMV8_2A, "v8.2a",
+AARCH64_ARCH("armv8.2-a", ARMV8_2A, "+v8.2a",
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM))
-AARCH64_ARCH("armv8.3-a", ARMV8_3A, "v8.3a",
+AARCH64_ARCH("armv8.3-a", ARMV8_3A, "+v8.3a",
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC))
-AARCH64_ARCH("armv8.4-a", ARMV8_4A, "v8.4a",
+AARCH64_ARCH("armv8.4-a", ARMV8_4A, "+v8.4a",
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD))
-AARCH64_ARCH("armv8.5-a", ARMV8_5A, "v8.5a",
+AARCH64_ARCH("armv8.5-a", ARMV8_5A, "+v8.5a",
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD))
-AARCH64_ARCH("armv8.6-a", ARMV8_6A, "v8.6a",
+AARCH64_ARCH("armv8.6-a", ARMV8_6A, "+v8.6a",
              (AArch64::AEK_CRC  | AArch64::AEK_FP   |
               AArch64::AEK_SIMD | AArch64::AEK_RAS  | AArch64::AEK_LSE     |
               AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16    |
               AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM))
-AARCH64_ARCH("armv8.7-a", ARMV8_7A, "v8.7a",
+AARCH64_ARCH("armv8.7-a", ARMV8_7A, "+v8.7a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
               AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
-AARCH64_ARCH("armv8.8-a", ARMV8_8A, "v8.8a",
+AARCH64_ARCH("armv8.8-a", ARMV8_8A, "+v8.8a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
               AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
-AARCH64_ARCH("armv8.9-a", ARMV8_9A, "v8.9a",
+AARCH64_ARCH("armv8.9-a", ARMV8_9A, "+v8.9a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
               AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
-AARCH64_ARCH("armv9-a",   ARMV9A, "v9a",
+AARCH64_ARCH("armv9-a",   ARMV9A, "+v9a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_SVE2))
-AARCH64_ARCH("armv9.1-a", ARMV9_1A, "v9.1a",
+AARCH64_ARCH("armv9.1-a", ARMV9_1A, "+v9.1a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
-AARCH64_ARCH("armv9.2-a", ARMV9_2A, "v9.2a",
+AARCH64_ARCH("armv9.2-a", ARMV9_2A, "+v9.2a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
-AARCH64_ARCH("armv9.3-a", ARMV9_3A, "v9.3a",
+AARCH64_ARCH("armv9.3-a", ARMV9_3A, "+v9.3a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
-AARCH64_ARCH("armv9.4-a", ARMV9_4A, "v9.4a",
+AARCH64_ARCH("armv9.4-a", ARMV9_4A, "+v9.4a",
              (AArch64::AEK_CRC | AArch64::AEK_FP |
               AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
               AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
               AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2))
 // For v8-R, we do not enable crypto and align with GCC that enables a more
 // minimal set of optional architecture extensions.
-AARCH64_ARCH("armv8-r", ARMV8R, "v8r",
+AARCH64_ARCH("armv8-r", ARMV8R, "+v8r",
              (AArch64::AEK_CRC     | AArch64::AEK_RDM  | AArch64::AEK_SSBS |
               AArch64::AEK_DOTPROD | AArch64::AEK_FP   | AArch64::AEK_SIMD |
               AArch64::AEK_FP16    | AArch64::AEK_FP16FML | AArch64::AEK_RAS |
               AArch64::AEK_RCPC    | AArch64::AEK_SB))
 #undef AARCH64_ARCH
 
 #ifndef AARCH64_ARCH_EXT_NAME
 #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
 #endif
 // FIXME: This would be nicer were it tablegen
-AARCH64_ARCH_EXT_NAME("invalid",      AArch64::AEK_INVALID,     nullptr,         nullptr)
-AARCH64_ARCH_EXT_NAME("none",         AArch64::AEK_NONE,        nullptr,         nullptr)
+AARCH64_ARCH_EXT_NAME("invalid",      AArch64::AEK_INVALID,     {},                  {})
+AARCH64_ARCH_EXT_NAME("none",         AArch64::AEK_NONE,        {},                  {})
 AARCH64_ARCH_EXT_NAME("crc",          AArch64::AEK_CRC,         "+crc",          "-crc")
 AARCH64_ARCH_EXT_NAME("lse",          AArch64::AEK_LSE,         "+lse",          "-lse")
 AARCH64_ARCH_EXT_NAME("rdm",          AArch64::AEK_RDM,         "+rdm",          "-rdm")
 AARCH64_ARCH_EXT_NAME("crypto",       AArch64::AEK_CRYPTO,      "+crypto",       "-crypto")
 AARCH64_ARCH_EXT_NAME("sm4",          AArch64::AEK_SM4,         "+sm4",          "-sm4")
 AARCH64_ARCH_EXT_NAME("sha3",         AArch64::AEK_SHA3,        "+sha3",         "-sha3")
 AARCH64_ARCH_EXT_NAME("sha2",         AArch64::AEK_SHA2,        "+sha2",         "-sha2")
 AARCH64_ARCH_EXT_NAME("aes",          AArch64::AEK_AES,         "+aes",          "-aes")

llvm/include/llvm/Support/ARMTargetParser.h

enum ArchExtKind : uint64_t {
   AEK_OS       =    1ULL << 59,
   AEK_IWMMXT   =    1ULL << 60,
   AEK_IWMMXT2  =    1ULL << 61,
   AEK_MAVERICK =    1ULL << 62,
   AEK_XSCALE   =    1ULL << 63,
 };
 
 // List of Arch Extension names.
-// FIXME: TableGen this.
 struct ExtName {
-  const char *NameCStr;
-  size_t NameLength;
+  StringRef Name;
   uint64_t ID;
-  const char *Feature;
-  const char *NegFeature;
-
-  StringRef getName() const { return StringRef(NameCStr, NameLength); }
+  StringRef Feature;
+  StringRef NegFeature;
 };
 
 const ExtName ARCHExtNames[] = {
 #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                       \
-  {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE},
+  {NAME, ID, FEATURE, NEGFEATURE},
 #include "ARMTargetParser.def"
 };
 
 // List of HWDiv names (use getHWDivSynonym) and which architectural
 // features they correspond to (use getHWDivFeatures).
-// FIXME: TableGen this.
 const struct {
-  const char *NameCStr;
-  size_t NameLength;
+  StringRef Name;
   uint64_t ID;
-
-  StringRef getName() const { return StringRef(NameCStr, NameLength); }
 } HWDivNames[] = {
-#define ARM_HW_DIV_NAME(NAME, ID) {NAME, sizeof(NAME) - 1, ID},
+#define ARM_HW_DIV_NAME(NAME, ID) {NAME, ID},
 #include "ARMTargetParser.def"
 };
 
 // Arch names.
 enum class ArchKind {
-#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
+#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU,        \
+                 ARCH_BASE_EXT)                                                \
+  ID,
 #include "ARMTargetParser.def"
 };
 
 // List of CPU names and their arches.
 // The same CPU can have multiple arches and can be default on multiple arches.
 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
 // When this becomes table-generated, we'd probably need two tables.
-// FIXME: TableGen this.
 struct CpuNames {
-  const char *NameCStr;
-  size_t NameLength;
+  StringRef Name;
   ArchKind ArchID;
   bool Default; // is $Name the default CPU for $ArchID ?
   uint64_t DefaultExtensions;
-
-  StringRef getName() const { return StringRef(NameCStr, NameLength); }
 };
 
 const CpuNames CPUNames[] = {
 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           \
-  {NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
+  {NAME, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
 #include "ARMTargetParser.def"
 };
 
 // FPU names.
 enum FPUKind {
 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
 #include "ARMTargetParser.def"
   FK_LAST
enum class NeonSupportLevel {
   Crypto    ///< Neon with Crypto
 };
 
 // v6/v7/v8 Profile
 enum class ProfileKind { INVALID = 0, A, R, M };
 
 // List of canonical FPU names (use getFPUSynonym) and which architectural
 // features they correspond to (use getFPUFeatures).
-// FIXME: TableGen this.
 // The entries must appear in the order listed in ARM::FPUKind for correct
 // indexing
 struct FPUName {
-  const char *NameCStr;
-  size_t NameLength;
+  StringRef Name;
   FPUKind ID;
   FPUVersion FPUVer;
   NeonSupportLevel NeonSupport;
   FPURestriction Restriction;
-
-  StringRef getName() const { return StringRef(NameCStr, NameLength); }
 };
 
 static const FPUName FPUNames[] = {
 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)                \
-  {NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
+  {NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
 #include "llvm/Support/ARMTargetParser.def"
 };
 
 // List of canonical arch names (use getArchSynonym).
 // This table also provides the build attribute fields for CPU arch
 // and Arch ID, according to the Addenda to the ARM ABI, chapters
 // 2.4 and 2.3.5.2 respectively.
 // FIXME: SubArch values were simplified to fit into the expectations
 // of the triples and are not conforming with their official names.
 // Check to see if the expectation should be changed.
-// FIXME: TableGen this.
 struct ArchNames {
-  const char *NameCStr;
-  size_t NameLength;
-  const char *CPUAttrCStr;
-  size_t CPUAttrLength;
-  const char *SubArchCStr;
-  size_t SubArchLength;
+  StringRef Name;
+  StringRef CPUAttr; // CPU class in build attributes.
+  StringRef ArchFeature;
   unsigned DefaultFPU;
   uint64_t ArchBaseExtensions;
   ArchKind ID;
   ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
 
-  StringRef getName() const { return StringRef(NameCStr, NameLength); }
-
-  // CPU class in build attributes.
-  StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
-
-  // Sub-Arch name.
-  StringRef getSubArch() const {
-    return getArchFeature().substr(1, SubArchLength);
-  }
-
-  // Arch Feature name.
-  StringRef getArchFeature() const {
-    return StringRef(SubArchCStr, SubArchLength);
-  }
+  // Return ArchFeature without the leading "+".
+  StringRef getSubArch() const { return ArchFeature.substr(1); }
 };
 
 static const ArchNames ARMArchNames[] = {
-#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU,            \
+#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU,        \
                  ARCH_BASE_EXT)                                                \
-  {NAME,         sizeof(NAME) - 1,                                             \
-   CPU_ATTR,     sizeof(CPU_ATTR) - 1,                                         \
-   "+" SUB_ARCH, sizeof(SUB_ARCH),                                             \
-   ARCH_FPU,     ARCH_BASE_EXT,                                                \
-   ArchKind::ID, ARCH_ATTR},
+  {NAME,          CPU_ATTR,     ARCH_FEATURE, ARCH_FPU,                        \
+   ARCH_BASE_EXT, ArchKind::ID, ARCH_ATTR},
 #include "llvm/Support/ARMTargetParser.def"
 };
 
 inline ArchKind &operator--(ArchKind &Kind) {
   assert((Kind >= ArchKind::ARMV8A && Kind <= ArchKind::ARMV9_3A) &&
          "We only expect operator-- to be called with ARMV8/V9");
   if (Kind == ArchKind::INVALID || Kind == ArchKind::ARMV8A ||
       Kind == ArchKind::ARMV8_1A || Kind == ArchKind::ARMV9A ||

llvm/include/llvm/Support/ARMTargetParser.def

 ARM_FPU("neon-vfpv4", FK_NEON_VFPV4, FPUVersion::VFPV4, NeonSupportLevel::Neon, FPURestriction::None)
 ARM_FPU("neon-fp-armv8", FK_NEON_FP_ARMV8, FPUVersion::VFPV5, NeonSupportLevel::Neon, FPURestriction::None)
 ARM_FPU("crypto-neon-fp-armv8", FK_CRYPTO_NEON_FP_ARMV8, FPUVersion::VFPV5, NeonSupportLevel::Crypto,
         FPURestriction::None)
 ARM_FPU("softvfp", FK_SOFTVFP, FPUVersion::NONE, NeonSupportLevel::None, FPURestriction::None)
 #undef ARM_FPU
 
 #ifndef ARM_ARCH
-#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT)
+#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT)
 #endif
-ARM_ARCH("invalid", INVALID, "", "",
+ARM_ARCH("invalid", INVALID, "", "+",
           ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv4", ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4,
+ARM_ARCH("armv4", ARMV4, "4", "+v4", ARMBuildAttrs::CPUArch::v4,
           FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv4t", ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T,
+ARM_ARCH("armv4t", ARMV4T, "4T", "+v4t", ARMBuildAttrs::CPUArch::v4T,
           FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv5t", ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T,
+ARM_ARCH("armv5t", ARMV5T, "5T", "+v5", ARMBuildAttrs::CPUArch::v5T,
           FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv5te", ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE,
+ARM_ARCH("armv5te", ARMV5TE, "5TE", "+v5e", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, ARM::AEK_DSP)
-ARM_ARCH("armv5tej", ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ,
+ARM_ARCH("armv5tej", ARMV5TEJ, "5TEJ", "+v5e", ARMBuildAttrs::CPUArch::v5TEJ,
           FK_NONE, ARM::AEK_DSP)
-ARM_ARCH("armv6", ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6,
+ARM_ARCH("armv6", ARMV6, "6", "+v6", ARMBuildAttrs::CPUArch::v6,
           FK_VFPV2, ARM::AEK_DSP)
-ARM_ARCH("armv6k", ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K,
+ARM_ARCH("armv6k", ARMV6K, "6K", "+v6k", ARMBuildAttrs::CPUArch::v6K,
           FK_VFPV2, ARM::AEK_DSP)
-ARM_ARCH("armv6t2", ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2,
+ARM_ARCH("armv6t2", ARMV6T2, "6T2", "+v6t2", ARMBuildAttrs::CPUArch::v6T2,
           FK_NONE, ARM::AEK_DSP)
-ARM_ARCH("armv6kz", ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ,
+ARM_ARCH("armv6kz", ARMV6KZ, "6KZ", "+v6kz", ARMBuildAttrs::CPUArch::v6KZ,
           FK_VFPV2, (ARM::AEK_SEC | ARM::AEK_DSP))
-ARM_ARCH("armv6-m", ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M,
+ARM_ARCH("armv6-m", ARMV6M, "6-M", "+v6m", ARMBuildAttrs::CPUArch::v6_M,
           FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv7-a", ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7,
+ARM_ARCH("armv7-a", ARMV7A, "7-A", "+v7", ARMBuildAttrs::CPUArch::v7,
           FK_NEON, ARM::AEK_DSP)
-ARM_ARCH("armv7ve", ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7,
+ARM_ARCH("armv7ve", ARMV7VE, "7VE", "+v7ve", ARMBuildAttrs::CPUArch::v7,
           FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
           ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
-ARM_ARCH("armv7-r", ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7,
+ARM_ARCH("armv7-r", ARMV7R, "7-R", "+v7r", ARMBuildAttrs::CPUArch::v7,
           FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
-ARM_ARCH("armv7-m", ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7,
+ARM_ARCH("armv7-m", ARMV7M, "7-M", "+v7m", ARMBuildAttrs::CPUArch::v7,
           FK_NONE, ARM::AEK_HWDIVTHUMB)
-ARM_ARCH("armv7e-m", ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M,
+ARM_ARCH("armv7e-m", ARMV7EM, "7E-M", "+v7em", ARMBuildAttrs::CPUArch::v7E_M,
           FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
-ARM_ARCH("armv8-a", ARMV8A, "8-A", "v8a", ARMBuildAttrs::CPUArch::v8_A,
+ARM_ARCH("armv8-a", ARMV8A, "8-A", "+v8a", ARMBuildAttrs::CPUArch::v8_A,
          FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC))
-ARM_ARCH("armv8.1-a", ARMV8_1A, "8.1-A", "v8.1a",
+ARM_ARCH("armv8.1-a", ARMV8_1A, "8.1-A", "+v8.1a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC))
-ARM_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a",
+ARM_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "+v8.2a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
-ARM_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "v8.3a",
+ARM_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "+v8.3a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
-ARM_ARCH("armv8.4-a", ARMV8_4A, "8.4-A", "v8.4a",
+ARM_ARCH("armv8.4-a", ARMV8_4A, "8.4-A", "+v8.4a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD))
-ARM_ARCH("armv8.5-a", ARMV8_5A, "8.5-A", "v8.5a",
+ARM_ARCH("armv8.5-a", ARMV8_5A, "8.5-A", "+v8.5a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD))
-ARM_ARCH("armv8.6-a", ARMV8_6A, "8.6-A", "v8.6a",
+ARM_ARCH("armv8.6-a", ARMV8_6A, "8.6-A", "+v8.6a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC        | ARM::AEK_MP   | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP  | ARM::AEK_CRC  | ARM::AEK_RAS |
           ARM::AEK_DOTPROD    | ARM::AEK_BF16 | ARM::AEK_I8MM))
-ARM_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a",
+ARM_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "+v8.7a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC        | ARM::AEK_MP   | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP  | ARM::AEK_CRC  | ARM::AEK_RAS |
           ARM::AEK_DOTPROD    | ARM::AEK_BF16 | ARM::AEK_I8MM))
-ARM_ARCH("armv8.8-a", ARMV8_8A, "8.8-A", "v8.8a",
+ARM_ARCH("armv8.8-a", ARMV8_8A, "8.8-A", "+v8.8a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_SHA2 | ARM::AEK_AES |
           ARM::AEK_I8MM))
-ARM_ARCH("armv8.9-a", ARMV8_9A, "8.9-A", "v8.9a",
+ARM_ARCH("armv8.9-a", ARMV8_9A, "8.9-A", "+v8.9a",
          ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_SHA2 | ARM::AEK_AES |
           ARM::AEK_I8MM))
-ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a",
+ARM_ARCH("armv9-a", ARMV9A, "9-A", "+v9a",
          ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD))
-ARM_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "v9.1a",
+ARM_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "+v9.1a",
          ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
-ARM_ARCH("armv9.2-a", ARMV9_2A, "9.2-A", "v9.2a",
+ARM_ARCH("armv9.2-a", ARMV9_2A, "9.2-A", "+v9.2a",
          ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
-ARM_ARCH("armv9.3-a", ARMV9_3A, "9.3-A", "v9.3a",
+ARM_ARCH("armv9.3-a", ARMV9_3A, "9.3-A", "+v9.3a",
          ARMBuildAttrs::CPUArch::v9_A, FK_CRYPTO_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
-ARM_ARCH("armv9.4-a", ARMV9_4A, "9.4-A", "v9.4a",
+ARM_ARCH("armv9.4-a", ARMV9_4A, "9.4-A", "+v9.4a",
          ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8,
          (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
           ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
           ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
-ARM_ARCH("armv8-r", ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R,
+ARM_ARCH("armv8-r", ARMV8R, "8-R", "+v8r", ARMBuildAttrs::CPUArch::v8_R,
           FK_NEON_FP_ARMV8,
           (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
            ARM::AEK_DSP | ARM::AEK_CRC))
-ARM_ARCH("armv8-m.base", ARMV8MBaseline, "8-M.Baseline", "v8m.base",
+ARM_ARCH("armv8-m.base", ARMV8MBaseline, "8-M.Baseline", "+v8m.base",
           ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIVTHUMB)
-ARM_ARCH("armv8-m.main", ARMV8MMainline, "8-M.Mainline", "v8m.main",
+ARM_ARCH("armv8-m.main", ARMV8MMainline, "8-M.Mainline", "+v8m.main",
           ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIVTHUMB)
-ARM_ARCH("armv8.1-m.main", ARMV8_1MMainline, "8.1-M.Mainline", "v8.1m.main",
+ARM_ARCH("armv8.1-m.main", ARMV8_1MMainline, "8.1-M.Mainline", "+v8.1m.main",
           ARMBuildAttrs::CPUArch::v8_1_M_Main, FK_FP_ARMV8_FULLFP16_SP_D16, ARM::AEK_HWDIVTHUMB | ARM::AEK_RAS | ARM::AEK_LOB)
 // Non-standard Arch names.
-ARM_ARCH("iwmmxt", IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
+ARM_ARCH("iwmmxt", IWMMXT, "iwmmxt", "+", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("iwmmxt2", IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE,
+ARM_ARCH("iwmmxt2", IWMMXT2, "iwmmxt2", "+", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("xscale", XSCALE, "xscale", "v5e", ARMBuildAttrs::CPUArch::v5TE,
+ARM_ARCH("xscale", XSCALE, "xscale", "+v5e", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv7s", ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7,
+ARM_ARCH("armv7s", ARMV7S, "7-S", "+v7s", ARMBuildAttrs::CPUArch::v7,
           FK_NEON_VFPV4, ARM::AEK_DSP)
-ARM_ARCH("armv7k", ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7,
+ARM_ARCH("armv7k", ARMV7K, "7-K", "+v7k", ARMBuildAttrs::CPUArch::v7,
           FK_NONE, ARM::AEK_DSP)
 #undef ARM_ARCH
 
 #ifndef ARM_ARCH_EXT_NAME
 #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
 #endif
-// FIXME: This would be nicer were it tablegen
-ARM_ARCH_EXT_NAME("invalid",  ARM::AEK_INVALID,  nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("none",     ARM::AEK_NONE,     nullptr,  nullptr)
+ARM_ARCH_EXT_NAME("invalid",  ARM::AEK_INVALID,  {},  {})
+ARM_ARCH_EXT_NAME("none",     ARM::AEK_NONE,     {},  {})
 ARM_ARCH_EXT_NAME("crc",      ARM::AEK_CRC,      "+crc",   "-crc")
 ARM_ARCH_EXT_NAME("crypto",   ARM::AEK_CRYPTO,   "+crypto","-crypto")
 ARM_ARCH_EXT_NAME("sha2",     ARM::AEK_SHA2,     "+sha2",  "-sha2")
 ARM_ARCH_EXT_NAME("aes",      ARM::AEK_AES,      "+aes",   "-aes")
 ARM_ARCH_EXT_NAME("dotprod",  ARM::AEK_DOTPROD,  "+dotprod","-dotprod")
 ARM_ARCH_EXT_NAME("dsp",      ARM::AEK_DSP,      "+dsp",   "-dsp")
-ARM_ARCH_EXT_NAME("fp",       ARM::AEK_FP,       nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("fp.dp",    ARM::AEK_FP_DP,    nullptr,  nullptr)
+ARM_ARCH_EXT_NAME("fp",       ARM::AEK_FP,       {},  {})
+ARM_ARCH_EXT_NAME("fp.dp",    ARM::AEK_FP_DP,    {},  {})
 ARM_ARCH_EXT_NAME("mve",     (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
 ARM_ARCH_EXT_NAME("mve.fp",  (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP), "+mve.fp", "-mve.fp")
-ARM_ARCH_EXT_NAME("idiv",     (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), nullptr, nullptr)
-ARM_ARCH_EXT_NAME("mp",       ARM::AEK_MP,       nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("simd",     ARM::AEK_SIMD,     nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("sec",      ARM::AEK_SEC,      nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("virt",     ARM::AEK_VIRT,     nullptr,  nullptr)
+ARM_ARCH_EXT_NAME("idiv",     (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
+ARM_ARCH_EXT_NAME("mp",       ARM::AEK_MP,       {},  {})
+ARM_ARCH_EXT_NAME("simd",     ARM::AEK_SIMD,     {},  {})
+ARM_ARCH_EXT_NAME("sec",      ARM::AEK_SEC,      {},  {})
+ARM_ARCH_EXT_NAME("virt",     ARM::AEK_VIRT,     {},  {})
 ARM_ARCH_EXT_NAME("fp16",     ARM::AEK_FP16,     "+fullfp16",  "-fullfp16")
 ARM_ARCH_EXT_NAME("ras",      ARM::AEK_RAS,      "+ras", "-ras")
-ARM_ARCH_EXT_NAME("os",       ARM::AEK_OS,       nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("iwmmxt",   ARM::AEK_IWMMXT,   nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("iwmmxt2",  ARM::AEK_IWMMXT2,  nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr,  nullptr)
-ARM_ARCH_EXT_NAME("xscale",   ARM::AEK_XSCALE,   nullptr,  nullptr)
+ARM_ARCH_EXT_NAME("os",       ARM::AEK_OS,       {},  {})
+ARM_ARCH_EXT_NAME("iwmmxt",   ARM::AEK_IWMMXT,   {},  {})
+ARM_ARCH_EXT_NAME("iwmmxt2",  ARM::AEK_IWMMXT2,  {},  {})
+ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, {},  {})
+ARM_ARCH_EXT_NAME("xscale",   ARM::AEK_XSCALE,   {},  {})
 ARM_ARCH_EXT_NAME("fp16fml",  ARM::AEK_FP16FML,  "+fp16fml", "-fp16fml")
 ARM_ARCH_EXT_NAME("bf16",     ARM::AEK_BF16,     "+bf16",    "-bf16")
 ARM_ARCH_EXT_NAME("sb",       ARM::AEK_SB,       "+sb",      "-sb")
 ARM_ARCH_EXT_NAME("i8mm",     ARM::AEK_I8MM,     "+i8mm",    "-i8mm")
 ARM_ARCH_EXT_NAME("lob",      ARM::AEK_LOB,      "+lob",   "-lob")
 ARM_ARCH_EXT_NAME("cdecp0",   ARM::AEK_CDECP0,   "+cdecp0",  "-cdecp0")
 ARM_ARCH_EXT_NAME("cdecp1",   ARM::AEK_CDECP1,   "+cdecp1",  "-cdecp1")
 ARM_ARCH_EXT_NAME("cdecp2",   ARM::AEK_CDECP2,   "+cdecp2",  "-cdecp2")

llvm/lib/Support/AArch64TargetParser.cpp

AArch64::ArchKind AArch64::getCPUArchKind(StringRef CPU) {
   return StringSwitch<AArch64::ArchKind>(CPU)
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)       \
   .Case(NAME, ArchKind::ID)
 #include "../../include/llvm/Support/AArch64TargetParser.def"
   .Default(ArchKind::INVALID);
 }
 
 AArch64::ArchKind AArch64::getSubArchArchKind(StringRef SubArch) {
-  return StringSwitch<AArch64::ArchKind>(SubArch)
-#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT)                        \
-  .Case(SUB_ARCH, ArchKind::ID)
-#include "../../include/llvm/Support/AArch64TargetParser.def"
-  .Default(ArchKind::INVALID);
+  for (const auto &A : AArch64ARCHNames)
+    if (A.getSubArch() == SubArch)
+      return A.ID;
+  return ArchKind::INVALID;
 }
 
 bool AArch64::getExtensionFeatures(uint64_t Extensions,
                                    std::vector<StringRef> &Features) {
   if (Extensions == AArch64::AEK_INVALID)
     return false;
 
 #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                   \

 #include "../../include/llvm/Support/AArch64TargetParser.def"
   .Default(CPU);
 }
 
 bool AArch64::getArchFeatures(AArch64::ArchKind AK,
                               std::vector<StringRef> &Features) {
   if (AK == ArchKind::INVALID)
     return false;
-  Features.push_back(
-      AArch64ARCHNames[static_cast<unsigned>(AK)].getArchFeature());
+  Features.push_back(AArch64ARCHNames[static_cast<unsigned>(AK)].ArchFeature);
   return true;
 }
 
 StringRef AArch64::getArchName(AArch64::ArchKind AK) {
-  return AArch64ARCHNames[static_cast<unsigned>(AK)].getName();
+  return AArch64ARCHNames[static_cast<unsigned>(AK)].Name;
 }
 
 StringRef AArch64::getSubArch(AArch64::ArchKind AK) {
   return AArch64ARCHNames[static_cast<unsigned>(AK)].getSubArch();
 }
 
 StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
   if (ArchExt.startswith("no")) {
     StringRef ArchExtBase(ArchExt.substr(2));
     for (const auto &AE : AArch64ARCHExtNames) {
-      if (AE.NegFeature && ArchExtBase == AE.getName())
-        return StringRef(AE.NegFeature);
+      if (!AE.NegFeature.empty() && ArchExtBase == AE.Name)
+        return AE.NegFeature;
     }
   }
 
   for (const auto &AE : AArch64ARCHExtNames)
-    if (AE.Feature && ArchExt == AE.getName())
-      return StringRef(AE.Feature);
+    if (!AE.Feature.empty() && ArchExt == AE.Name)
+      return AE.Feature;
   return StringRef();
 }
 
 AArch64::ArchKind AArch64::convertV9toV8(AArch64::ArchKind AK) {
   if (AK == AArch64::ArchKind::INVALID)
     return AK;
   if (AK < AArch64::ArchKind::ARMV9A)
     return AK;
   if (AK >= AArch64::ArchKind::ARMV8R)
     return AArch64::ArchKind::INVALID;
   unsigned AK_v8 = static_cast<unsigned>(AArch64::ArchKind::ARMV8_5A);
   AK_v8 += static_cast<unsigned>(AK) -
            static_cast<unsigned>(AArch64::ArchKind::ARMV9A);
   return static_cast<AArch64::ArchKind>(AK_v8);
 }
 
 void AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
   for (const auto &Arch : AArch64CPUNames) {
     if (Arch.ArchID != ArchKind::INVALID)
-      Values.push_back(Arch.getName());
+      Values.push_back(Arch.Name);
   }
 
   for (const auto &Alias: AArch64CPUAliases)
-    Values.push_back(Alias.getAlias());
+    Values.push_back(Alias.Alias);
 }
 
 bool AArch64::isX18ReservedByDefault(const Triple &TT) {
   return TT.isAndroid() || TT.isOSDarwin() || TT.isOSFuchsia() ||
          TT.isOSWindows();
 }
 
 // Allows partial match, ex. "v8a" matches "armv8a".
 AArch64::ArchKind AArch64::parseArch(StringRef Arch) {
   Arch = llvm::ARM::getCanonicalArchName(Arch);
   if (checkArchVersion(Arch) < 8)
     return ArchKind::INVALID;
 
   StringRef Syn = llvm::ARM::getArchSynonym(Arch);
   for (const auto &A : AArch64ARCHNames) {
-    if (A.getName().endswith(Syn))
+    if (A.Name.endswith(Syn))
       return A.ID;
   }
   return ArchKind::INVALID;
 }
 
 AArch64::ArchExtKind AArch64::parseArchExt(StringRef ArchExt) {
   for (const auto &A : AArch64ARCHExtNames) {
-    if (ArchExt == A.getName())
+    if (ArchExt == A.Name)
       return static_cast<ArchExtKind>(A.ID);
   }
   return AArch64::AEK_INVALID;
 }
 
 AArch64::ArchKind AArch64::parseCPUArch(StringRef CPU) {
   // Resolve aliases first.
   for (const auto &Alias : AArch64CPUAliases) {
-    if (CPU == Alias.getAlias()) {
-      CPU = Alias.getName();
+    if (CPU == Alias.Alias) {
+      CPU = Alias.Name;
       break;
     }
   }
   // Then find the CPU name.
   for (const auto &C : AArch64CPUNames)
-    if (CPU == C.getName())
+    if (CPU == C.Name)
       return C.ArchID;
 
   return ArchKind::INVALID;
 }

llvm/lib/Support/ARMTargetParser.cpp

return StringSwitch<StringRef>(HWDiv)
       .Default(HWDiv);
 }
 
 // Allows partial match, ex. "v7a" matches "armv7a".
 ARM::ArchKind ARM::parseArch(StringRef Arch) {
   Arch = getCanonicalArchName(Arch);
   StringRef Syn = getArchSynonym(Arch);
   for (const auto &A : ARMArchNames) {
-    if (A.getName().endswith(Syn))
+    if (A.Name.endswith(Syn))
       return A.ID;
   }
   return ArchKind::INVALID;
 }
 
 // Version number (ex. v7 = 7).
 unsigned ARM::parseArchVersion(StringRef Arch) {
   Arch = getCanonicalArchName(Arch);
bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
   }
 
   return true;
 }
 
 unsigned ARM::parseFPU(StringRef FPU) {
   StringRef Syn = getFPUSynonym(FPU);
   for (const auto &F : FPUNames) {
-    if (Syn == F.getName())
+    if (Syn == F.Name)
       return F.ID;
   }
   return FK_INVALID;
 }
 
 ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) {
   if (FPUKind >= FK_LAST)
     return NeonSupportLevel::None;
return StringSwitch<StringRef>(FPU)
       // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
       .Case("neon-vfpv3", "neon")
       .Default(FPU);
 }
 
 StringRef ARM::getFPUName(unsigned FPUKind) {
   if (FPUKind >= FK_LAST)
     return StringRef();
-  return FPUNames[FPUKind].getName();
+  return FPUNames[FPUKind].Name;
 }
 
 ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) {
   if (FPUKind >= FK_LAST)
     return FPUVersion::NONE;
   return FPUNames[FPUKind].FPUVer;
 }
 

 
 bool ARM::getExtensionFeatures(uint64_t Extensions,
                                std::vector<StringRef> &Features) {
 
   if (Extensions == AEK_INVALID)
     return false;
 
   for (const auto &AE : ARCHExtNames) {
-    if ((Extensions & AE.ID) == AE.ID && AE.Feature)
+    if ((Extensions & AE.ID) == AE.ID && !AE.Feature.empty())
       Features.push_back(AE.Feature);
-    else if (AE.NegFeature)
+    else if (!AE.NegFeature.empty())
       Features.push_back(AE.NegFeature);
   }
 
   return getHWDivFeatures(Extensions, Features);
 }
 
 StringRef ARM::getArchName(ARM::ArchKind AK) {
-  return ARMArchNames[static_cast<unsigned>(AK)].getName();
+  return ARMArchNames[static_cast<unsigned>(AK)].Name;
 }
 
 StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
-  return ARMArchNames[static_cast<unsigned>(AK)].getCPUAttr();
+  return ARMArchNames[static_cast<unsigned>(AK)].CPUAttr;
 }
 
 StringRef ARM::getSubArch(ARM::ArchKind AK) {
   return ARMArchNames[static_cast<unsigned>(AK)].getSubArch();
 }
 
 unsigned ARM::getArchAttr(ARM::ArchKind AK) {
   return ARMArchNames[static_cast<unsigned>(AK)].ArchAttr;
 }
 
 StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
   for (const auto &AE : ARCHExtNames) {
     if (ArchExtKind == AE.ID)
-      return AE.getName();
+      return AE.Name;
   }
   return StringRef();
 }
 
 static bool stripNegationPrefix(StringRef &Name) {
   if (Name.startswith("no")) {
     Name = Name.substr(2);
     return true;
   }
   return false;
 }
 
 StringRef ARM::getArchExtFeature(StringRef ArchExt) {
   bool Negated = stripNegationPrefix(ArchExt);
   for (const auto &AE : ARCHExtNames) {
-    if (AE.Feature && ArchExt == AE.getName())
+    if (!AE.Feature.empty() && ArchExt == AE.Name)
       return StringRef(Negated ? AE.NegFeature : AE.Feature);
   }
 
   return StringRef();
 }
 
 static unsigned findDoublePrecisionFPU(unsigned InputFPUKind) {
   const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
bool ARM::appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK,
   const bool Negated = stripNegationPrefix(ArchExt);
   uint64_t ID = parseArchExt(ArchExt);
 
   if (ID == AEK_INVALID)
     return false;
 
   for (const auto &AE : ARCHExtNames) {
     if (Negated) {
-      if ((AE.ID & ID) == ID && AE.NegFeature)
+      if ((AE.ID & ID) == ID && !AE.NegFeature.empty())
         Features.push_back(AE.NegFeature);
     } else {
-      if ((AE.ID & ID) == AE.ID && AE.Feature)
+      if ((AE.ID & ID) == AE.ID && !AE.Feature.empty())
         Features.push_back(AE.Feature);
     }
   }
 
   if (CPU == "")
     CPU = "generic";
 
   if (ArchExt == "fp" || ArchExt == "fp.dp") {

 StringRef ARM::getDefaultCPU(StringRef Arch) {
   ArchKind AK = parseArch(Arch);
   if (AK == ArchKind::INVALID)
     return StringRef();
 
   // Look for multiple AKs to find the default for pair AK+Name.
   for (const auto &CPU : CPUNames) {
     if (CPU.ArchID == AK && CPU.Default)
-      return CPU.getName();
+      return CPU.Name;
   }
 
   // If we can't find a default then target the architecture instead
   return "generic";
 }
 
 uint64_t ARM::parseHWDiv(StringRef HWDiv) {
   StringRef Syn = getHWDivSynonym(HWDiv);
   for (const auto &D : HWDivNames) {
-    if (Syn == D.getName())
+    if (Syn == D.Name)
       return D.ID;
   }
   return AEK_INVALID;
 }
 
 uint64_t ARM::parseArchExt(StringRef ArchExt) {
   for (const auto &A : ARCHExtNames) {
-    if (ArchExt == A.getName())
+    if (ArchExt == A.Name)
       return A.ID;
   }
   return AEK_INVALID;
 }
 
 ARM::ArchKind ARM::parseCPUArch(StringRef CPU) {
   for (const auto &C : CPUNames) {
-    if (CPU == C.getName())
+    if (CPU == C.Name)
       return C.ArchID;
   }
   return ArchKind::INVALID;
 }
 
 void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
   for (const auto &Arch : CPUNames) {
     if (Arch.ArchID != ArchKind::INVALID)
-      Values.push_back(Arch.getName());
+      Values.push_back(Arch.Name);
   }
 }
 
 StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
   StringRef ArchName =
       CPU.empty() ? TT.getArchName() : getArchName(parseCPUArch(CPU));
 
   if (TT.isOSBinFormatMachO()) {

llvm/unittests/Support/TargetParserTest.cpp

else
       EXPECT_NE(ARM::FPURestriction::None, ARM::getFPURestriction(FK));
   }
 }
 
 TEST(TargetParserTest, ARMExtensionFeatures) {
   std::map<uint64_t, std::vector<StringRef>> Extensions;
 
   for (auto &Ext : ARM::ARCHExtNames) {
-    if (Ext.Feature && Ext.NegFeature)
-      Extensions[Ext.ID] = { StringRef(Ext.Feature),
-                             StringRef(Ext.NegFeature) };
+    if (!Ext.Feature.empty() && !Ext.NegFeature.empty())
+      Extensions[Ext.ID] = {Ext.Feature, Ext.NegFeature};
   }
 
   Extensions[ARM::AEK_HWDIVARM]   = { "+hwdiv-arm", "-hwdiv-arm" };
   Extensions[ARM::AEK_HWDIVTHUMB] = { "+hwdiv",     "-hwdiv" };
 
   std::vector<StringRef> Features;
 
   EXPECT_FALSE(ARM::getExtensionFeatures(ARM::AEK_INVALID, Features));