Enable roundeven.

[Leonc]

Summary

Add support for roundeven and implement appropriate tests.

[arsenm]

Can you also take care of globalisel here?

[arsenm]

llvm/test/CodeGen/AMDGPU/roundeven.ll

17

Does v_trunc_f32 ever raise FP exceptions?

[Leonc]

In D137954#3925014, @arsenm wrote:

Can you also take care of globalisel here?

From what I can tell globalisel already has support.

[Leonc]

llvm/test/CodeGen/AMDGPU/roundeven.ll

17

I assume we have tests for that in a different file, but if not I could make a new task to add them.

[arsenm]

In D137954#3925019, @Leonc wrote:

In D137954#3925014, @arsenm wrote:

Can you also take care of globalisel here?

From what I can tell globalisel already has support.

Tests should be unified then

llvm/test/CodeGen/AMDGPU/roundeven.ll

17

That's not testable here, it's an isa behavior question

[Leonc]

• Address comments.

[Leonc]

@arsenm how's this? The tests are unified, but it seems a little misleading to have ISel and GlobalISel tests in the same directory.

[foad]

In D137954#3926910, @Leonc wrote:

@arsenm how's this? The tests are unified, but it seems a little misleading to have ISel and GlobalISel tests in the same directory.

Move it out of GlobalISel/. There are plenty of unified sdag/gisel tests in the parent directory already.

[foad]

llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll

1

SDAG- is commonly used for this. ISEL_ is a bit vague.

[Leonc]

• Move test file.

[Leonc]

• Address comments.

[Leonc]

Couldn't reproduce pre-merge warning locally.
All tests have passed successfully.

[Leonc]

• Rebase.

[Leonc]

The warning is from clang-format. It wants to make 86 changes over hundreds of lines unrelated to this patch.

clang-format-changes.diff64 KBDownload

[foad]

In D137954#3933743, @Leonc wrote:

The warning is from clang-format. It wants to make 86 changes over hundreds of lines unrelated to this patch.

clang-format-changes.diff64 KBDownload

No, it only wants correct formatting for the lines you actually changed in your patch. If you "install" git clang-format, by making sure llvm-project/clang/tools/clang-format/git-clang-format is on your $PATH, then you can run: git clang-format @^. This is what the Harbormaster build does.

[Leonc]

• Changes required by clang-format.

[Leonc]

In D137954#3936521, @foad wrote:

In D137954#3933743, @Leonc wrote:

The warning is from clang-format. It wants to make 86 changes over hundreds of lines unrelated to this patch.

clang-format-changes.diff64 KBDownload

No, it only wants correct formatting for the lines you actually changed in your patch. If you "install" git clang-format, by making sure llvm-project/clang/tools/clang-format/git-clang-format is on your $PATH, then you can run: git clang-format @^. This is what the Harbormaster build does.

Thanks. I've applied the changes now.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1195

I'm perpetually confused by the variety of rounding functions.

llvm.rint => round to nearest integer, in current rounding mode (which is assumed to be round nearest even), which is implied by being non-constrained
llvm.nearbyint => same as llvm.rint, except no FP exceptions. FP exceptions aren't supported with non-constrained intrinsics, so this distinction is pointless

llvm.round -> round, away from 0
llvm.roundeven -> round halfway nearest 0

so I think this isn't the same as round, but is supposed to be the same as llvm.rint (which we have 3 different names for)

[Leonc]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1195

I thought llvm.roundeven is supposed to always round to nearest even regardless of the rounding mode. Does our implementation of llvm.rint ignore the rounding mode?

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1195

Yes. This is all legacy cruft from when people were imaging possible solutions to supporting strictfp in the distant future without an actual design in mind. The non-strict, regular floating point intrinsics all assume RTE rounding with no fp exceptions.

This cruft is bothering me; as a follow up, can you prepare a patch to deprecate the old intrinsics and auto-upgrade them so we're left with one?

[Leonc]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1195

Can do. I agree it's needlessly confusing.

[craig.topper]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1195

For targets that don't optimize them to inline sequences, wouldn't that cause calls library calls to mutate into a different library call? Functionally it would be correct in the default environment, but might be surprising.

Depending on which one you choose as canonical it could cause link errors. I don't think you could choose roundeven as canonical since its not in older libm.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1195

Part of the problem is thinking the intrinsics have anything to do with libm. You can lower the intrinsic to a different name for the libcall

[craig.topper]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1195

I didn't say we couldn't. Merely saying that someone will find that surprising and probably file a bug.

[Leonc]

• Change rounding method to match GlobalISel.

[Leonc]

FRINT only handles f64 so I'm updating the patch to handle the remaining scalar types.

[arsenm]

LGTM

llvm/test/CodeGen/AMDGPU/roundeven.ll

9

Should use explicit -global-isel=0

[Leonc]

• Add support for vector types.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

309–312

Commented out vector types? The vectors should be and have defaulted to expand

[Leonc]

• Revert vector code in favour of auto-vectorisation.

[Leonc]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

309–312

Apologies these were debug comments. I've removed them now.

[Leonc]

• Address comments.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2194–2196

Subtarget is already available as a member here, don't need to go through the function

2198–2204

You don't need a generation check here, you can just lower to whatever opcode you choose to consolidate on and let the handling of that one take care of the subtarget specific legality considerations which should already work

[Leonc]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2198–2204

LowerFRINT handles lowering when f64 isn't supported. Based on GlobalISel's implementation that's any generation before gfx7.

[Leonc]

• Address comments.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2198–2204

You do not need to directly call LowerFRINT. You can just unconditionally produce the frint, and let that be legalized. What you have here is repeating the legality condition in a second place

[Leonc]

• Clang formatting.

[Leonc]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2198–2204

I tried that and it crashed.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2198–2204

Define "crashed". Something else is wrong, you can rely on re-legalization of new nodes

[Leonc]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2198–2204

I didn't save the log unfortunately. I'll see if I can reproduce it.

[Leonc]

• Address comments.

[Leonc]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2198–2204

You were right. I must have done something wrong the first time.

[bcahoon]

llvm/test/CodeGen/AMDGPU/roundeven.ll

479

It looks like arguments are converted from f32->f16->f32. Is that correct/efficient?

[arsenm]

llvm/test/CodeGen/AMDGPU/roundeven.ll

479

This is the broken ABI the DAG wants to give targets without legal f16. It’s a problem and ends up with different behavior for GlobalISel

[Leonc]

llvm/test/CodeGen/AMDGPU/roundeven.ll

479

Is there a workaround?

[arsenm]

llvm/test/CodeGen/AMDGPU/roundeven.ll

479

use an i16 argument and bitcast to half in the IR. Should also figure out how to fix the DAG from promoting to float

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS,
                      MVT::f32, Legal);
 
   setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom);
 
   setOperationAction({ISD::FLOG, ISD::FLOG10, ISD::FEXP}, MVT::f32, Custom);
 
   setOperationAction(ISD::FNEARBYINT, {MVT::f16, MVT::f32, MVT::f64}, Custom);
 
+  setOperationAction(ISD::FROUNDEVEN, {MVT::f16, MVT::f32, MVT::f64}, Custom);
+
   setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom);
 
   // Expand to fneg + fadd.
   setOperationAction(ISD::FSUB, MVT::f64, Expand);
 
   setOperationAction(ISD::CONCAT_VECTORS,
                      {MVT::v3i32, MVT::v3f32, MVT::v4i32, MVT::v4f32,
                       MVT::v5i32, MVT::v5f32, MVT::v6i32, MVT::v6f32,
                       MVT::v7i32, MVT::v7f32, MVT::v8i32, MVT::v8f32},
                      Custom);
   setOperationAction(
       ISD::EXTRACT_SUBVECTOR,
SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
   case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
   case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
   case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
   case ISD::FREM: return LowerFREM(Op, DAG);
   case ISD::FCEIL: return LowerFCEIL(Op, DAG);
   case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
   case ISD::FRINT: return LowerFRINT(Op, DAG);
   case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
+  case ISD::FROUNDEVEN: return LowerFROUND(Op, DAG);
   case ISD::FROUND: return LowerFROUND(Op, DAG);
   case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
   case ISD::FLOG:
     return LowerFLOG(Op, DAG, numbers::ln2f);
   case ISD::FLOG10:
     return LowerFLOG(Op, DAG, numbers::ln2f / numbers::ln10f);
   case ISD::FEXP:
     return lowerFEXP(Op, DAG);
   case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);

 
 // XXX - May require not supporting f32 denormals?
 
 // Don't handle v2f16. The extra instructions to scalarize and repack around the
 // compare and vselect end up producing worse code than scalarizing the whole
 // operation.
 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
   SDLoc SL(Op);
   SDValue X = Op.getOperand(0);
   EVT VT = Op.getValueType();
 
   SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
 
   // TODO: Should this propagate fast-math-flags?
 
   SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
 
   SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
 
   const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
   const SDValue One = DAG.getConstantFP(1.0, SL, VT);
   const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
 
   SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
 
   EVT SetCCVT =
       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);

llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
-
-define float @v_roundeven_f32(float %x) {
-; GFX6-LABEL: v_roundeven_f32:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_f32:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_f32:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_f32:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call float @llvm.roundeven.f32(float %x)
-  ret float %roundeven
-}
-
-define <2 x float> @v_roundeven_v2f32(<2 x float> %x) {
-; GFX6-LABEL: v_roundeven_v2f32:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_v2f32:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_v2f32:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX8-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_v2f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX9-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_v2f32:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %x)
-  ret <2 x float> %roundeven
-}
-
-define <3 x float> @v_roundeven_v3f32(<3 x float> %x) {
-; GFX6-LABEL: v_roundeven_v3f32:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX6-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_v3f32:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX7-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_v3f32:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX8-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX8-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_v3f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX9-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX9-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_v3f32:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call <3 x float> @llvm.roundeven.v3f32(<3 x float> %x)
-  ret <3 x float> %roundeven
-}
-
-define <4 x float> @v_roundeven_v4f32(<4 x float> %x) {
-; GFX6-LABEL: v_roundeven_v4f32:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX6-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX6-NEXT:    v_rndne_f32_e32 v3, v3
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_v4f32:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX7-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX7-NEXT:    v_rndne_f32_e32 v3, v3
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_v4f32:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX8-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX8-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX8-NEXT:    v_rndne_f32_e32 v3, v3
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_v4f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX9-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX9-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX9-NEXT:    v_rndne_f32_e32 v3, v3
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_v4f32:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v3, v3
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %x)
-  ret <4 x float> %roundeven
-}
-
-define half @v_roundeven_f16(half %x) {
-; GFX6-LABEL: v_roundeven_f16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_f16:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_f16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_f16:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_f16:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call half @llvm.roundeven.f16(half %x)
-  ret half %roundeven
-}
-
-define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {
-; GFX6-LABEL: v_roundeven_v2f16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_v2f16:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_v2f16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f16_e32 v1, v0
-; GFX8-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT:    v_mov_b32_e32 v2, 16
-; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_v2f16:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f16_e32 v1, v0
-; GFX9-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT:    v_pack_b32_f16 v0, v1, v0
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_roundeven_v2f16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_rndne_f16_e32 v1, v0
-; GFX10-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT:    v_pack_b32_f16 v0, v1, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_roundeven_v2f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x)
-  ret <2 x half> %roundeven
-}
-
-define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {
-; GFX6-LABEL: v_roundeven_v2f16_fneg:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v0
-; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v0
-; GFX6-NEXT:    v_rndne_f32_e32 v0, v1
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT:    v_rndne_f32_e32 v1, v2
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_v2f16_fneg:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX7-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX7-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v0
-; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v0
-; GFX7-NEXT:    v_rndne_f32_e32 v0, v1
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT:    v_rndne_f32_e32 v1, v2
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_v2f16_fneg:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX8-NEXT:    v_rndne_f16_e32 v1, v0
-; GFX8-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT:    v_mov_b32_e32 v2, 16
-; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_v2f16_fneg:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX9-NEXT:    v_rndne_f16_e32 v1, v0
-; GFX9-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT:    v_pack_b32_f16 v0, v1, v0
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_roundeven_v2f16_fneg:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX10-NEXT:    v_rndne_f16_e32 v1, v0
-; GFX10-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT:    v_pack_b32_f16 v0, v1, v0
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_roundeven_v2f16_fneg:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %x.fneg = fneg <2 x half> %x
-  %roundeven = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x.fneg)
-  ret <2 x half> %roundeven
-}
-
-define <4 x half> @v_roundeven_v4f16(<4 x half> %x) {
-; GFX6-LABEL: v_roundeven_v4f16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX6-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX6-NEXT:    v_rndne_f32_e32 v3, v3
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_v4f16:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
-; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX7-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX7-NEXT:    v_rndne_f32_e32 v3, v3
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_v4f16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f16_e32 v2, v0
-; GFX8-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT:    v_rndne_f16_e32 v3, v1
-; GFX8-NEXT:    v_rndne_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT:    v_mov_b32_e32 v4, 16
-; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_v4f16:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f16_e32 v2, v0
-; GFX9-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT:    v_rndne_f16_e32 v3, v1
-; GFX9-NEXT:    v_rndne_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX9-NEXT:    v_pack_b32_f16 v1, v3, v1
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: v_roundeven_v4f16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_rndne_f16_e32 v2, v0
-; GFX10-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT:    v_rndne_f16_e32 v3, v1
-; GFX10-NEXT:    v_rndne_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX10-NEXT:    v_pack_b32_f16 v1, v3, v1
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_roundeven_v4f16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
-; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
-; GFX11-NEXT:    v_rndne_f16_e32 v2, v2
-; GFX11-NEXT:    v_rndne_f16_e32 v3, v3
-; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v2
-; GFX11-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %x)
-  ret <4 x half> %roundeven
-}
-
-
-define float @v_roundeven_f32_fabs(float %x) {
-; GFX6-LABEL: v_roundeven_f32_fabs:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_rndne_f32_e64 v0, |v0|
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_f32_fabs:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f32_e64 v0, |v0|
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_f32_fabs:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f32_e64 v0, |v0|
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_f32_fabs:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f32_e64 v0, |v0|
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_f32_fabs:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f32_e64 v0, |v0|
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %fabs.x = call float @llvm.fabs.f32(float %x)
-  %roundeven = call float @llvm.roundeven.f32(float %fabs.x)
-  ret float %roundeven
-}
-
-define amdgpu_ps float @s_roundeven_f32(float inreg %x) {
-; GFX6-LABEL: s_roundeven_f32:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    v_rndne_f32_e32 v0, s0
-; GFX6-NEXT:    ; return to shader part epilog
-;
-; GFX7-LABEL: s_roundeven_f32:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    v_rndne_f32_e32 v0, s0
-; GFX7-NEXT:    ; return to shader part epilog
-;
-; GFX8-LABEL: s_roundeven_f32:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    v_rndne_f32_e32 v0, s0
-; GFX8-NEXT:    ; return to shader part epilog
-;
-; GFX9-LABEL: s_roundeven_f32:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_rndne_f32_e32 v0, s0
-; GFX9-NEXT:    ; return to shader part epilog
-;
-; GFX10PLUS-LABEL: s_roundeven_f32:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, s0
-; GFX10PLUS-NEXT:    ; return to shader part epilog
-  %roundeven = call float @llvm.roundeven.f32(float %x)
-  ret float %roundeven
-}
-
-define float @v_roundeven_f32_fneg(float %x) {
-; GFX6-LABEL: v_roundeven_f32_fneg:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_rndne_f32_e64 v0, -v0
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_f32_fneg:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f32_e64 v0, -v0
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_f32_fneg:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f32_e64 v0, -v0
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_f32_fneg:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f32_e64 v0, -v0
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_f32_fneg:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f32_e64 v0, -v0
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %neg.x = fneg float %x
-  %roundeven = call float @llvm.roundeven.f32(float %neg.x)
-  ret float %roundeven
-}
-
-define double @v_roundeven_f64(double %x) {
-; GFX6-LABEL: v_roundeven_f64:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_and_b32_e32 v3, 0x80000000, v1
-; GFX6-NEXT:    v_mov_b32_e32 v2, 0
-; GFX6-NEXT:    v_or_b32_e32 v3, 0x43300000, v3
-; GFX6-NEXT:    v_add_f64 v[4:5], v[0:1], v[2:3]
-; GFX6-NEXT:    s_mov_b32 s4, -1
-; GFX6-NEXT:    s_mov_b32 s5, 0x432fffff
-; GFX6-NEXT:    v_add_f64 v[2:3], v[4:5], -v[2:3]
-; GFX6-NEXT:    v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_f64:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_f64:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_f64:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_f64:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call double @llvm.roundeven.f64(double %x)
-  ret double %roundeven
-}
-
-define double @v_roundeven_f64_fneg(double %x) {
-; GFX6-LABEL: v_roundeven_f64_fneg:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_xor_b32_e32 v6, 0x80000000, v1
-; GFX6-NEXT:    v_and_b32_e32 v3, 0x80000000, v6
-; GFX6-NEXT:    v_mov_b32_e32 v2, 0
-; GFX6-NEXT:    v_or_b32_e32 v3, 0x43300000, v3
-; GFX6-NEXT:    v_add_f64 v[4:5], -v[0:1], v[2:3]
-; GFX6-NEXT:    s_mov_b32 s4, -1
-; GFX6-NEXT:    s_mov_b32 s5, 0x432fffff
-; GFX6-NEXT:    v_add_f64 v[2:3], v[4:5], -v[2:3]
-; GFX6-NEXT:    v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v3, v6, vcc
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_f64_fneg:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f64_e64 v[0:1], -v[0:1]
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_f64_fneg:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f64_e64 v[0:1], -v[0:1]
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_f64_fneg:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f64_e64 v[0:1], -v[0:1]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_f64_fneg:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f64_e64 v[0:1], -v[0:1]
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %neg.x = fneg double %x
-  %roundeven = call double @llvm.roundeven.f64(double %neg.x)
-  ret double %roundeven
-}
-
-define <2 x double> @v_roundeven_v2f64(<2 x double> %x) {
-; GFX6-LABEL: v_roundeven_v2f64:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_or_b32_e32 v5, 0x43300000, v5
-; GFX6-NEXT:    v_add_f64 v[6:7], v[0:1], v[4:5]
-; GFX6-NEXT:    s_mov_b32 s4, -1
-; GFX6-NEXT:    s_mov_b32 s5, 0x432fffff
-; GFX6-NEXT:    v_add_f64 v[5:6], v[6:7], -v[4:5]
-; GFX6-NEXT:    v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
-; GFX6-NEXT:    v_and_b32_e32 v5, 0x80000000, v3
-; GFX6-NEXT:    v_or_b32_e32 v5, 0x43300000, v5
-; GFX6-NEXT:    v_add_f64 v[7:8], v[2:3], v[4:5]
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; GFX6-NEXT:    v_add_f64 v[4:5], v[7:8], -v[4:5]
-; GFX6-NEXT:    v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[4:5]
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX6-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX7-LABEL: v_roundeven_v2f64:
-; GFX7:       ; %bb.0:
-; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX7-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX7-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_roundeven_v2f64:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX8-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_roundeven_v2f64:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX9-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10PLUS-LABEL: v_roundeven_v2f64:
-; GFX10PLUS:       ; %bb.0:
-; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10PLUS-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
-; GFX10PLUS-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
-  %roundeven = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %x)
-  ret <2 x double> %roundeven
-}
-
-declare half @llvm.roundeven.f16(half) #0
-declare <2 x half> @llvm.roundeven.v2f16(<2 x half>) #0
-declare <4 x half> @llvm.roundeven.v4f16(<4 x half>) #0
-
-declare float @llvm.roundeven.f32(float) #0
-declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) #0
-declare <3 x float> @llvm.roundeven.v3f32(<3 x float>) #0
-declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #0
-
-declare double @llvm.roundeven.f64(double) #0
-declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) #0
-
-declare half @llvm.fabs.f16(half) #0
-declare float @llvm.fabs.f32(float) #0
-
-attributes #0 = { nounwind readnone speculatable willreturn }

llvm/test/CodeGen/AMDGPU/roundeven.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=ISEL_GFX6 %s
+; RUN: llc -march=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefix=ISEL_GFX7 %s
+; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=ISEL_GFX8 %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=ISEL_GFX9 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=ISEL_GFX10PLUS,ISEL_GFX10 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=ISEL_GFX10PLUS,ISEL_GFX11 %s
+
+define float @v_roundeven_f32(float %x) {
+; GFX6-LABEL: v_roundeven_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_f32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_f32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_f32:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v2, v0
+; ISEL_GFX6-NEXT:    v_bfi_b32 v1, s4, 1.0, v0
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v0, v0, v2
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_f32:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v2, v0
+; ISEL_GFX7-NEXT:    v_bfi_b32 v1, s4, 1.0, v0
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v0, v0, v2
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_f32:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v2, v0
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, 1.0, v0
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v0, v0, v2
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_f32:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v2, v0
+; ISEL_GFX9-NEXT:    v_bfi_b32 v1, s4, 1.0, v0
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v0, v0, v2
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10PLUS-LABEL: v_roundeven_f32:
+; ISEL_GFX10PLUS:       ; %bb.0:
+; ISEL_GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10PLUS-NEXT:    v_trunc_f32_e32 v1, v0
+; ISEL_GFX10PLUS-NEXT:    v_sub_f32_e32 v2, v0, v1
+; ISEL_GFX10PLUS-NEXT:    v_bfi_b32 v0, 0x7fffffff, 1.0, v0
+; ISEL_GFX10PLUS-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v2|, 0.5
+; ISEL_GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; ISEL_GFX10PLUS-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call float @llvm.roundeven.f32(float %x)
+  ret float %roundeven
+}
+
+define <2 x float> @v_roundeven_v2f32(<2 x float> %x) {
+; GFX6-LABEL: v_roundeven_v2f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_v2f32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_v2f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX8-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_v2f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX9-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_v2f32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_v2f32:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v3, v0
+; ISEL_GFX6-NEXT:    v_bfi_b32 v2, s4, 1.0, v0
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v0, v0, v3
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v3, v0
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v3, v1
+; ISEL_GFX6-NEXT:    v_bfi_b32 v2, s4, 1.0, v1
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v1, v1, v3
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v1, v3, v1
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_v2f32:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v3, v0
+; ISEL_GFX7-NEXT:    v_bfi_b32 v2, s4, 1.0, v0
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v0, v0, v3
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v3, v0
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v3, v1
+; ISEL_GFX7-NEXT:    v_bfi_b32 v2, s4, 1.0, v1
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v1, v1, v3
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v1, v3, v1
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_v2f32:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v3, v0
+; ISEL_GFX8-NEXT:    v_bfi_b32 v2, s4, 1.0, v0
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v0, v0, v3
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v0, v3, v0
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v3, v1
+; ISEL_GFX8-NEXT:    v_bfi_b32 v2, s4, 1.0, v1
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v1, v1, v3
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v1, v3, v1
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_v2f32:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v3, v0
+; ISEL_GFX9-NEXT:    v_bfi_b32 v2, s4, 1.0, v0
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v0, v0, v3
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v0, v3, v0
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v3, v1
+; ISEL_GFX9-NEXT:    v_bfi_b32 v2, s4, 1.0, v1
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v1, v1, v3
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v1, v3, v1
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_v2f32:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v2, v0
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v3, v1
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v4, v0, v2
+; ISEL_GFX10-NEXT:    v_bfi_b32 v0, 0x7fffffff, 1.0, v0
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v5, v1, v3
+; ISEL_GFX10-NEXT:    v_bfi_b32 v1, 0x7fffffff, 1.0, v1
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v4|, 0.5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v5|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v1, v3, v1
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_v2f32:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v2, v0
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v3, v1
+; ISEL_GFX11-NEXT:    v_dual_sub_f32 v4, v0, v2 :: v_dual_sub_f32 v5, v1, v3
+; ISEL_GFX11-NEXT:    v_bfi_b32 v0, 0x7fffffff, 1.0, v0
+; ISEL_GFX11-NEXT:    v_bfi_b32 v1, 0x7fffffff, 1.0, v1
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v4|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v5|, 0.5
+; ISEL_GFX11-NEXT:    v_dual_cndmask_b32 v1, 0, v1 :: v_dual_add_f32 v0, v2, v0
+; ISEL_GFX11-NEXT:    v_add_f32_e32 v1, v3, v1
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %x)
+  ret <2 x float> %roundeven
+}
+
+define <3 x float> @v_roundeven_v3f32(<3 x float> %x) {
+; GFX6-LABEL: v_roundeven_v3f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX6-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_v3f32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX7-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_v3f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX8-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX8-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_v3f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX9-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX9-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_v3f32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_v3f32:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v4, v0
+; ISEL_GFX6-NEXT:    v_bfi_b32 v3, s4, 1.0, v0
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v0, v0, v4
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v4, v0
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v4, v1
+; ISEL_GFX6-NEXT:    v_bfi_b32 v3, s4, 1.0, v1
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v1, v1, v4
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v1, v4, v1
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v4, v2
+; ISEL_GFX6-NEXT:    v_bfi_b32 v3, s4, 1.0, v2
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v2, v2, v4
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v3, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v2, v4, v2
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_v3f32:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v4, v0
+; ISEL_GFX7-NEXT:    v_bfi_b32 v3, s4, 1.0, v0
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v0, v0, v4
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v4, v0
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v4, v1
+; ISEL_GFX7-NEXT:    v_bfi_b32 v3, s4, 1.0, v1
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v1, v1, v4
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v1, v4, v1
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v4, v2
+; ISEL_GFX7-NEXT:    v_bfi_b32 v3, s4, 1.0, v2
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v2, v2, v4
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v2, 0, v3, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v2, v4, v2
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_v3f32:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v4, v0
+; ISEL_GFX8-NEXT:    v_bfi_b32 v3, s4, 1.0, v0
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v0, v0, v4
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v0, v4, v0
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v4, v1
+; ISEL_GFX8-NEXT:    v_bfi_b32 v3, s4, 1.0, v1
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v1, v1, v4
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v1, v4, v1
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v4, v2
+; ISEL_GFX8-NEXT:    v_bfi_b32 v3, s4, 1.0, v2
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v2, v2, v4
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v3, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v2, v4, v2
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_v3f32:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v4, v0
+; ISEL_GFX9-NEXT:    v_bfi_b32 v3, s4, 1.0, v0
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v0, v0, v4
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v0, v4, v0
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v4, v1
+; ISEL_GFX9-NEXT:    v_bfi_b32 v3, s4, 1.0, v1
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v1, v1, v4
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v1, v4, v1
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v4, v2
+; ISEL_GFX9-NEXT:    v_bfi_b32 v3, s4, 1.0, v2
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v2, v2, v4
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v3, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v2, v4, v2
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_v3f32:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v3, v0
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v4, v1
+; ISEL_GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, 1.0, v0
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v6, v2
+; ISEL_GFX10-NEXT:    v_bfi_b32 v7, 0x7fffffff, 1.0, v1
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v0, v0, v3
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v1, v1, v4
+; ISEL_GFX10-NEXT:    v_bfi_b32 v8, 0x7fffffff, 1.0, v2
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v2, v2, v6
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v5, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v0, v3, v0
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v7, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v2|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v1, v4, v1
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v2, 0, v8, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v2, v6, v2
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_v3f32:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v3, v0
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v4, v1
+; ISEL_GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, 1.0, v0
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v6, v2
+; ISEL_GFX11-NEXT:    v_bfi_b32 v7, 0x7fffffff, 1.0, v1
+; ISEL_GFX11-NEXT:    v_dual_sub_f32 v0, v0, v3 :: v_dual_sub_f32 v1, v1, v4
+; ISEL_GFX11-NEXT:    v_bfi_b32 v8, 0x7fffffff, 1.0, v2
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v5, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX11-NEXT:    v_sub_f32_e32 v2, v2, v6
+; ISEL_GFX11-NEXT:    v_dual_add_f32 v0, v3, v0 :: v_dual_cndmask_b32 v1, 0, v7
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v2|, 0.5
+; ISEL_GFX11-NEXT:    v_dual_add_f32 v1, v4, v1 :: v_dual_cndmask_b32 v2, 0, v8
+; ISEL_GFX11-NEXT:    v_add_f32_e32 v2, v6, v2
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call <3 x float> @llvm.roundeven.v3f32(<3 x float> %x)
+  ret <3 x float> %roundeven
+}
+
+define <4 x float> @v_roundeven_v4f32(<4 x float> %x) {
+; GFX6-LABEL: v_roundeven_v4f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX6-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX6-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_v4f32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX7-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX7-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_v4f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX8-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX8-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX8-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_v4f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX9-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX9-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX9-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_v4f32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_v4f32:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v5, v0
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, 1.0, v0
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v0, v0, v5
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v5, v0
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v5, v1
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, 1.0, v1
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v1, v1, v5
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v1, v5, v1
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v5, v2
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, 1.0, v2
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v2, v2, v5
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v2, v5, v2
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v5, v3
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, 1.0, v3
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v3, v3, v5
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v3, v5, v3
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_v4f32:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v5, v0
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, 1.0, v0
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v0, v0, v5
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v5, v0
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v5, v1
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, 1.0, v1
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v1, v1, v5
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v1, v5, v1
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v5, v2
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, 1.0, v2
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v2, v2, v5
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v2, v5, v2
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v5, v3
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, 1.0, v3
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v3, v3, v5
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v3, v5, v3
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_v4f32:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v5, v0
+; ISEL_GFX8-NEXT:    v_bfi_b32 v4, s4, 1.0, v0
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v0, v0, v5
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v0, v5, v0
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v5, v1
+; ISEL_GFX8-NEXT:    v_bfi_b32 v4, s4, 1.0, v1
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v1, v1, v5
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v1, v5, v1
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v5, v2
+; ISEL_GFX8-NEXT:    v_bfi_b32 v4, s4, 1.0, v2
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v2, v2, v5
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v2, v5, v2
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v5, v3
+; ISEL_GFX8-NEXT:    v_bfi_b32 v4, s4, 1.0, v3
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v3, v3, v5
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v3, v5, v3
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_v4f32:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v5, v0
+; ISEL_GFX9-NEXT:    v_bfi_b32 v4, s4, 1.0, v0
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v0, v0, v5
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v0, v5, v0
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v5, v1
+; ISEL_GFX9-NEXT:    v_bfi_b32 v4, s4, 1.0, v1
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v1, v1, v5
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v1, v5, v1
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v5, v2
+; ISEL_GFX9-NEXT:    v_bfi_b32 v4, s4, 1.0, v2
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v2, v2, v5
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v2, v5, v2
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v5, v3
+; ISEL_GFX9-NEXT:    v_bfi_b32 v4, s4, 1.0, v3
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v3, v3, v5
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v3, v5, v3
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_v4f32:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v4, v0
+; ISEL_GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, 1.0, v0
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v7, v1
+; ISEL_GFX10-NEXT:    v_bfi_b32 v6, 0x7fffffff, 1.0, v1
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v8, v2
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v0, v0, v4
+; ISEL_GFX10-NEXT:    v_bfi_b32 v9, 0x7fffffff, 1.0, v2
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v1, v1, v7
+; ISEL_GFX10-NEXT:    v_trunc_f32_e32 v10, v3
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v2, v2, v8
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v5, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, 1.0, v3
+; ISEL_GFX10-NEXT:    v_sub_f32_e32 v3, v3, v10
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v0, v4, v0
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v6, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v2|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v1, v7, v1
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v2, 0, v9, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v3|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v2, v8, v2
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v3, v10, v3
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_v4f32:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v4, v0
+; ISEL_GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, 1.0, v0
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v7, v1
+; ISEL_GFX11-NEXT:    v_bfi_b32 v6, 0x7fffffff, 1.0, v1
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v8, v2
+; ISEL_GFX11-NEXT:    v_sub_f32_e32 v0, v0, v4
+; ISEL_GFX11-NEXT:    v_bfi_b32 v9, 0x7fffffff, 1.0, v2
+; ISEL_GFX11-NEXT:    v_sub_f32_e32 v1, v1, v7
+; ISEL_GFX11-NEXT:    v_trunc_f32_e32 v10, v3
+; ISEL_GFX11-NEXT:    v_sub_f32_e32 v2, v2, v8
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v5, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, 1.0, v3
+; ISEL_GFX11-NEXT:    v_sub_f32_e32 v3, v3, v10
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v1, 0, v6, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v2|, 0.5
+; ISEL_GFX11-NEXT:    v_add_f32_e32 v0, v4, v0
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v2, 0, v9, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v3|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc_lo
+; ISEL_GFX11-NEXT:    v_add_f32_e32 v3, v10, v3
+; ISEL_GFX11-NEXT:    v_dual_add_f32 v1, v7, v1 :: v_dual_add_f32 v2, v8, v2
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %x)
+  ret <4 x float> %roundeven
+}
+
+define half @v_roundeven_f16(half %x) {
+; GFX6-LABEL: v_roundeven_f16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_f16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_f16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_f16:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_f16:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v2, v0
+; ISEL_GFX6-NEXT:    v_bfi_b32 v1, s4, 1.0, v0
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v0, v0, v2
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_f16:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v2, v0
+; ISEL_GFX7-NEXT:    v_bfi_b32 v1, s4, 1.0, v0
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v0, v0, v2
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_f16:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    s_movk_i32 s4, 0x7fff
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v1, 0x3c00
+; ISEL_GFX8-NEXT:    v_trunc_f16_e32 v2, v0
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, v1, v0
+; ISEL_GFX8-NEXT:    v_sub_f16_e32 v0, v0, v2
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_add_f16_e32 v0, v2, v0
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_f16:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    s_movk_i32 s4, 0x7fff
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v1, 0x3c00
+; ISEL_GFX9-NEXT:    v_trunc_f16_e32 v2, v0
+; ISEL_GFX9-NEXT:    v_bfi_b32 v1, s4, v1, v0
+; ISEL_GFX9-NEXT:    v_sub_f16_e32 v0, v0, v2
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v0|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v0, v2, v0
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_f16:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f16_e32 v1, v0
+; ISEL_GFX10-NEXT:    s_movk_i32 s4, 0x3c00
+; ISEL_GFX10-NEXT:    v_sub_f16_e32 v2, v0, v1
+; ISEL_GFX10-NEXT:    v_bfi_b32 v0, 0x7fff, s4, v0
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v2|, 0.5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v0, v1, v0
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_f16:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f16_e32 v1, v0
+; ISEL_GFX11-NEXT:    s_movk_i32 s0, 0x3c00
+; ISEL_GFX11-NEXT:    v_sub_f16_e32 v2, v0, v1
+; ISEL_GFX11-NEXT:    v_bfi_b32 v0, 0x7fff, s0, v0
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v2|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v0, v1, v0
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call half @llvm.roundeven.f16(half %x)
+  ret half %roundeven
+}
+
+define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {
+; GFX6-LABEL: v_roundeven_v2f16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_v2f16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_v2f16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f16_e32 v1, v0
+; GFX8-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT:    v_mov_b32_e32 v2, 16
+; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_v2f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f16_e32 v1, v0
+; GFX9-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_pack_b32_f16 v0, v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_roundeven_v2f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_rndne_f16_e32 v1, v0
+; GFX10-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_pack_b32_f16 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_roundeven_v2f16:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
+; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_v2f16:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v3, v0
+; ISEL_GFX6-NEXT:    v_bfi_b32 v2, s4, 1.0, v0
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v0, v0, v3
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v3, v0
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v3, v1
+; ISEL_GFX6-NEXT:    v_bfi_b32 v2, s4, 1.0, v1
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v1, v1, v3
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v1, v3, v1
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_v2f16:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v3, v0
+; ISEL_GFX7-NEXT:    v_bfi_b32 v2, s4, 1.0, v0
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v0, v0, v3
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v3, v0
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v3, v1
+; ISEL_GFX7-NEXT:    v_bfi_b32 v2, s4, 1.0, v1
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v1, v1, v3
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v1, v3, v1
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_v2f16:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; ISEL_GFX8-NEXT:    v_trunc_f16_e32 v2, v1
+; ISEL_GFX8-NEXT:    v_sub_f16_e32 v3, v1, v2
+; ISEL_GFX8-NEXT:    s_movk_i32 s4, 0x7fff
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v4, 0x3c00
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, v4, v1
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v3|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_trunc_f16_e32 v3, v0
+; ISEL_GFX8-NEXT:    v_add_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; ISEL_GFX8-NEXT:    v_bfi_b32 v2, s4, v4, v0
+; ISEL_GFX8-NEXT:    v_sub_f16_e32 v0, v0, v3
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
+; ISEL_GFX8-NEXT:    v_add_f16_e32 v0, v3, v0
+; ISEL_GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_v2f16:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    v_trunc_f16_e32 v3, v0
+; ISEL_GFX9-NEXT:    s_movk_i32 s4, 0x7fff
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v1, 0x3c00
+; ISEL_GFX9-NEXT:    v_sub_f16_e32 v4, v0, v3
+; ISEL_GFX9-NEXT:    v_bfi_b32 v2, s4, v1, v0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v4|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; ISEL_GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v2, v3, v2
+; ISEL_GFX9-NEXT:    v_trunc_f16_e32 v3, v0
+; ISEL_GFX9-NEXT:    v_sub_f16_e32 v4, v0, v3
+; ISEL_GFX9-NEXT:    v_bfi_b32 v0, s4, v1, v0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v4|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v0, v3, v0
+; ISEL_GFX9-NEXT:    v_pack_b32_f16 v0, v2, v0
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_v2f16:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; ISEL_GFX10-NEXT:    v_trunc_f16_e32 v2, v0
+; ISEL_GFX10-NEXT:    s_movk_i32 s4, 0x3c00
+; ISEL_GFX10-NEXT:    v_trunc_f16_e32 v3, v1
+; ISEL_GFX10-NEXT:    v_sub_f16_e32 v4, v0, v2
+; ISEL_GFX10-NEXT:    v_bfi_b32 v0, 0x7fff, s4, v0
+; ISEL_GFX10-NEXT:    v_sub_f16_e32 v5, v1, v3
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v4|, 0.5
+; ISEL_GFX10-NEXT:    v_bfi_b32 v1, 0x7fff, s4, v1
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v5|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v0, v2, v0
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v1, v3, v1
+; ISEL_GFX10-NEXT:    v_pack_b32_f16 v0, v0, v1
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_v2f16:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; ISEL_GFX11-NEXT:    v_trunc_f16_e32 v2, v0
+; ISEL_GFX11-NEXT:    s_movk_i32 s0, 0x3c00
+; ISEL_GFX11-NEXT:    v_trunc_f16_e32 v3, v1
+; ISEL_GFX11-NEXT:    v_sub_f16_e32 v4, v0, v2
+; ISEL_GFX11-NEXT:    v_bfi_b32 v0, 0x7fff, s0, v0
+; ISEL_GFX11-NEXT:    v_sub_f16_e32 v5, v1, v3
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v4|, 0.5
+; ISEL_GFX11-NEXT:    v_bfi_b32 v1, 0x7fff, s0, v1
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v5|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v0, v2, v0
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v1, v3, v1
+; ISEL_GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x)
+  ret <2 x half> %roundeven
+}
+
+define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {
+; GFX6-LABEL: v_roundeven_v2f16_fneg:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v0
+; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v0
+; GFX6-NEXT:    v_rndne_f32_e32 v0, v1
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT:    v_rndne_f32_e32 v1, v2
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_v2f16_fneg:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX7-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v0
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v0
+; GFX7-NEXT:    v_rndne_f32_e32 v0, v1
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT:    v_rndne_f32_e32 v1, v2
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_v2f16_fneg:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX8-NEXT:    v_rndne_f16_e32 v1, v0
+; GFX8-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT:    v_mov_b32_e32 v2, 16
+; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_v2f16_fneg:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX9-NEXT:    v_rndne_f16_e32 v1, v0
+; GFX9-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_pack_b32_f16 v0, v1, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_roundeven_v2f16_fneg:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX10-NEXT:    v_rndne_f16_e32 v1, v0
+; GFX10-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_pack_b32_f16 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_roundeven_v2f16_fneg:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
+; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_v2f16_fneg:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; ISEL_GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
+; ISEL_GFX6-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v0
+; ISEL_GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v0
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v0, v1
+; ISEL_GFX6-NEXT:    v_bfi_b32 v3, s4, 1.0, v1
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v1, v1, v0
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v0, v1
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v1, v2
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v3, v2, v1
+; ISEL_GFX6-NEXT:    v_bfi_b32 v2, s4, 1.0, v2
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v1, v1, v2
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_v2f16_fneg:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; ISEL_GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
+; ISEL_GFX7-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v0
+; ISEL_GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v0
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v0, v1
+; ISEL_GFX7-NEXT:    v_bfi_b32 v3, s4, 1.0, v1
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v1, v1, v0
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v0, v1
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v1, v2
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v3, v2, v1
+; ISEL_GFX7-NEXT:    v_bfi_b32 v2, s4, 1.0, v2
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v1, v1, v2
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_v2f16_fneg:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; ISEL_GFX8-NEXT:    v_trunc_f16_e64 v2, -v1
+; ISEL_GFX8-NEXT:    v_sub_f16_e64 v3, -v1, v2
+; ISEL_GFX8-NEXT:    v_xor_b32_e32 v1, 0x8000, v1
+; ISEL_GFX8-NEXT:    s_movk_i32 s4, 0x7fff
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v4, 0x3c00
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, v4, v1
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v3|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_trunc_f16_e64 v3, -v0
+; ISEL_GFX8-NEXT:    v_add_f16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; ISEL_GFX8-NEXT:    v_xor_b32_e32 v2, 0x8000, v0
+; ISEL_GFX8-NEXT:    v_sub_f16_e64 v0, -v0, v3
+; ISEL_GFX8-NEXT:    v_bfi_b32 v2, s4, v4, v2
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
+; ISEL_GFX8-NEXT:    v_add_f16_e32 v0, v3, v0
+; ISEL_GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_v2f16_fneg:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    v_trunc_f16_e64 v3, -v0
+; ISEL_GFX9-NEXT:    v_xor_b32_e32 v1, 0x8000, v0
+; ISEL_GFX9-NEXT:    s_movk_i32 s4, 0x7fff
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v2, 0x3c00
+; ISEL_GFX9-NEXT:    v_sub_f16_e64 v4, -v0, v3
+; ISEL_GFX9-NEXT:    v_bfi_b32 v1, s4, v2, v1
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v4|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v1, v3, v1
+; ISEL_GFX9-NEXT:    v_trunc_f16_e64 v3, -v0
+; ISEL_GFX9-NEXT:    v_sub_f16_e64 v4, -v0, v3
+; ISEL_GFX9-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; ISEL_GFX9-NEXT:    v_bfi_b32 v0, s4, v2, v0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v4|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v0, v3, v0
+; ISEL_GFX9-NEXT:    v_pack_b32_f16 v0, v1, v0
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_v2f16_fneg:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; ISEL_GFX10-NEXT:    v_trunc_f16_e64 v2, -v0
+; ISEL_GFX10-NEXT:    v_xor_b32_e32 v3, 0x8000, v0
+; ISEL_GFX10-NEXT:    s_movk_i32 s4, 0x3c00
+; ISEL_GFX10-NEXT:    v_trunc_f16_e64 v4, -v1
+; ISEL_GFX10-NEXT:    v_sub_f16_e64 v0, -v0, v2
+; ISEL_GFX10-NEXT:    v_xor_b32_e32 v5, 0x8000, v1
+; ISEL_GFX10-NEXT:    v_bfi_b32 v3, 0x7fff, s4, v3
+; ISEL_GFX10-NEXT:    v_sub_f16_e64 v1, -v1, v4
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX10-NEXT:    v_bfi_b32 v5, 0x7fff, s4, v5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v0, v2, v0
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v1, v4, v1
+; ISEL_GFX10-NEXT:    v_pack_b32_f16 v0, v0, v1
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_v2f16_fneg:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; ISEL_GFX11-NEXT:    v_trunc_f16_e64 v2, -v0
+; ISEL_GFX11-NEXT:    v_xor_b32_e32 v3, 0x8000, v0
+; ISEL_GFX11-NEXT:    s_movk_i32 s0, 0x3c00
+; ISEL_GFX11-NEXT:    v_trunc_f16_e64 v4, -v1
+; ISEL_GFX11-NEXT:    v_sub_f16_e64 v0, -v0, v2
+; ISEL_GFX11-NEXT:    v_xor_b32_e32 v5, 0x8000, v1
+; ISEL_GFX11-NEXT:    v_bfi_b32 v3, 0x7fff, s0, v3
+; ISEL_GFX11-NEXT:    v_sub_f16_e64 v1, -v1, v4
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX11-NEXT:    v_bfi_b32 v5, 0x7fff, s0, v5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc_lo
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v0, v2, v0
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v1, v4, v1
+; ISEL_GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %x.fneg = fneg <2 x half> %x
+  %roundeven = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x.fneg)
+  ret <2 x half> %roundeven
+}
+
+define <4 x half> @v_roundeven_v4f16(<4 x half> %x) {
+; GFX6-LABEL: v_roundeven_v4f16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GFX6-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX6-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX6-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX6-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_v4f16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; GFX7-NEXT:    v_rndne_f32_e32 v0, v0
+; GFX7-NEXT:    v_rndne_f32_e32 v1, v1
+; GFX7-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX7-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_v4f16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f16_e32 v2, v0
+; GFX8-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT:    v_rndne_f16_e32 v3, v1
+; GFX8-NEXT:    v_rndne_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT:    v_mov_b32_e32 v4, 16
+; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT:    v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_v4f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f16_e32 v2, v0
+; GFX9-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_rndne_f16_e32 v3, v1
+; GFX9-NEXT:    v_rndne_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX9-NEXT:    v_pack_b32_f16 v1, v3, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_roundeven_v4f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_rndne_f16_e32 v2, v0
+; GFX10-NEXT:    v_rndne_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_rndne_f16_e32 v3, v1
+; GFX10-NEXT:    v_rndne_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX10-NEXT:    v_pack_b32_f16 v1, v3, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_roundeven_v4f16:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-NEXT:    v_rndne_f16_e32 v0, v0
+; GFX11-NEXT:    v_rndne_f16_e32 v1, v1
+; GFX11-NEXT:    v_rndne_f16_e32 v2, v2
+; GFX11-NEXT:    v_rndne_f16_e32 v3, v3
+; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX11-NEXT:    v_pack_b32_f16 v1, v1, v3
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_v4f16:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; ISEL_GFX6-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v5, v0
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, 1.0, v0
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v0, v0, v5
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v5, v0
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v5, v1
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, 1.0, v1
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v1, v1, v5
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v1, v5, v1
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v5, v2
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, 1.0, v2
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v2, v2, v5
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v2, v5, v2
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v5, v3
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, 1.0, v3
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v3, v3, v5
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v3, v5, v3
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_v4f16:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; ISEL_GFX7-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v5, v0
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, 1.0, v0
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v0, v0, v5
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v5, v0
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v5, v1
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, 1.0, v1
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v1, v1, v5
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v1, v5, v1
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v5, v2
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, 1.0, v2
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v2, v2, v5
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v2, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v2, v5, v2
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v5, v3
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, 1.0, v3
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v3, v3, v5
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v3, v5, v3
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_v4f16:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    v_trunc_f16_e32 v4, v1
+; ISEL_GFX8-NEXT:    s_movk_i32 s4, 0x7fff
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v2, 0x3c00
+; ISEL_GFX8-NEXT:    v_sub_f16_e32 v5, v1, v4
+; ISEL_GFX8-NEXT:    v_bfi_b32 v3, s4, v2, v1
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v5|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
+; ISEL_GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; ISEL_GFX8-NEXT:    v_add_f16_e32 v3, v4, v3
+; ISEL_GFX8-NEXT:    v_trunc_f16_e32 v4, v1
+; ISEL_GFX8-NEXT:    v_sub_f16_e32 v5, v1, v4
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, v2, v1
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v5|, 0.5
+; ISEL_GFX8-NEXT:    v_trunc_f16_e32 v5, v0
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_sub_f16_e32 v6, v0, v5
+; ISEL_GFX8-NEXT:    v_add_f16_sdwa v1, v4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; ISEL_GFX8-NEXT:    v_bfi_b32 v4, s4, v2, v0
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v6|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
+; ISEL_GFX8-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; ISEL_GFX8-NEXT:    v_add_f16_e32 v4, v5, v4
+; ISEL_GFX8-NEXT:    v_trunc_f16_e32 v5, v0
+; ISEL_GFX8-NEXT:    v_sub_f16_e32 v6, v0, v5
+; ISEL_GFX8-NEXT:    v_bfi_b32 v0, s4, v2, v0
+; ISEL_GFX8-NEXT:    v_cmp_ge_f16_e64 vcc, |v6|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; ISEL_GFX8-NEXT:    v_add_f16_sdwa v0, v5, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; ISEL_GFX8-NEXT:    v_or_b32_e32 v0, v4, v0
+; ISEL_GFX8-NEXT:    v_or_b32_e32 v1, v3, v1
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_v4f16:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    v_trunc_f16_e32 v4, v1
+; ISEL_GFX9-NEXT:    s_movk_i32 s4, 0x7fff
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v2, 0x3c00
+; ISEL_GFX9-NEXT:    v_sub_f16_e32 v5, v1, v4
+; ISEL_GFX9-NEXT:    v_bfi_b32 v3, s4, v2, v1
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v5|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
+; ISEL_GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v3, v4, v3
+; ISEL_GFX9-NEXT:    v_trunc_f16_e32 v4, v1
+; ISEL_GFX9-NEXT:    v_sub_f16_e32 v5, v1, v4
+; ISEL_GFX9-NEXT:    v_bfi_b32 v1, s4, v2, v1
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v5|, 0.5
+; ISEL_GFX9-NEXT:    v_trunc_f16_e32 v5, v0
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX9-NEXT:    v_sub_f16_e32 v6, v0, v5
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v1, v4, v1
+; ISEL_GFX9-NEXT:    v_bfi_b32 v4, s4, v2, v0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v6|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
+; ISEL_GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v4, v5, v4
+; ISEL_GFX9-NEXT:    v_trunc_f16_e32 v5, v0
+; ISEL_GFX9-NEXT:    v_sub_f16_e32 v6, v0, v5
+; ISEL_GFX9-NEXT:    v_bfi_b32 v0, s4, v2, v0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f16_e64 vcc, |v6|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; ISEL_GFX9-NEXT:    v_add_f16_e32 v0, v5, v0
+; ISEL_GFX9-NEXT:    v_pack_b32_f16 v0, v4, v0
+; ISEL_GFX9-NEXT:    v_pack_b32_f16 v1, v3, v1
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_v4f16:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f16_e32 v2, v1
+; ISEL_GFX10-NEXT:    s_movk_i32 s4, 0x3c00
+; ISEL_GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
+; ISEL_GFX10-NEXT:    v_bfi_b32 v3, 0x7fff, s4, v1
+; ISEL_GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; ISEL_GFX10-NEXT:    v_trunc_f16_e32 v6, v0
+; ISEL_GFX10-NEXT:    v_sub_f16_e32 v1, v1, v2
+; ISEL_GFX10-NEXT:    v_bfi_b32 v7, 0x7fff, s4, v0
+; ISEL_GFX10-NEXT:    v_trunc_f16_e32 v8, v4
+; ISEL_GFX10-NEXT:    v_trunc_f16_e32 v9, v5
+; ISEL_GFX10-NEXT:    v_sub_f16_e32 v0, v0, v6
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX10-NEXT:    v_sub_f16_e32 v10, v5, v9
+; ISEL_GFX10-NEXT:    v_bfi_b32 v5, 0x7fff, s4, v5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX10-NEXT:    v_sub_f16_e32 v3, v4, v8
+; ISEL_GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, s4, v4
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v1, v2, v1
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v7, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v10|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v0, v6, v0
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v3|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v2, v9, v5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc_lo
+; ISEL_GFX10-NEXT:    v_pack_b32_f16 v0, v0, v2
+; ISEL_GFX10-NEXT:    v_add_f16_e32 v3, v8, v3
+; ISEL_GFX10-NEXT:    v_pack_b32_f16 v1, v1, v3
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_v4f16:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f16_e32 v2, v1
+; ISEL_GFX11-NEXT:    s_movk_i32 s0, 0x3c00
+; ISEL_GFX11-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
+; ISEL_GFX11-NEXT:    v_bfi_b32 v3, 0x7fff, s0, v1
+; ISEL_GFX11-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; ISEL_GFX11-NEXT:    v_trunc_f16_e32 v6, v0
+; ISEL_GFX11-NEXT:    v_sub_f16_e32 v1, v1, v2
+; ISEL_GFX11-NEXT:    v_bfi_b32 v7, 0x7fff, s0, v0
+; ISEL_GFX11-NEXT:    v_trunc_f16_e32 v8, v4
+; ISEL_GFX11-NEXT:    v_trunc_f16_e32 v9, v5
+; ISEL_GFX11-NEXT:    v_sub_f16_e32 v0, v0, v6
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX11-NEXT:    v_sub_f16_e32 v10, v5, v9
+; ISEL_GFX11-NEXT:    v_bfi_b32 v5, 0x7fff, s0, v5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX11-NEXT:    v_sub_f16_e32 v3, v4, v8
+; ISEL_GFX11-NEXT:    v_bfi_b32 v4, 0x7fff, s0, v4
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v1, v2, v1
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v7, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v10|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc_lo
+; ISEL_GFX11-NEXT:    v_cmp_ge_f16_e64 vcc_lo, |v3|, 0.5
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v0, v6, v0
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v2, v9, v5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v3, 0, v4, vcc_lo
+; ISEL_GFX11-NEXT:    v_pack_b32_f16 v0, v0, v2
+; ISEL_GFX11-NEXT:    v_add_f16_e32 v3, v8, v3
+; ISEL_GFX11-NEXT:    v_pack_b32_f16 v1, v1, v3
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %x)
+  ret <4 x half> %roundeven
+}
+
+
+define float @v_roundeven_f32_fabs(float %x) {
+; GFX6-LABEL: v_roundeven_f32_fabs:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_rndne_f32_e64 v0, |v0|
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_f32_fabs:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f32_e64 v0, |v0|
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_f32_fabs:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f32_e64 v0, |v0|
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_f32_fabs:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f32_e64 v0, |v0|
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_f32_fabs:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f32_e64 v0, |v0|
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_f32_fabs:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_trunc_f32_e64 v1, |v0|
+; ISEL_GFX6-NEXT:    v_sub_f32_e64 v0, |v0|, v1
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s[4:5]
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_f32_fabs:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_trunc_f32_e64 v1, |v0|
+; ISEL_GFX7-NEXT:    v_sub_f32_e64 v0, |v0|, v1
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s[4:5]
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_f32_fabs:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    v_trunc_f32_e64 v1, |v0|
+; ISEL_GFX8-NEXT:    v_sub_f32_e64 v0, |v0|, v1
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s[4:5]
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_f32_fabs:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    v_trunc_f32_e64 v1, |v0|
+; ISEL_GFX9-NEXT:    v_sub_f32_e64 v0, |v0|, v1
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s[4:5]
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_f32_fabs:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f32_e64 v1, |v0|
+; ISEL_GFX10-NEXT:    v_sub_f32_e64 v0, |v0|, v1
+; ISEL_GFX10-NEXT:    v_cmp_ge_f32_e64 s4, |v0|, 0.5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s4
+; ISEL_GFX10-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_f32_fabs:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f32_e64 v1, |v0|
+; ISEL_GFX11-NEXT:    v_sub_f32_e64 v0, |v0|, v1
+; ISEL_GFX11-NEXT:    v_cmp_ge_f32_e64 s0, |v0|, 0.5
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s0
+; ISEL_GFX11-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %fabs.x = call float @llvm.fabs.f32(float %x)
+  %roundeven = call float @llvm.roundeven.f32(float %fabs.x)
+  ret float %roundeven
+}
+
+define amdgpu_ps float @s_roundeven_f32(float inreg %x) {
+; GFX6-LABEL: s_roundeven_f32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    v_rndne_f32_e32 v0, s0
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX7-LABEL: s_roundeven_f32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_rndne_f32_e32 v0, s0
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_roundeven_f32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_rndne_f32_e32 v0, s0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_roundeven_f32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_rndne_f32_e32 v0, s0
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10PLUS-LABEL: s_roundeven_f32:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    v_rndne_f32_e32 v0, s0
+; GFX10PLUS-NEXT:    ; return to shader part epilog
+;
+; ISEL_GFX6-LABEL: s_roundeven_f32:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    v_trunc_f32_e32 v1, s0
+; ISEL_GFX6-NEXT:    s_brev_b32 s1, -2
+; ISEL_GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; ISEL_GFX6-NEXT:    v_sub_f32_e32 v2, s0, v1
+; ISEL_GFX6-NEXT:    v_bfi_b32 v0, s1, 1.0, v0
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX6-NEXT:    ; return to shader part epilog
+;
+; ISEL_GFX7-LABEL: s_roundeven_f32:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    v_trunc_f32_e32 v1, s0
+; ISEL_GFX7-NEXT:    s_brev_b32 s1, -2
+; ISEL_GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; ISEL_GFX7-NEXT:    v_sub_f32_e32 v2, s0, v1
+; ISEL_GFX7-NEXT:    v_bfi_b32 v0, s1, 1.0, v0
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX7-NEXT:    ; return to shader part epilog
+;
+; ISEL_GFX8-LABEL: s_roundeven_f32:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    v_trunc_f32_e32 v1, s0
+; ISEL_GFX8-NEXT:    s_brev_b32 s1, -2
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; ISEL_GFX8-NEXT:    v_sub_f32_e32 v2, s0, v1
+; ISEL_GFX8-NEXT:    v_bfi_b32 v0, s1, 1.0, v0
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX8-NEXT:    ; return to shader part epilog
+;
+; ISEL_GFX9-LABEL: s_roundeven_f32:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    v_trunc_f32_e32 v1, s0
+; ISEL_GFX9-NEXT:    s_brev_b32 s1, -2
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; ISEL_GFX9-NEXT:    v_sub_f32_e32 v2, s0, v1
+; ISEL_GFX9-NEXT:    v_bfi_b32 v0, s1, 1.0, v0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX9-NEXT:    ; return to shader part epilog
+;
+; ISEL_GFX10PLUS-LABEL: s_roundeven_f32:
+; ISEL_GFX10PLUS:       ; %bb.0:
+; ISEL_GFX10PLUS-NEXT:    v_trunc_f32_e32 v0, s0
+; ISEL_GFX10PLUS-NEXT:    v_bfi_b32 v2, 0x7fffffff, 1.0, s0
+; ISEL_GFX10PLUS-NEXT:    v_sub_f32_e32 v1, s0, v0
+; ISEL_GFX10PLUS-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v1|, 0.5
+; ISEL_GFX10PLUS-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc_lo
+; ISEL_GFX10PLUS-NEXT:    v_add_f32_e32 v0, v0, v1
+; ISEL_GFX10PLUS-NEXT:    ; return to shader part epilog
+  %roundeven = call float @llvm.roundeven.f32(float %x)
+  ret float %roundeven
+}
+
+define float @v_roundeven_f32_fneg(float %x) {
+; GFX6-LABEL: v_roundeven_f32_fneg:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_rndne_f32_e64 v0, -v0
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_f32_fneg:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f32_e64 v0, -v0
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_f32_fneg:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f32_e64 v0, -v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_f32_fneg:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f32_e64 v0, -v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_f32_fneg:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f32_e64 v0, -v0
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_f32_fneg:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_trunc_f32_e64 v2, -v0
+; ISEL_GFX6-NEXT:    v_xor_b32_e32 v1, 0x80000000, v0
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_sub_f32_e64 v0, -v0, v2
+; ISEL_GFX6-NEXT:    v_bfi_b32 v1, s4, 1.0, v1
+; ISEL_GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX6-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_f32_fneg:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_trunc_f32_e64 v2, -v0
+; ISEL_GFX7-NEXT:    v_xor_b32_e32 v1, 0x80000000, v0
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_sub_f32_e64 v0, -v0, v2
+; ISEL_GFX7-NEXT:    v_bfi_b32 v1, s4, 1.0, v1
+; ISEL_GFX7-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX7-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_f32_fneg:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    v_trunc_f32_e64 v2, -v0
+; ISEL_GFX8-NEXT:    v_xor_b32_e32 v1, 0x80000000, v0
+; ISEL_GFX8-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX8-NEXT:    v_sub_f32_e64 v0, -v0, v2
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, 1.0, v1
+; ISEL_GFX8-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_f32_fneg:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    v_trunc_f32_e64 v2, -v0
+; ISEL_GFX9-NEXT:    v_xor_b32_e32 v1, 0x80000000, v0
+; ISEL_GFX9-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX9-NEXT:    v_sub_f32_e64 v0, -v0, v2
+; ISEL_GFX9-NEXT:    v_bfi_b32 v1, s4, 1.0, v1
+; ISEL_GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
+; ISEL_GFX9-NEXT:    v_add_f32_e32 v0, v2, v0
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10PLUS-LABEL: v_roundeven_f32_fneg:
+; ISEL_GFX10PLUS:       ; %bb.0:
+; ISEL_GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10PLUS-NEXT:    v_trunc_f32_e64 v1, -v0
+; ISEL_GFX10PLUS-NEXT:    v_xor_b32_e32 v2, 0x80000000, v0
+; ISEL_GFX10PLUS-NEXT:    v_sub_f32_e64 v0, -v0, v1
+; ISEL_GFX10PLUS-NEXT:    v_bfi_b32 v2, 0x7fffffff, 1.0, v2
+; ISEL_GFX10PLUS-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v0|, 0.5
+; ISEL_GFX10PLUS-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc_lo
+; ISEL_GFX10PLUS-NEXT:    v_add_f32_e32 v0, v1, v0
+; ISEL_GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+  %neg.x = fneg float %x
+  %roundeven = call float @llvm.roundeven.f32(float %neg.x)
+  ret float %roundeven
+}
+
+define double @v_roundeven_f64(double %x) {
+; GFX6-LABEL: v_roundeven_f64:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_and_b32_e32 v3, 0x80000000, v1
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0
+; GFX6-NEXT:    v_or_b32_e32 v3, 0x43300000, v3
+; GFX6-NEXT:    v_add_f64 v[4:5], v[0:1], v[2:3]
+; GFX6-NEXT:    s_mov_b32 s4, -1
+; GFX6-NEXT:    s_mov_b32 s5, 0x432fffff
+; GFX6-NEXT:    v_add_f64 v[2:3], v[4:5], -v[2:3]
+; GFX6-NEXT:    v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_f64:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_f64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_f64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_f64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_f64:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_bfe_u32 v2, v1, 20, 11
+; ISEL_GFX6-NEXT:    s_mov_b32 s4, -1
+; ISEL_GFX6-NEXT:    v_add_i32_e32 v4, vcc, 0xfffffc01, v2
+; ISEL_GFX6-NEXT:    s_mov_b32 s5, 0xfffff
+; ISEL_GFX6-NEXT:    v_lshr_b64 v[2:3], s[4:5], v4
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
+; ISEL_GFX6-NEXT:    v_not_b32_e32 v3, v3
+; ISEL_GFX6-NEXT:    v_not_b32_e32 v2, v2
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v3, v1, v3
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v2, v0, v2
+; ISEL_GFX6-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v4
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
+; ISEL_GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], 51, v4
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, 0, vcc
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v1, s[4:5]
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v0, s[4:5]
+; ISEL_GFX6-NEXT:    v_add_f64 v[4:5], v[0:1], -v[2:3]
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_mov_b32_e32 v0, 0x3ff00000
+; ISEL_GFX6-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; ISEL_GFX6-NEXT:    v_bfi_b32 v0, s4, v0, v1
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
+; ISEL_GFX6-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX6-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_f64:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_add_f64 v[4:5], v[0:1], -v[2:3]
+; ISEL_GFX7-NEXT:    v_mov_b32_e32 v0, 0x3ff00000
+; ISEL_GFX7-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; ISEL_GFX7-NEXT:    v_bfi_b32 v0, s4, v0, v1
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
+; ISEL_GFX7-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX7-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_f64:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
+; ISEL_GFX8-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v6, 0x3ff00000
+; ISEL_GFX8-NEXT:    v_add_f64 v[4:5], v[0:1], -v[2:3]
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, v6, v1
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX8-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_f64:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
+; ISEL_GFX9-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v6, 0x3ff00000
+; ISEL_GFX9-NEXT:    v_add_f64 v[4:5], v[0:1], -v[2:3]
+; ISEL_GFX9-NEXT:    v_bfi_b32 v1, s4, v6, v1
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX9-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_f64:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
+; ISEL_GFX10-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX10-NEXT:    v_add_f64 v[4:5], v[0:1], -v[2:3]
+; ISEL_GFX10-NEXT:    v_bfi_b32 v1, s4, 0x3ff00000, v1
+; ISEL_GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX10-NEXT:    v_cmp_ge_f64_e64 vcc_lo, |v[4:5]|, 0.5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_f64:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
+; ISEL_GFX11-NEXT:    s_brev_b32 s0, -2
+; ISEL_GFX11-NEXT:    v_add_f64 v[4:5], v[0:1], -v[2:3]
+; ISEL_GFX11-NEXT:    v_bfi_b32 v1, s0, 0x3ff00000, v1
+; ISEL_GFX11-NEXT:    v_cmp_ge_f64_e64 vcc_lo, |v[4:5]|, 0.5
+; ISEL_GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_cndmask_b32 v1, 0, v1
+; ISEL_GFX11-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call double @llvm.roundeven.f64(double %x)
+  ret double %roundeven
+}
+
+define double @v_roundeven_f64_fneg(double %x) {
+; GFX6-LABEL: v_roundeven_f64_fneg:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_xor_b32_e32 v6, 0x80000000, v1
+; GFX6-NEXT:    v_and_b32_e32 v3, 0x80000000, v6
+; GFX6-NEXT:    v_mov_b32_e32 v2, 0
+; GFX6-NEXT:    v_or_b32_e32 v3, 0x43300000, v3
+; GFX6-NEXT:    v_add_f64 v[4:5], -v[0:1], v[2:3]
+; GFX6-NEXT:    s_mov_b32 s4, -1
+; GFX6-NEXT:    s_mov_b32 s5, 0x432fffff
+; GFX6-NEXT:    v_add_f64 v[2:3], v[4:5], -v[2:3]
+; GFX6-NEXT:    v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v3, v6, vcc
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_f64_fneg:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f64_e64 v[0:1], -v[0:1]
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_f64_fneg:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f64_e64 v[0:1], -v[0:1]
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_f64_fneg:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f64_e64 v[0:1], -v[0:1]
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_f64_fneg:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f64_e64 v[0:1], -v[0:1]
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_f64_fneg:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_xor_b32_e32 v4, 0x80000000, v1
+; ISEL_GFX6-NEXT:    v_bfe_u32 v2, v4, 20, 11
+; ISEL_GFX6-NEXT:    s_mov_b32 s4, -1
+; ISEL_GFX6-NEXT:    v_add_i32_e32 v5, vcc, 0xfffffc01, v2
+; ISEL_GFX6-NEXT:    s_mov_b32 s5, 0xfffff
+; ISEL_GFX6-NEXT:    v_lshr_b64 v[2:3], s[4:5], v5
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v6, 0x80000000, v4
+; ISEL_GFX6-NEXT:    v_not_b32_e32 v3, v3
+; ISEL_GFX6-NEXT:    v_not_b32_e32 v2, v2
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v3, v4, v3
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v2, v0, v2
+; ISEL_GFX6-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
+; ISEL_GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], 51, v5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, 0, vcc
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[4:5]
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v0, s[4:5]
+; ISEL_GFX6-NEXT:    v_add_f64 v[0:1], -v[0:1], -v[2:3]
+; ISEL_GFX6-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX6-NEXT:    v_mov_b32_e32 v5, 0x3ff00000
+; ISEL_GFX6-NEXT:    v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
+; ISEL_GFX6-NEXT:    v_bfi_b32 v4, s4, v5, v4
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; ISEL_GFX6-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX6-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_f64_fneg:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_trunc_f64_e64 v[2:3], -v[0:1]
+; ISEL_GFX7-NEXT:    v_xor_b32_e32 v4, 0x80000000, v1
+; ISEL_GFX7-NEXT:    v_add_f64 v[0:1], -v[0:1], -v[2:3]
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_mov_b32_e32 v5, 0x3ff00000
+; ISEL_GFX7-NEXT:    v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
+; ISEL_GFX7-NEXT:    v_bfi_b32 v4, s4, v5, v4
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; ISEL_GFX7-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX7-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_f64_fneg:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    v_trunc_f64_e64 v[2:3], -v[0:1]
+; ISEL_GFX8-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v6, 0x3ff00000
+; ISEL_GFX8-NEXT:    v_add_f64 v[4:5], -v[0:1], -v[2:3]
+; ISEL_GFX8-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, v6, v1
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX8-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_f64_fneg:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    v_trunc_f64_e64 v[2:3], -v[0:1]
+; ISEL_GFX9-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v6, 0x3ff00000
+; ISEL_GFX9-NEXT:    v_add_f64 v[4:5], -v[0:1], -v[2:3]
+; ISEL_GFX9-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
+; ISEL_GFX9-NEXT:    v_bfi_b32 v1, s4, v6, v1
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX9-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_f64_fneg:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f64_e64 v[2:3], -v[0:1]
+; ISEL_GFX10-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX10-NEXT:    v_add_f64 v[4:5], -v[0:1], -v[2:3]
+; ISEL_GFX10-NEXT:    v_xor_b32_e32 v0, 0x80000000, v1
+; ISEL_GFX10-NEXT:    v_bfi_b32 v1, s4, 0x3ff00000, v0
+; ISEL_GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX10-NEXT:    v_cmp_ge_f64_e64 vcc_lo, |v[4:5]|, 0.5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_f64_fneg:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f64_e64 v[2:3], -v[0:1]
+; ISEL_GFX11-NEXT:    s_brev_b32 s0, -2
+; ISEL_GFX11-NEXT:    v_add_f64 v[4:5], -v[0:1], -v[2:3]
+; ISEL_GFX11-NEXT:    v_xor_b32_e32 v0, 0x80000000, v1
+; ISEL_GFX11-NEXT:    v_bfi_b32 v1, s0, 0x3ff00000, v0
+; ISEL_GFX11-NEXT:    v_cmp_ge_f64_e64 vcc_lo, |v[4:5]|, 0.5
+; ISEL_GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_cndmask_b32 v1, 0, v1
+; ISEL_GFX11-NEXT:    v_add_f64 v[0:1], v[2:3], v[0:1]
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %neg.x = fneg double %x
+  %roundeven = call double @llvm.roundeven.f64(double %neg.x)
+  ret double %roundeven
+}
+
+define <2 x double> @v_roundeven_v2f64(<2 x double> %x) {
+; GFX6-LABEL: v_roundeven_v2f64:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_and_b32_e32 v5, 0x80000000, v1
+; GFX6-NEXT:    v_mov_b32_e32 v4, 0
+; GFX6-NEXT:    v_or_b32_e32 v5, 0x43300000, v5
+; GFX6-NEXT:    v_add_f64 v[6:7], v[0:1], v[4:5]
+; GFX6-NEXT:    s_mov_b32 s4, -1
+; GFX6-NEXT:    s_mov_b32 s5, 0x432fffff
+; GFX6-NEXT:    v_add_f64 v[5:6], v[6:7], -v[4:5]
+; GFX6-NEXT:    v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
+; GFX6-NEXT:    v_and_b32_e32 v5, 0x80000000, v3
+; GFX6-NEXT:    v_or_b32_e32 v5, 0x43300000, v5
+; GFX6-NEXT:    v_add_f64 v[7:8], v[2:3], v[4:5]
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
+; GFX6-NEXT:    v_add_f64 v[4:5], v[7:8], -v[4:5]
+; GFX6-NEXT:    v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[4:5]
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_roundeven_v2f64:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
+; GFX7-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_roundeven_v2f64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
+; GFX8-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_roundeven_v2f64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
+; GFX9-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10PLUS-LABEL: v_roundeven_v2f64:
+; GFX10PLUS:       ; %bb.0:
+; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT:    v_rndne_f64_e32 v[0:1], v[0:1]
+; GFX10PLUS-NEXT:    v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX6-LABEL: v_roundeven_v2f64:
+; ISEL_GFX6:       ; %bb.0:
+; ISEL_GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX6-NEXT:    v_bfe_u32 v4, v1, 20, 11
+; ISEL_GFX6-NEXT:    s_mov_b32 s6, -1
+; ISEL_GFX6-NEXT:    v_add_i32_e32 v6, vcc, 0xfffffc01, v4
+; ISEL_GFX6-NEXT:    s_mov_b32 s7, 0xfffff
+; ISEL_GFX6-NEXT:    v_lshr_b64 v[4:5], s[6:7], v6
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v7, 0x80000000, v1
+; ISEL_GFX6-NEXT:    v_not_b32_e32 v5, v5
+; ISEL_GFX6-NEXT:    v_not_b32_e32 v4, v4
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v5, v1, v5
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v4, v0, v4
+; ISEL_GFX6-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v6
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
+; ISEL_GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], 51, v6
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v5, v5, v1, s[4:5]
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v0, s[4:5]
+; ISEL_GFX6-NEXT:    v_add_f64 v[6:7], v[0:1], -v[4:5]
+; ISEL_GFX6-NEXT:    s_brev_b32 s9, -2
+; ISEL_GFX6-NEXT:    v_mov_b32_e32 v8, 0x3ff00000
+; ISEL_GFX6-NEXT:    v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
+; ISEL_GFX6-NEXT:    s_movk_i32 s8, 0xfc01
+; ISEL_GFX6-NEXT:    v_bfi_b32 v0, s9, v8, v1
+; ISEL_GFX6-NEXT:    v_bfe_u32 v6, v3, 20, 11
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
+; ISEL_GFX6-NEXT:    v_add_i32_e32 v9, vcc, s8, v6
+; ISEL_GFX6-NEXT:    v_lshr_b64 v[6:7], s[6:7], v9
+; ISEL_GFX6-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX6-NEXT:    v_add_f64 v[0:1], v[4:5], v[0:1]
+; ISEL_GFX6-NEXT:    v_not_b32_e32 v4, v7
+; ISEL_GFX6-NEXT:    v_not_b32_e32 v5, v6
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v4, v3, v4
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v6, v2, v5
+; ISEL_GFX6-NEXT:    v_and_b32_e32 v5, 0x80000000, v3
+; ISEL_GFX6-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v9
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
+; ISEL_GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], 51, v9
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v5, v4, v3, s[4:5]
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, 0, vcc
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v2, s[4:5]
+; ISEL_GFX6-NEXT:    v_add_f64 v[6:7], v[2:3], -v[4:5]
+; ISEL_GFX6-NEXT:    v_bfi_b32 v2, s9, v8, v3
+; ISEL_GFX6-NEXT:    v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
+; ISEL_GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v2, vcc
+; ISEL_GFX6-NEXT:    v_mov_b32_e32 v2, 0
+; ISEL_GFX6-NEXT:    v_add_f64 v[2:3], v[4:5], v[2:3]
+; ISEL_GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX7-LABEL: v_roundeven_v2f64:
+; ISEL_GFX7:       ; %bb.0:
+; ISEL_GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX7-NEXT:    v_trunc_f64_e32 v[4:5], v[0:1]
+; ISEL_GFX7-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX7-NEXT:    v_add_f64 v[6:7], v[0:1], -v[4:5]
+; ISEL_GFX7-NEXT:    v_mov_b32_e32 v8, 0x3ff00000
+; ISEL_GFX7-NEXT:    v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
+; ISEL_GFX7-NEXT:    v_bfi_b32 v0, s4, v8, v1
+; ISEL_GFX7-NEXT:    v_trunc_f64_e32 v[6:7], v[2:3]
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v1, 0, v0, vcc
+; ISEL_GFX7-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX7-NEXT:    v_add_f64 v[0:1], v[4:5], v[0:1]
+; ISEL_GFX7-NEXT:    v_add_f64 v[4:5], v[2:3], -v[6:7]
+; ISEL_GFX7-NEXT:    v_bfi_b32 v2, s4, v8, v3
+; ISEL_GFX7-NEXT:    v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; ISEL_GFX7-NEXT:    v_cndmask_b32_e32 v3, 0, v2, vcc
+; ISEL_GFX7-NEXT:    v_mov_b32_e32 v2, 0
+; ISEL_GFX7-NEXT:    v_add_f64 v[2:3], v[6:7], v[2:3]
+; ISEL_GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX8-LABEL: v_roundeven_v2f64:
+; ISEL_GFX8:       ; %bb.0:
+; ISEL_GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX8-NEXT:    v_trunc_f64_e32 v[4:5], v[0:1]
+; ISEL_GFX8-NEXT:    v_trunc_f64_e32 v[6:7], v[2:3]
+; ISEL_GFX8-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v12, 0x3ff00000
+; ISEL_GFX8-NEXT:    v_add_f64 v[8:9], v[0:1], -v[4:5]
+; ISEL_GFX8-NEXT:    v_add_f64 v[10:11], v[2:3], -v[6:7]
+; ISEL_GFX8-NEXT:    v_bfi_b32 v1, s4, v12, v1
+; ISEL_GFX8-NEXT:    v_bfi_b32 v3, s4, v12, v3
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX8-NEXT:    v_mov_b32_e32 v2, 0
+; ISEL_GFX8-NEXT:    v_cmp_ge_f64_e64 vcc, |v[8:9]|, 0.5
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX8-NEXT:    v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
+; ISEL_GFX8-NEXT:    v_add_f64 v[0:1], v[4:5], v[0:1]
+; ISEL_GFX8-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
+; ISEL_GFX8-NEXT:    v_add_f64 v[2:3], v[6:7], v[2:3]
+; ISEL_GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX9-LABEL: v_roundeven_v2f64:
+; ISEL_GFX9:       ; %bb.0:
+; ISEL_GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX9-NEXT:    v_trunc_f64_e32 v[4:5], v[0:1]
+; ISEL_GFX9-NEXT:    v_trunc_f64_e32 v[6:7], v[2:3]
+; ISEL_GFX9-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v12, 0x3ff00000
+; ISEL_GFX9-NEXT:    v_add_f64 v[8:9], v[0:1], -v[4:5]
+; ISEL_GFX9-NEXT:    v_add_f64 v[10:11], v[2:3], -v[6:7]
+; ISEL_GFX9-NEXT:    v_bfi_b32 v1, s4, v12, v1
+; ISEL_GFX9-NEXT:    v_bfi_b32 v3, s4, v12, v3
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; ISEL_GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; ISEL_GFX9-NEXT:    v_cmp_ge_f64_e64 vcc, |v[8:9]|, 0.5
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; ISEL_GFX9-NEXT:    v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
+; ISEL_GFX9-NEXT:    v_add_f64 v[0:1], v[4:5], v[0:1]
+; ISEL_GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
+; ISEL_GFX9-NEXT:    v_add_f64 v[2:3], v[6:7], v[2:3]
+; ISEL_GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX10-LABEL: v_roundeven_v2f64:
+; ISEL_GFX10:       ; %bb.0:
+; ISEL_GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX10-NEXT:    v_trunc_f64_e32 v[4:5], v[0:1]
+; ISEL_GFX10-NEXT:    v_trunc_f64_e32 v[6:7], v[2:3]
+; ISEL_GFX10-NEXT:    s_brev_b32 s4, -2
+; ISEL_GFX10-NEXT:    v_mov_b32_e32 v12, 0
+; ISEL_GFX10-NEXT:    v_add_f64 v[8:9], v[0:1], -v[4:5]
+; ISEL_GFX10-NEXT:    v_add_f64 v[10:11], v[2:3], -v[6:7]
+; ISEL_GFX10-NEXT:    v_bfi_b32 v0, s4, 0x3ff00000, v1
+; ISEL_GFX10-NEXT:    v_bfi_b32 v2, s4, 0x3ff00000, v3
+; ISEL_GFX10-NEXT:    v_cmp_ge_f64_e64 vcc_lo, |v[8:9]|, 0.5
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v13, 0, v0, vcc_lo
+; ISEL_GFX10-NEXT:    v_cmp_ge_f64_e64 vcc_lo, |v[10:11]|, 0.5
+; ISEL_GFX10-NEXT:    v_add_f64 v[0:1], v[4:5], v[12:13]
+; ISEL_GFX10-NEXT:    v_cndmask_b32_e32 v13, 0, v2, vcc_lo
+; ISEL_GFX10-NEXT:    v_add_f64 v[2:3], v[6:7], v[12:13]
+; ISEL_GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; ISEL_GFX11-LABEL: v_roundeven_v2f64:
+; ISEL_GFX11:       ; %bb.0:
+; ISEL_GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ISEL_GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; ISEL_GFX11-NEXT:    v_trunc_f64_e32 v[4:5], v[0:1]
+; ISEL_GFX11-NEXT:    v_trunc_f64_e32 v[6:7], v[2:3]
+; ISEL_GFX11-NEXT:    s_brev_b32 s0, -2
+; ISEL_GFX11-NEXT:    v_add_f64 v[8:9], v[0:1], -v[4:5]
+; ISEL_GFX11-NEXT:    v_add_f64 v[10:11], v[2:3], -v[6:7]
+; ISEL_GFX11-NEXT:    v_bfi_b32 v0, s0, 0x3ff00000, v1
+; ISEL_GFX11-NEXT:    v_bfi_b32 v2, s0, 0x3ff00000, v3
+; ISEL_GFX11-NEXT:    v_cmp_ge_f64_e64 vcc_lo, |v[8:9]|, 0.5
+; ISEL_GFX11-NEXT:    v_dual_mov_b32 v12, 0 :: v_dual_cndmask_b32 v13, 0, v0
+; ISEL_GFX11-NEXT:    v_cmp_ge_f64_e64 vcc_lo, |v[10:11]|, 0.5
+; ISEL_GFX11-NEXT:    v_add_f64 v[0:1], v[4:5], v[12:13]
+; ISEL_GFX11-NEXT:    v_cndmask_b32_e32 v13, 0, v2, vcc_lo
+; ISEL_GFX11-NEXT:    v_add_f64 v[2:3], v[6:7], v[12:13]
+; ISEL_GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %roundeven = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %x)
+  ret <2 x double> %roundeven
+}
+
+declare half @llvm.roundeven.f16(half) #0
+declare <2 x half> @llvm.roundeven.v2f16(<2 x half>) #0
+declare <4 x half> @llvm.roundeven.v4f16(<4 x half>) #0
+
+declare float @llvm.roundeven.f32(float) #0
+declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) #0
+declare <3 x float> @llvm.roundeven.v3f32(<3 x float>) #0
+declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #0
+
+declare double @llvm.roundeven.f64(double) #0
+declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) #0
+
+declare half @llvm.fabs.f16(half) #0
+declare float @llvm.fabs.f32(float) #0
+
+attributes #0 = { nounwind readnone speculatable willreturn }