[X86] Add missing Zen3 model subtypes

[RKSimon]

Summary

This patch adds support for detecting all current Zen/Zen3+ submodels

Based off a mixture of https://github.com/torvalds/linux/blob/master/drivers/hwmon/k10temp.c#L436 and InstLatx64 https://github.com/InstLatx64/InstLatx64/tree/master/AuthenticAMD CPUID dumps and confirmed by @GGanesh

[FreddyYe]

compiler-rt/lib/builtins/cpu_model.c

630

Where can we find the Model values? Meanwhile I cannot find the new condition in gcc's codes either.

[RKSimon]

CC'ing @GGanesh who might might be able to suggest where we can get further references.

compiler-rt/lib/builtins/cpu_model.c

630

AMD are really slow at providing this kind of documentation and its a mess - there is a reference to Fam19h-51h at https://www.amd.com/en/support/tech-docs?keyword=19h but not the rest of the range.

As I said in the summary I took the CPUIDs that have been seen by InstLatx64 and mapped those to the linux kernel code for confirmation - the best you can then do is look at the git history of the file to see when those cases were added, at least some of those change came from the AMD kernel team.

gcc might not have bothered as zen3+ is really just changes to IGPU and cache, not the ISA feature/tuning set.

@lebedev.ri Might be able to give a little more insight - I based this change off his previous patch for additional zen3 models: D121708

[GGanesh]

The following are the AMD Zen3 models.

Family 19h Models 00h-0Fh - Zen3
Family 19h Models 20h-2Fh - Zen3
Family 19h Models 30h-3Fh - Zen3
Family 19h Models 40h-4Fh - Zen3
Family 19h Models 50h-5Fh - Zen3

You need to exclude 10h-1Fh

[RKSimon]

Thanks!

[FreddyYe]

compiler-rt/lib/builtins/cpu_model.c

630

Thanks for your detailed explaining!

compiler-rt/lib/builtins/cpu_model.c

case 23:
     if (Model <= 0x0f) {
       *Subtype = AMDFAM17H_ZNVER1;
       break; // 00h-0Fh: Zen1
     }
     break;
   case 25:
     CPU = "znver3";
     *Type = AMDFAM19H;
-    if (Model <= 0x0f || Model == 0x21) {
+    if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
+      // Family 19h Models 00h-0Fh - Zen3
+      // Family 19h Models 20h-2Fh - Zen3
+      // Family 19h Models 30h-3Fh - Zen3
+      // Family 19h Models 40h-4Fh - Zen3+
+      // Family 19h Models 50h-5Fh - Zen3+
       *Subtype = AMDFAM19H_ZNVER3;
-      break; // 00h-0Fh, 21h: Zen3
+      break;
     }
     break;
   default:
     break; // Unknown AMD CPU.
   }
 
   return CPU;
 }
 
 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,

llvm/lib/Support/Host.cpp

case 23:
     if (Model <= 0x0f) {
       *Subtype = X86::AMDFAM17H_ZNVER1;
       break; // 00h-0Fh: Zen1
     }
     break;
   case 25:
     CPU = "znver3";
     *Type = X86::AMDFAM19H;
-    if (Model <= 0x0f || Model == 0x21) {
+    if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
+      // Family 19h Models 00h-0Fh - Zen3
+      // Family 19h Models 20h-2Fh - Zen3
+      // Family 19h Models 30h-3Fh - Zen3
+      // Family 19h Models 40h-4Fh - Zen3+
+      // Family 19h Models 50h-5Fh - Zen3+
       *Subtype = X86::AMDFAM19H_ZNVER3;
-      break; // 00h-0Fh, 21h: Zen3
+      break;
     }
     break;
   default:
     break; // Unknown AMD CPU.
   }
 
   return CPU;
 }