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Differential D137508

[LLDB][RISCV] Allow accessing registers through ABI names
ClosedPublic

Authored by Emmmer on Nov 6 2022, 3:27 AM.

Details

Reviewers
DavidSpickett
asb
Commits
rG4113e98ea785: [LLDB][RISCV] Allow accessing registers through ABI names
Summary

This patch uses RISCV ABI register name as alt_name in RegisterInfo in lldb-private-types.h

Diff Detail

Event Timeline

Emmmer created this revision.Nov 6 2022, 3:27 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 6 2022, 3:27 AM
Herald added subscribers: sunshaoce, VincentWu, StephenFan and 28 others. · View Herald Transcript
Emmmer requested review of this revision.Nov 6 2022, 3:27 AM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald TranscriptNov 6 2022, 3:27 AM
Harbormaster completed remote builds in B196346: Diff 473493.Nov 6 2022, 3:30 AM
Emmmer mentioned this in D137761: [LLDB][RISCV] Allow accessing FPR registers through ABI names.Nov 9 2022, 8:35 PM
Emmmer added a child revision: D137761: [LLDB][RISCV] Allow accessing FPR registers through ABI names.
Emmmer added a comment.Nov 9 2022, 8:38 PM

ping

Emmmer added a comment.Nov 16 2022, 9:43 PM

ping @DavidSpickett @asb

DavidSpickett accepted this revision.Nov 17 2022, 3:02 AM

Glanced at "Table 18.2: RISC-V calling convention register usage.", LGTM.

This revision is now accepted and ready to land.Nov 17 2022, 3:02 AM
Closed by commit rG4113e98ea785: [LLDB][RISCV] Allow accessing registers through ABI names (authored by Emmmer). · Explain WhyNov 17 2022, 3:39 AM
This revision was automatically updated to reflect the committed changes.
Emmmer added a commit: rG4113e98ea785: [LLDB][RISCV] Allow accessing registers through ABI names.
Herald added a subscriber: lldb-commits. · View Herald TranscriptNov 17 2022, 3:39 AM
Emmmer mentioned this in rG201ed71cfd7e: [LLDB][RISCV] Allow accessing FPR registers through ABI names.Nov 17 2022, 3:58 AM

Revision Contents

PathSize
lldb/
source/
Plugins/
Process/
Utility/
58 lines
29 lines
Utility/
31 lines

Diff 476078

lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
// clang-format on // clang-format on
static lldb_private::RegisterInfo g_register_infos_riscv64_le[] = { static lldb_private::RegisterInfo g_register_infos_riscv64_le[] = {
// DEFINE_GPR64(name, GENERIC KIND) // DEFINE_GPR64(name, GENERIC KIND)
DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC), DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
DEFINE_GPR64_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA), DEFINE_GPR64_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
DEFINE_GPR64_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP), DEFINE_GPR64_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
DEFINE_GPR64(x3, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(gp, x3, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x4, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(tp, x4, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x5, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(t0, x5, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x6, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(t1, x6, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x7, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(t2, x7, LLDB_INVALID_REGNUM),
DEFINE_GPR64_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP), DEFINE_GPR64_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
DEFINE_GPR64(x9, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s1, x9, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x10, LLDB_REGNUM_GENERIC_ARG1), DEFINE_GPR64_ALT(a0, x10, LLDB_REGNUM_GENERIC_ARG1),
DEFINE_GPR64(x11, LLDB_REGNUM_GENERIC_ARG2), DEFINE_GPR64_ALT(a1, x11, LLDB_REGNUM_GENERIC_ARG2),
DEFINE_GPR64(x12, LLDB_REGNUM_GENERIC_ARG3), DEFINE_GPR64_ALT(a2, x12, LLDB_REGNUM_GENERIC_ARG3),
DEFINE_GPR64(x13, LLDB_REGNUM_GENERIC_ARG4), DEFINE_GPR64_ALT(a3, x13, LLDB_REGNUM_GENERIC_ARG4),
DEFINE_GPR64(x14, LLDB_REGNUM_GENERIC_ARG5), DEFINE_GPR64_ALT(a4, x14, LLDB_REGNUM_GENERIC_ARG5),
DEFINE_GPR64(x15, LLDB_REGNUM_GENERIC_ARG6), DEFINE_GPR64_ALT(a5, x15, LLDB_REGNUM_GENERIC_ARG6),
DEFINE_GPR64(x16, LLDB_REGNUM_GENERIC_ARG7), DEFINE_GPR64_ALT(a6, x16, LLDB_REGNUM_GENERIC_ARG7),
DEFINE_GPR64(x17, LLDB_REGNUM_GENERIC_ARG8), DEFINE_GPR64_ALT(a7, x17, LLDB_REGNUM_GENERIC_ARG8),
DEFINE_GPR64(x18, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s2, x18, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x19, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s3, x19, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x20, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s4, x20, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x21, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s5, x21, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x22, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s6, x22, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x23, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s7, x23, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x24, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s8, x24, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x25, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s9, x25, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x26, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s10, x26, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x27, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(s11, x27, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x28, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(t3, x28, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x29, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(t4, x29, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x30, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(t5, x30, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x31, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(t6, x31, LLDB_INVALID_REGNUM),
DEFINE_GPR64(x0, LLDB_INVALID_REGNUM), DEFINE_GPR64_ALT(zero, x0, LLDB_INVALID_REGNUM),
DEFINE_FPR64(f0, LLDB_INVALID_REGNUM), DEFINE_FPR64(f0, LLDB_INVALID_REGNUM),
DEFINE_FPR64(f1, LLDB_INVALID_REGNUM), DEFINE_FPR64(f1, LLDB_INVALID_REGNUM),
DEFINE_FPR64(f2, LLDB_INVALID_REGNUM), DEFINE_FPR64(f2, LLDB_INVALID_REGNUM),
DEFINE_FPR64(f3, LLDB_INVALID_REGNUM), DEFINE_FPR64(f3, LLDB_INVALID_REGNUM),
DEFINE_FPR64(f4, LLDB_INVALID_REGNUM), DEFINE_FPR64(f4, LLDB_INVALID_REGNUM),
DEFINE_FPR64(f5, LLDB_INVALID_REGNUM), DEFINE_FPR64(f5, LLDB_INVALID_REGNUM),
DEFINE_FPR64(f6, LLDB_INVALID_REGNUM), DEFINE_FPR64(f6, LLDB_INVALID_REGNUM),
Show All 28 Lines

lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linesenum {
gpr_x26_riscv, gpr_x26_riscv,
gpr_x27_riscv, gpr_x27_riscv,
gpr_x28_riscv, gpr_x28_riscv,
gpr_x29_riscv, gpr_x29_riscv,
gpr_x30_riscv, gpr_x30_riscv,
gpr_x31_riscv, gpr_x31_riscv,
gpr_x0_riscv, gpr_x0_riscv,
gpr_last_riscv = gpr_x0_riscv, gpr_last_riscv = gpr_x0_riscv,
gpr_zero_riscv = gpr_x0_riscv,
gpr_ra_riscv = gpr_x1_riscv, gpr_ra_riscv = gpr_x1_riscv,
gpr_sp_riscv = gpr_x2_riscv, gpr_sp_riscv = gpr_x2_riscv,
gpr_gp_riscv = gpr_x3_riscv,
gpr_tp_riscv = gpr_x4_riscv,
gpr_t0_riscv = gpr_x5_riscv,
gpr_t1_riscv = gpr_x6_riscv,
gpr_t2_riscv = gpr_x7_riscv,
gpr_fp_riscv = gpr_x8_riscv, gpr_fp_riscv = gpr_x8_riscv,
gpr_s1_riscv = gpr_x9_riscv,
gpr_a0_riscv = gpr_x10_riscv,
gpr_a1_riscv = gpr_x11_riscv,
gpr_a2_riscv = gpr_x12_riscv,
gpr_a3_riscv = gpr_x13_riscv,
gpr_a4_riscv = gpr_x14_riscv,
gpr_a5_riscv = gpr_x15_riscv,
gpr_a6_riscv = gpr_x16_riscv,
gpr_a7_riscv = gpr_x17_riscv,
gpr_s2_riscv = gpr_x18_riscv,
gpr_s3_riscv = gpr_x19_riscv,
gpr_s4_riscv = gpr_x20_riscv,
gpr_s5_riscv = gpr_x21_riscv,
gpr_s6_riscv = gpr_x22_riscv,
gpr_s7_riscv = gpr_x23_riscv,
gpr_s8_riscv = gpr_x24_riscv,
gpr_s9_riscv = gpr_x25_riscv,
gpr_s10_riscv = gpr_x26_riscv,
gpr_s11_riscv = gpr_x27_riscv,
gpr_t3_riscv = gpr_x28_riscv,
gpr_t4_riscv = gpr_x29_riscv,
gpr_t5_riscv = gpr_x30_riscv,
gpr_t6_riscv = gpr_x31_riscv,
fpr_first_riscv = 33, fpr_first_riscv = 33,
fpr_f0_riscv = fpr_first_riscv, fpr_f0_riscv = fpr_first_riscv,
fpr_f1_riscv, fpr_f1_riscv,
fpr_f2_riscv, fpr_f2_riscv,
fpr_f3_riscv, fpr_f3_riscv,
fpr_f4_riscv, fpr_f4_riscv,
fpr_f5_riscv, fpr_f5_riscv,
Show All 34 Lines

lldb/source/Utility/RISCV_DWARF_Registers.h

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Linesenum {
dwarf_v27, dwarf_v27,
dwarf_v28, dwarf_v28,
dwarf_v29, dwarf_v29,
dwarf_v30, dwarf_v30,
dwarf_v31 = 127, dwarf_v31 = 127,
dwarf_first_csr = 4096, dwarf_first_csr = 4096,
dwarf_last_csr = 8191, dwarf_last_csr = 8191,
// register name alias // register ABI name
dwarf_gpr_zero = dwarf_gpr_x0,
dwarf_gpr_ra = dwarf_gpr_x1, dwarf_gpr_ra = dwarf_gpr_x1,
dwarf_gpr_sp = dwarf_gpr_x2, dwarf_gpr_sp = dwarf_gpr_x2,
dwarf_gpr_gp = dwarf_gpr_x3,
dwarf_gpr_tp = dwarf_gpr_x4,
dwarf_gpr_t0 = dwarf_gpr_x5,
dwarf_gpr_t1 = dwarf_gpr_x6,
dwarf_gpr_t2 = dwarf_gpr_x7,
dwarf_gpr_fp = dwarf_gpr_x8, dwarf_gpr_fp = dwarf_gpr_x8,
dwarf_gpr_s1 = dwarf_gpr_x9,
dwarf_gpr_a0 = dwarf_gpr_x10,
dwarf_gpr_a1 = dwarf_gpr_x11,
dwarf_gpr_a2 = dwarf_gpr_x12,
dwarf_gpr_a3 = dwarf_gpr_x13,
dwarf_gpr_a4 = dwarf_gpr_x14,
dwarf_gpr_a5 = dwarf_gpr_x15,
dwarf_gpr_a6 = dwarf_gpr_x16,
dwarf_gpr_a7 = dwarf_gpr_x17,
dwarf_gpr_s2 = dwarf_gpr_x18,
dwarf_gpr_s3 = dwarf_gpr_x19,
dwarf_gpr_s4 = dwarf_gpr_x20,
dwarf_gpr_s5 = dwarf_gpr_x21,
dwarf_gpr_s6 = dwarf_gpr_x22,
dwarf_gpr_s7 = dwarf_gpr_x23,
dwarf_gpr_s8 = dwarf_gpr_x24,
dwarf_gpr_s9 = dwarf_gpr_x25,
dwarf_gpr_s10 = dwarf_gpr_x26,
dwarf_gpr_s11 = dwarf_gpr_x27,
dwarf_gpr_t3 = dwarf_gpr_x28,
dwarf_gpr_t4 = dwarf_gpr_x29,
dwarf_gpr_t5 = dwarf_gpr_x30,
dwarf_gpr_t6 = dwarf_gpr_x31,
// mock pc regnum // mock pc regnum
dwarf_gpr_pc = 11451, dwarf_gpr_pc = 11451,
}; };
} // namespace riscv_dwarf } // namespace riscv_dwarf
#endif // LLDB_SOURCE_UTILITY_RISCV_DWARF_REGISTERS_H #endif // LLDB_SOURCE_UTILITY_RISCV_DWARF_REGISTERS_H