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[LoongArch] Add support for the BranchRelaxation pass
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Authored by XiaodongLoong on Nov 2 2022, 1:22 AM.

Details

Summary

When the branch target is out of the range represented by the current
branch instruction's immediate, branch relaxation is required. There
are three types of immediate for branch instructions on LoongArch,
including simm16, simm21 and simm26. And the real branch target
address is PC + sext(simmXX << 2). In addition, the indirect branch
way is implemented to support larger branch target.

BranchRelaxation pass calls RenumberBlocks to renumber all of the
machine basic blocks in the function. So the machine basic blocks
number changed in some test cases.

Diff Detail

Event Timeline

XiaodongLoong created this revision.Nov 2 2022, 1:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 2 2022, 1:22 AM
XiaodongLoong requested review of this revision.Nov 2 2022, 1:22 AM
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arsenm added inline comments.Nov 2 2022, 4:17 PM
llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
267

MC can handle relaxing these different immediate offset types; you probably only want to handle the > 28 bit case here (and even then there may be a better way to deal with it which I don't know about it, if you have dedicated registers for it)

About the title, you'd better to add a [LoongArch] prefix.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
379

How about when assert = off? Will generate wrong code if Scav == LoongArch::NoRegister?

XiaodongLoong retitled this revision from Add support for the BranchRelaxation pass to [LoongArch] Add support for the BranchRelaxation pass.Nov 2 2022, 6:22 PM
XiaodongLoong added inline comments.Nov 2 2022, 7:20 PM
llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
267

MC can handle relaxing these different immediate offset types; you probably only want to handle the > 28 bit case here (and even then there may be a better way to deal with it which I don't know about it, if you have dedicated registers for it)

The BranchRelaxation pass could handle both condition branch and uncondition branch after I read the code. And I also read the patch from RISCV https://reviews.llvm.org/D40830. I think it might be OK to handle branch relaxing here on LoongArch. As far as I can see, there is no dedicated registers on LoongArch.
Thanks!

379

How about when assert = off? Will generate wrong code if Scav == LoongArch::NoRegister?

I will handle the condition in other patch. Thanks!

XiaodongLoong removed a subscriber: StephenFan.
StephenFan added inline comments.Nov 4 2022, 12:23 AM
llvm/test/CodeGen/LoongArch/branch-relaxation.ll
3

Is it possible to use -filetype=null if the output is not needed?

XiaodongLoong marked an inline comment as done.Nov 4 2022, 3:12 AM
XiaodongLoong added inline comments.
llvm/test/CodeGen/LoongArch/branch-relaxation.ll
3

Is it possible to use -filetype=null if the output is not needed?

Sorry, it is not possible to use -filetype=null.
When I use -filetype=null, I can not reproduce the errors I want to fix showed as following:

<unknown>:0: error: fixup value out of range [-131072, 131071]
<unknown>:0: error: fixup value out of range [-4194304, 4194303]
<unknown>:0: error: fixup value out of range [-4194304, 4194303]
SixWeining accepted this revision.Nov 6 2022, 7:21 PM

LGTM except a small nit.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
160

We can directly use MI.getOpcode() here (at least for now).

This revision is now accepted and ready to land.Nov 6 2022, 7:21 PM
XiaodongLoong marked an inline comment as done.

rebase code and fix nits.

XiaodongLoong added inline comments.Nov 6 2022, 7:55 PM
llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
160

Thanks! I changed it.