[AMDGPU] Enable `update/mov.dpp` selection with `+dpp`

[Pierre-vh]

Summary

ROCm device libs can emit those intrinsics w/ the +dpp attribute, and it counts on the optimizer to remove the call if the GPU is too old.
When built at O0 it caused codegen issues as Clang allowed this intrinsic to go through with just +dpp, but the backend wanted the GPU to be >=GFX8 as well.

This patch allows selecting that intrinsic with just +dpp

Depends on D136945

[foad]

Typo "gfx10" in title.

Why do you need +dpp as well as +gfx8-insts? Doesn't +gfx8-insts kind of imply +dpp already?

[Pierre-vh]

In D136946#3891728, @foad wrote:

Typo "gfx10" in title.

Why do you need +dpp as well as +gfx8-insts? Doesn't +gfx8-insts kind of imply +dpp already?

I'm not sure - I used both to be safe because the intrinsic is dpp specific. If everyone agrees we just need gfx8-insts then sure I'll remove the need for DPP.
Though, the change in pseudoToMCOpcode will still need to be DPP-specific because if I only check for GFX8-insts, it creates a mess (about 90 tests failures + various crashes). It seems like it needs to return -1 in some cases so I did a very targeted fix there (which I don't really like, if there's a better option I'd love to do something else really)

[foad]

Though, the change in pseudoToMCOpcode will still need to be DPP-specific because if I only check for GFX8-insts, it creates a mess (about 90 tests failures + various crashes). It seems like it needs to return -1 in some cases so I did a very targeted fix there (which I don't really like, if there's a better option I'd love to do something else really)

I think most of those extra cases in pseudoToMCOpcode should be conditional on MCOp == (uint16_t)-1, i.e. only try them if we have so far failed to find an MC opcode. Does that help?

[arsenm]

I think we're underutilizing implied features. I do think HasDPP should be sufficient. If you're running into further trouble, I'd guess it's from generation encoding changes

[Pierre-vh]

Only use hasDPP

[Pierre-vh]

Removing from review queue until we decide whether it's the way to go

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (DppCt) {
     }
     if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 &&
         ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
       ErrInfo = "Invalid dpp_ctrl value: "
                 "broadcasts are not supported on GFX10+";
       return false;
     }
     if (DC >= DppCtrl::ROW_SHARE_FIRST && DC <= DppCtrl::ROW_XMASK_LAST &&
-        ST.getGeneration() < AMDGPUSubtarget::GFX10) {
+        !ST.hasGFX10Insts()) {
       if (DC >= DppCtrl::ROW_NEWBCAST_FIRST &&
           DC <= DppCtrl::ROW_NEWBCAST_LAST &&
           !ST.hasGFX90AInsts()) {
         ErrInfo = "Invalid dpp_ctrl value: "
                   "row_newbroadcast/row_share is not supported before "
                   "GFX90A/GFX10";
         return false;
       } else if (DC > DppCtrl::ROW_NEWBCAST_LAST || !ST.hasGFX90AInsts()) {
int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
   }
 
   int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
 
   // -1 means that Opcode is already a native instruction.
   if (MCOp == -1)
     return Opcode;
 
+  if (ST.hasDPP() && get(Opcode).TSFlags & SIInstrFlags::DPP) {
+    uint16_t NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::VI);
+    if (NMCOp != (uint16_t)-1)
+      MCOp = NMCOp;
+  }
+
   if (ST.hasGFX90AInsts()) {
     uint16_t NMCOp = (uint16_t)-1;
     if (ST.hasGFX940Insts())
       NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX940);
     if (NMCOp == (uint16_t)-1)
       NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX90A);
     if (NMCOp == (uint16_t)-1)
       NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX9);

llvm/lib/Target/AMDGPU/VOP1Instructions.td

 def V_MOV_B32_indirect_read : VPseudoInstSI<
   (outs getVALUDstForVT<i32>.ret:$vdst),
   (ins getVOPSrc0ForVT<i32, 0>.ret:$src0)>,
   PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
                                         getVOPSrc0ForVT<i32, 0>.ret:$src0)>;
 
 } // End VOP1 = 1, SubtargetPredicate = isGFX8GFX9, Uses = [M0]
 
-let OtherPredicates = [isGFX8Plus] in {
+let OtherPredicates = [HasDPP] in {
 
 def : GCNPat <
   (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask,
                            timm:$bank_mask, timm:$bound_ctrl)),
   (V_MOV_B32_dpp VGPR_32:$src, VGPR_32:$src, (as_i32timm $dpp_ctrl),
                        (as_i32timm $row_mask), (as_i32timm $bank_mask),
                        (as_i1timm $bound_ctrl))
 >;
 
 def : GCNPat <
   (i32 (int_amdgcn_update_dpp i32:$old, i32:$src, timm:$dpp_ctrl,
                               timm:$row_mask, timm:$bank_mask,
                               timm:$bound_ctrl)),
   (V_MOV_B32_dpp VGPR_32:$old, VGPR_32:$src, (as_i32timm $dpp_ctrl),
                  (as_i32timm $row_mask), (as_i32timm $bank_mask),
                  (as_i1timm $bound_ctrl))
 >;
 
-} // End OtherPredicates = [isGFX8Plus]
+} // End OtherPredicates = [HasDPP]
 
 let OtherPredicates = [isGFX8Plus] in {
 def : GCNPat<
   (i32 (anyext i16:$src)),
   (COPY $src)
 >;
 
 def : GCNPat<

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -mattr=+dpp -verify-machineinstrs < %s | FileCheck -check-prefix=PREGFX8 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX11 %s
 
+; Note: the Hawaii +dpp run line is to check that we can select this instruction
+; only using the attribute, without needing an actual >=GFX8 GPU.
+
 ; FIXME: Merge with DAG test
 
 define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
+; PREGFX8-LABEL: dpp_test:
+; PREGFX8:       ; %bb.0:
+; PREGFX8-NEXT:    s_load_dword s3, s[0:1], 0xb
+; PREGFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; PREGFX8-NEXT:    s_mov_b32 s2, -1
+; PREGFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; PREGFX8-NEXT:    v_mov_b32_e32 v0, s3
+; PREGFX8-NEXT:    s_nop 1
+; PREGFX8-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
+; PREGFX8-NEXT:    s_mov_b32 s3, 0xf000
+; PREGFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; PREGFX8-NEXT:    s_endpgm
+;
 ; GFX8-LABEL: dpp_test:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dword s2, s[0:1], 0x2c
 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s2
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    s_nop 0

 ; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1] ; encoding: [0x00,0x00,0x6a,0xdc,0x01,0x00,0x00,0x00]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; encoding: [0x03,0x00,0xb6,0xbf]
 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
   %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 define amdgpu_kernel void @mov_dpp64_test(i64 addrspace(1)* %out, i64 %in1) {
+; PREGFX8-LABEL: mov_dpp64_test:
+; PREGFX8:       ; %bb.0:
+; PREGFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; PREGFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; PREGFX8-NEXT:    v_mov_b32_e32 v0, s2
+; PREGFX8-NEXT:    v_mov_b32_e32 v1, s3
+; PREGFX8-NEXT:    v_mov_b32_e32 v3, s1
+; PREGFX8-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
+; PREGFX8-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
+; PREGFX8-NEXT:    v_mov_b32_e32 v2, s0
+; PREGFX8-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; PREGFX8-NEXT:    s_endpgm
+;
 ; GFX8-LABEL: mov_dpp64_test:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX8-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX8-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -mattr=+dpp -verify-machineinstrs < %s | FileCheck -check-prefix=PREGFX8 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
 
+; Note: the Hawaii +dpp run line is to check that we can select this instruction
+; only using the attribute, without needing an actual >=GFX8 GPU.
+
 define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
+; PREGFX8-LABEL: dpp_test:
+; PREGFX8:       ; %bb.0:
+; PREGFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; PREGFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; PREGFX8-NEXT:    v_mov_b32_e32 v0, s2
+; PREGFX8-NEXT:    v_mov_b32_e32 v1, s3
+; PREGFX8-NEXT:    s_mov_b32 s2, -1
+; PREGFX8-NEXT:    s_mov_b32 s3, 0xf000
+; PREGFX8-NEXT:    v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
+; PREGFX8-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; PREGFX8-NEXT:    s_endpgm
+;
 ; GFX8-LABEL: dpp_test:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s2
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s3
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1

 ; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
   %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false)
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 define amdgpu_kernel void @update_dpp64_test(i64 addrspace(1)* %arg, i64 %in1, i64 %in2) {
+; PREGFX8-LABEL: update_dpp64_test:
+; PREGFX8:       ; %bb.0:
+; PREGFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; PREGFX8-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; PREGFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; PREGFX8-NEXT:    v_mov_b32_e32 v0, s0
+; PREGFX8-NEXT:    v_mov_b32_e32 v1, s1
+; PREGFX8-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; PREGFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; PREGFX8-NEXT:    flat_load_dwordx2 v[2:3], v[0:1]
+; PREGFX8-NEXT:    v_mov_b32_e32 v5, s3
+; PREGFX8-NEXT:    v_mov_b32_e32 v4, s2
+; PREGFX8-NEXT:    s_waitcnt vmcnt(0)
+; PREGFX8-NEXT:    v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
+; PREGFX8-NEXT:    v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
+; PREGFX8-NEXT:    flat_store_dwordx2 v[0:1], v[4:5]
+; PREGFX8-NEXT:    s_endpgm
+;
 ; GFX8-LABEL: update_dpp64_test:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll

+; RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+dpp,-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT,PREGFX10,PREGFX10-OPT %s
+; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -mattr=+dpp,-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-NOOPT,PREGFX10,PREGFX10-NOOPT %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT,PREGFX10,PREGFX10-OPT %s
 ; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-NOOPT,PREGFX10,PREGFX10-NOOPT %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -amdgpu-enable-vopd=0 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s
 
+; Note: the Hawaii +dpp run line is to check that we can select this instruction
+; only using the attribute, without needing an actual >=GFX8 GPU.
+
 ; FIXME: The register allocator / scheduler should be able to avoid these hazards.
 
 ; VI-LABEL: {{^}}dpp_test:
 ; VI: v_mov_b32_e32 v0, s{{[0-9]+}}
 ; VI-NOOPT: v_mov_b32_e32 v1, s{{[0-9]+}}
 ; PREGFX10: s_nop 1
 ; VI-OPT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
 ; VI-NOOPT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11]

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll

+; RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+dpp,-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-OPT,GCN-OPT %s
+; RUN: llc -march=amdgcn -mcpu=hawaii -O0 -mattr=+dpp,-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-NOOPT %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-OPT,GCN-OPT %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -O0 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-NOOPT %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GCN-OPT %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -amdgpu-enable-vopd=0 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX11,GCN-OPT %s
 
+; Note: the Hawaii +dpp run line is to check that we can select this instruction
+; only using the attribute, without needing an actual >=GFX8 GPU.
+
 ; GCN-LABEL: {{^}}dpp_test:
 ; GCN:  v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}}
 ; GCN:  v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
 ; GFX8-OPT: s_mov
 ; GFX8-OPT: s_mov
 ; GFX8-NOOPT: s_nop 1
 ; GCN:  v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
 define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
define amdgpu_kernel void @dpp_test_bc(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
   %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 2, i32 1, i32 1, i1 1) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 
 ; GCN-LABEL: {{^}}dpp_test1:
 ; GFX10,GFX11: v_add_nc_u32_e32 [[REG:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
-; GFX8-OPT: v_add_u32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}
-; GFX8-NOOPT: v_add_u32_e64 [[REG:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX8-OPT: v_add_{{u|i}}32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX8-NOOPT: v_add_{{u|i}}32_e64 [[REG:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; GFX8-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0
 ; GFX8: s_nop 1
 ; GFX8-NEXT: v_mov_b32_dpp {{v[0-9]+}}, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
 @0 = internal unnamed_addr addrspace(3) global [448 x i32] undef, align 4
 define weak_odr amdgpu_kernel void @dpp_test1(i32* %arg) local_unnamed_addr {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp1 = zext i32 %tmp to i64