This is an archive of the discontinued LLVM Phabricator instance.

Differential D136459

[AMDGPU] Use VGPR classes in divergent build_vector patterns
ClosedPublic

Authored by foad on Oct 21 2022, 8:44 AM.

Details

Reviewers
arsenm
Pierre-vh
Group Reviewers
Restricted Project
Commits
rG31bd3e6e92e6: [AMDGPU] Use VGPR classes in divergent build_vector patterns
Summary

This does not appear to affect codegen, but using SGPR classes for
operands of VALU instructions looked weird.

Diff Detail

Event Timeline

foad created this revision.Oct 21 2022, 8:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 21 2022, 8:44 AM
Herald added subscribers: kosarev, kerbowa, hiraditya and 6 others. · View Herald Transcript
foad requested review of this revision.Oct 21 2022, 8:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 21 2022, 8:44 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
arsenm accepted this revision.Oct 21 2022, 8:54 AM
This revision is now accepted and ready to land.Oct 21 2022, 8:54 AM
This revision was landed with ongoing or failed builds.Oct 21 2022, 8:57 AM
Closed by commit rG31bd3e6e92e6: [AMDGPU] Use VGPR classes in divergent build_vector patterns (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rG31bd3e6e92e6: [AMDGPU] Use VGPR classes in divergent build_vector patterns.
Harbormaster completed remote builds in B193542: Diff 469633.Oct 21 2022, 9:36 AM
Pierre-vh mentioned this in D136236: [AMDGPU][GISel] Allow VReg srcs in (build_vector undef, i16) pattern.Nov 6 2022, 11:53 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
22 lines

Diff 469640

llvm/lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 2,685 Lines • ▼ Show 20 Lines
// from S_LSHL_B32's multiple outputs from implicit scc def. // from S_LSHL_B32's multiple outputs from implicit scc def.
let AddedComplexity = 1 in { let AddedComplexity = 1 in {
def : GCNPat < def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 0), (i16 SReg_32:$src1))), (v2i16 (UniformBinFrag<build_vector> (i16 0), (i16 SReg_32:$src1))),
(S_LSHL_B32 SReg_32:$src1, (i16 16)) (S_LSHL_B32 SReg_32:$src1, (i16 16))
>; >;
def : GCNPat < def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 0), (i16 SReg_32:$src1))), (v2i16 (DivergentBinFrag<build_vector> (i16 0), (i16 VGPR_32:$src1))),
(v2i16 (V_LSHLREV_B32_e64 (i16 16), SReg_32:$src1)) (v2i16 (V_LSHLREV_B32_e64 (i16 16), VGPR_32:$src1))
>; >;
def : GCNPat < def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src1), (i16 0))), (v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src1), (i16 0))),
(S_AND_B32 (S_MOV_B32 (i32 0xffff)), SReg_32:$src1) (S_AND_B32 (S_MOV_B32 (i32 0xffff)), SReg_32:$src1)
>; >;
def : GCNPat < def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 SReg_32:$src1), (i16 0))), (v2i16 (DivergentBinFrag<build_vector> (i16 VGPR_32:$src1), (i16 0))),
(v2i16 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), SReg_32:$src1)) (v2i16 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), VGPR_32:$src1))
>; >;
def : GCNPat < def : GCNPat <
(v2f16 (UniformBinFrag<build_vector> (f16 SReg_32:$src1), (f16 FP_ZERO))), (v2f16 (UniformBinFrag<build_vector> (f16 SReg_32:$src1), (f16 FP_ZERO))),
(S_AND_B32 (S_MOV_B32 (i32 0xffff)), SReg_32:$src1) (S_AND_B32 (S_MOV_B32 (i32 0xffff)), SReg_32:$src1)
>; >;
def : GCNPat < def : GCNPat <
(v2f16 (DivergentBinFrag<build_vector> (f16 SReg_32:$src1), (f16 FP_ZERO))), (v2f16 (DivergentBinFrag<build_vector> (f16 VGPR_32:$src1), (f16 FP_ZERO))),
(v2f16 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), SReg_32:$src1)) (v2f16 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), VGPR_32:$src1))
>; >;
def : GCNPat < def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 undef))), (v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 undef))),
(COPY_TO_REGCLASS SReg_32:$src0, SReg_32) (COPY_TO_REGCLASS SReg_32:$src0, SReg_32)
>; >;
def : GCNPat < def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 VGPR_32:$src0), (i16 undef))), (v2i16 (DivergentBinFrag<build_vector> (i16 VGPR_32:$src0), (i16 undef))),
(COPY_TO_REGCLASS VGPR_32:$src0, VGPR_32) (COPY_TO_REGCLASS VGPR_32:$src0, VGPR_32)
>; >;
def : GCNPat < def : GCNPat <
(v2f16 (build_vector f16:$src0, (f16 undef))), (v2f16 (build_vector f16:$src0, (f16 undef))),
(COPY $src0) (COPY $src0)
>; >;
def : GCNPat < def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))), (v2i16 (UniformBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))),
(S_LSHL_B32 SReg_32:$src1, (i32 16)) (S_LSHL_B32 SReg_32:$src1, (i32 16))
>; >;
def : GCNPat < def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))), (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 VGPR_32:$src1))),
(v2i16 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1)) (v2i16 (V_LSHLREV_B32_e64 (i32 16), VGPR_32:$src1))
>; >;
def : GCNPat < def : GCNPat <
(v2f16 (UniformBinFrag<build_vector> (f16 undef), (f16 SReg_32:$src1))), (v2f16 (UniformBinFrag<build_vector> (f16 undef), (f16 SReg_32:$src1))),
(S_LSHL_B32 SReg_32:$src1, (i32 16)) (S_LSHL_B32 SReg_32:$src1, (i32 16))
>; >;
def : GCNPat < def : GCNPat <
(v2f16 (DivergentBinFrag<build_vector> (f16 undef), (f16 SReg_32:$src1))), (v2f16 (DivergentBinFrag<build_vector> (f16 undef), (f16 VGPR_32:$src1))),
(v2f16 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1)) (v2f16 (V_LSHLREV_B32_e64 (i32 16), VGPR_32:$src1))
>; >;
} }
let SubtargetPredicate = HasVOP3PInsts in { let SubtargetPredicate = HasVOP3PInsts in {
def : GCNPat < def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 SReg_32:$src1))), (v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 SReg_32:$src1))),
(S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1) (S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
>; >;
def : GCNPat < def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 SReg_32:$src0), (i16 SReg_32:$src1))), (v2i16 (DivergentBinFrag<build_vector> (i16 VGPR_32:$src0), (i16 VGPR_32:$src1))),
(v2i16 (V_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0)))) (v2i16 (V_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
>; >;
// With multiple uses of the shift, this will duplicate the shift and // With multiple uses of the shift, this will duplicate the shift and
// increase register pressure. // increase register pressure.
def : GCNPat < def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 (trunc (srl_oneuse SReg_32:$src1, (i32 16)))))), (v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 (trunc (srl_oneuse SReg_32:$src1, (i32 16)))))),
(v2i16 (S_PACK_LH_B32_B16 SReg_32:$src0, SReg_32:$src1)) (v2i16 (S_PACK_LH_B32_B16 SReg_32:$src0, SReg_32:$src1))
▲ Show 20 Lines • Show All 700 Lines • Show Last 20 Lines