[AMDGPU][GISel] Constrain selected operands in selectG_BUILD_VECTOR

[Pierre-vh]

Summary

Small bugfix. Currently harmless but a case in D134354 triggers it.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

692

Should be able to get away with just src0

[Pierre-vh]

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

692

Do you mean calling constrainOperandRegClass directly?
If possible I'd rather keep constrainSelectedInstRegOperands. We're doing the same operation in both cases (we want the operands to be constrained to the instruction's desired RB) and I feel like it's easier to follow if we just use the same function in both cases

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

const auto &RC =
         IsVector ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass;
     return RBI.constrainGenericRegister(Dst, RC, *MRI) &&
            RBI.constrainGenericRegister(Src0, RC, *MRI);
   }
 
   // TODO: Can be improved?
   if (IsVector) {
     Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
-    BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg)
+    auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg)
                    .addImm(0xFFFF)
                    .addReg(Src0);
-    BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst)
+    if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
+      return false;
+
+    MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst)
               .addReg(Src1)
               .addImm(16)
               .addReg(TmpReg);
+    if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
+      return false;
+
     MI.eraseFromParent();
     return true;
   }
 
   Register ShiftSrc0;
   Register ShiftSrc1;
 
   // With multiple uses of the shift, this will duplicate the shift and