[LoongArch] Fix codegen of atomicrmw nand

[lrzlin]

Summary

Fix invalid RISCV-like MI being emitted for performing the not operation: the LoongArch xori zero-extends the immediate, hence is not equivalent to RISCV xori. The LoongArch not is a nor with zero.

[xen0n]

Thanks for the catch! Maybe we've read too much RISCV assembly to notice this. /facepalms

BTW I've edited the patch title and summary for you. Please check if I did it right.

[gonglingqin]

Thanks！

[SixWeining]

LGTM. Thanks.

[SixWeining]

update test case

llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp

case AtomicRMWInst::Xchg:
     BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg)
         .addReg(IncrReg)
         .addReg(LoongArch::R0);
     break;
   case AtomicRMWInst::Nand:
     BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg)
         .addReg(DestReg)
         .addReg(IncrReg);
-    BuildMI(LoopMBB, DL, TII->get(LoongArch::XORI), ScratchReg)
+    BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg)
         .addReg(ScratchReg)
-        .addImm(-1);
+        .addReg(LoongArch::R0);
     break;
   case AtomicRMWInst::Add:
     BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg)
         .addReg(DestReg)
         .addReg(IncrReg);
     break;
   case AtomicRMWInst::Sub:
     BuildMI(LoopMBB, DL, TII->get(LoongArch::SUB_W), ScratchReg)
case AtomicRMWInst::Sub:
     BuildMI(LoopMBB, DL, TII->get(LoongArch::SUB_W), ScratchReg)
         .addReg(DestReg)
         .addReg(IncrReg);
     break;
   case AtomicRMWInst::Nand:
     BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg)
         .addReg(DestReg)
         .addReg(IncrReg);
-    BuildMI(LoopMBB, DL, TII->get(LoongArch::XORI), ScratchReg)
+    BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg)
         .addReg(ScratchReg)
-        .addImm(-1);
+        .addReg(LoongArch::R0);
     // TODO: support other AtomicRMWInst.
   }
 
   insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg,
                     ScratchReg);
 
   BuildMI(LoopMBB, DL, TII->get(LoongArch::SC_W), ScratchReg)
       .addReg(ScratchReg)

llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll

 ; LA32-NEXT:    ori $a3, $zero, 255
 ; LA32-NEXT:    sll.w $a3, $a3, $a0
 ; LA32-NEXT:    andi $a1, $a1, 255
 ; LA32-NEXT:    sll.w $a1, $a1, $a0
 ; LA32-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a4, $a2, 0
 ; LA32-NEXT:    and $a5, $a4, $a1
-; LA32-NEXT:    xori $a5, $a5, -1
+; LA32-NEXT:    nor $a5, $a5, $zero
 ; LA32-NEXT:    xor $a5, $a4, $a5
 ; LA32-NEXT:    and $a5, $a5, $a3
 ; LA32-NEXT:    xor $a5, $a4, $a5
 ; LA32-NEXT:    sc.w $a5, $a2, 0
 ; LA32-NEXT:    beqz $a5, .LBB12_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    srl.w $a0, $a4, $a0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_nand_i8_acquire:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a2, $zero, -4
 ; LA64-NEXT:    and $a2, $a0, $a2
 ; LA64-NEXT:    slli.d $a0, $a0, 3
 ; LA64-NEXT:    ori $a3, $zero, 255
 ; LA64-NEXT:    sll.w $a3, $a3, $a0
 ; LA64-NEXT:    addi.w $a3, $a3, 0
 ; LA64-NEXT:    andi $a1, $a1, 255
 ; LA64-NEXT:    sll.w $a1, $a1, $a0
 ; LA64-NEXT:    addi.w $a1, $a1, 0
 ; LA64-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a4, $a2, 0
 ; LA64-NEXT:    and $a5, $a4, $a1
-; LA64-NEXT:    xori $a5, $a5, -1
+; LA64-NEXT:    nor $a5, $a5, $zero
 ; LA64-NEXT:    xor $a5, $a4, $a5
 ; LA64-NEXT:    and $a5, $a5, $a3
 ; LA64-NEXT:    xor $a5, $a4, $a5
 ; LA64-NEXT:    sc.w $a5, $a2, 0
 ; LA64-NEXT:    beqz $a5, .LBB12_1
 ; LA64-NEXT:  # %bb.2:
 ; LA64-NEXT:    srl.w $a0, $a4, $a0
 ; LA64-NEXT:    ret

 ; LA32-NEXT:    ori $a3, $a3, 4095
 ; LA32-NEXT:    sll.w $a3, $a3, $a0
 ; LA32-NEXT:    bstrpick.w $a1, $a1, 15, 0
 ; LA32-NEXT:    sll.w $a1, $a1, $a0
 ; LA32-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a4, $a2, 0
 ; LA32-NEXT:    and $a5, $a4, $a1
-; LA32-NEXT:    xori $a5, $a5, -1
+; LA32-NEXT:    nor $a5, $a5, $zero
 ; LA32-NEXT:    xor $a5, $a4, $a5
 ; LA32-NEXT:    and $a5, $a5, $a3
 ; LA32-NEXT:    xor $a5, $a4, $a5
 ; LA32-NEXT:    sc.w $a5, $a2, 0
 ; LA32-NEXT:    beqz $a5, .LBB13_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    srl.w $a0, $a4, $a0
 ; LA32-NEXT:    ret

 ; LA64-NEXT:    addi.w $a3, $a3, 0
 ; LA64-NEXT:    bstrpick.d $a1, $a1, 15, 0
 ; LA64-NEXT:    sll.w $a1, $a1, $a0
 ; LA64-NEXT:    addi.w $a1, $a1, 0
 ; LA64-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a4, $a2, 0
 ; LA64-NEXT:    and $a5, $a4, $a1
-; LA64-NEXT:    xori $a5, $a5, -1
+; LA64-NEXT:    nor $a5, $a5, $zero
 ; LA64-NEXT:    xor $a5, $a4, $a5
 ; LA64-NEXT:    and $a5, $a5, $a3
 ; LA64-NEXT:    xor $a5, $a4, $a5
 ; LA64-NEXT:    sc.w $a5, $a2, 0
 ; LA64-NEXT:    beqz $a5, .LBB13_1
 ; LA64-NEXT:  # %bb.2:
 ; LA64-NEXT:    srl.w $a0, $a4, $a0
 ; LA64-NEXT:    ret
   %1 = atomicrmw nand ptr %a, i16 %b acquire
   ret i16 %1
 }
 
 define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
 ; LA32-LABEL: atomicrmw_nand_i32_acquire:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
 ; LA32-NEXT:    dbar 0
 ; LA32-NEXT:    ll.w $a2, $a1, 0
 ; LA32-NEXT:    and $a3, $a2, $a0
-; LA32-NEXT:    xori $a3, $a3, -1
+; LA32-NEXT:    nor $a3, $a3, $zero
 ; LA32-NEXT:    sc.w $a3, $a1, 0
 ; LA32-NEXT:    beqz $a3, .LBB14_1
 ; LA32-NEXT:  # %bb.2:
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_nand_i32_acquire:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.w $a2, $a1, 0
 ; LA64-NEXT:    and $a3, $a2, $a0
-; LA64-NEXT:    xori $a3, $a3, -1
+; LA64-NEXT:    nor $a3, $a3, $zero
 ; LA64-NEXT:    sc.w $a3, $a1, 0
 ; LA64-NEXT:    beqz $a3, .LBB14_1
 ; LA64-NEXT:  # %bb.2:
 ; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw nand ptr %a, i32 %b acquire
   ret i32 %1
 }

 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: atomicrmw_nand_i64_acquire:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    ll.d $a2, $a1, 0
 ; LA64-NEXT:    and $a3, $a2, $a0
-; LA64-NEXT:    xori $a3, $a3, -1
+; LA64-NEXT:    nor $a3, $a3, $zero
 ; LA64-NEXT:    sc.d $a3, $a1, 0
 ; LA64-NEXT:    beqz $a3, .LBB15_1
 ; LA64-NEXT:  # %bb.2:
 ; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %1 = atomicrmw nand ptr %a, i64 %b acquire
   ret i64 %1
 }