[AMDGPU][MC][GFX8+] Correct v_cndmask modifiers

[dp]

Summary

Correct v_cndmask_b32 to support abs/neg modifiers in dpp/sdwa/e64 variants.
Correct v_cndmask_b16 for proper disassembly of abs/neg modifiers in e64_dpp variants.

See this bug for more information.

[rampitec]

LGTM

[Joe_Nash]

I guess CNDMASK_B16 should be a True16 instruction. I shall plan to do that. With that in mind, this patch appears even less parameterized for (i32 vs i16) input types than before. Is there any way to get some of that back? IE before this patch CNDMASK_B16_T16 wouldn't need to override InsDPP, but after this it does.

[dp]

In D135900#3856534, @Joe_Nash wrote:

I guess CNDMASK_B16 should be a True16 instruction. I shall plan to do that. With that in mind, this patch appears even less parameterized for (i32 vs i16) input types than before. Is there any way to get some of that back? IE before this patch CNDMASK_B16_T16 wouldn't need to override InsDPP, but after this it does.

I assume that True16 instructions may use first 128 VGPRs only. v_cndmask_b16 is a native VOP3 instruction, it does not have such limitations. Also, it has no e32_dpp variant, so I do not understand why InsDPP may need a correction. What am I missing here?

[Joe_Nash]

In D135900#3858246, @dp wrote:

In D135900#3856534, @Joe_Nash wrote:

I guess CNDMASK_B16 should be a True16 instruction. I shall plan to do that. With that in mind, this patch appears even less parameterized for (i32 vs i16) input types than before. Is there any way to get some of that back? IE before this patch CNDMASK_B16_T16 wouldn't need to override InsDPP, but after this it does.

I assume that True16 instructions may use first 128 VGPRs only. v_cndmask_b16 is a native VOP3 instruction, it does not have such limitations. Also, it has no e32_dpp variant, so I do not understand why InsDPP may need a correction. What am I missing here?

Ok, sorry, I missed the fact that v_cndmask_b16 is a native VOP3 instruction. LGTM!

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
   // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
   switch (MI->getOpcode()) {
   default: break;
 
   case AMDGPU::V_CNDMASK_B32_e32_gfx10:
   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
-  case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
   case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
   case AMDGPU::V_CNDMASK_B32_e32_gfx11:
   case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
   case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
   case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
-  case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
   case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
   case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
   case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
   case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
   case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
   case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
   case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
 
if (InputModifiers & SISrcMods::ABS)
     O << '|';
   printRegularOperand(MI, OpNo + 1, STI, O);
   if (InputModifiers & SISrcMods::ABS)
     O << '|';
 
   if (NegMnemo) {
     O << ')';
   }
+
+  // Print default vcc/vcc_lo operand of VOP2b.
+  switch (MI->getOpcode()) {
+  default:
+    break;
+
+  case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
+  case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
+  case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
+    if ((int)OpNo + 1 ==
+        AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1))
+      printDefaultVccOperand(OpNo == 0, STI, O);
+    break;
+  }
 }
 
 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
                                                     unsigned OpNo,
                                                     const MCSubtargetInfo &STI,
                                                     raw_ostream &O) {
   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
   if (needsImpliedVcc(Desc, OpNo))
     printDefaultVccOperand(true, STI, O);
 
   unsigned InputModifiers = MI->getOperand(OpNo).getImm();
   if (InputModifiers & SISrcMods::SEXT)
     O << "sext(";
   printRegularOperand(MI, OpNo + 1, STI, O);
   if (InputModifiers & SISrcMods::SEXT)
     O << ')';
 
   // Print default vcc/vcc_lo operand of VOP2b.
   switch (MI->getOpcode()) {
   default: break;
 
-  case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
   case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
   case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
   case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
     if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
                                                     AMDGPU::OpName::src1))
       printDefaultVccOperand(OpNo == 0, STI, O);
     break;
   }

llvm/lib/Target/AMDGPU/VOP2Instructions.td

 }
 
 // Read in from vcc or arbitrary SGPR.
 class VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT, /*EnableF32SrcMods=*/1> {
   let Asm32 = "$vdst, $src0, $src1";
   let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
   let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
   let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
-  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
+  let AsmDPP = "$vdst, $src0_modifiers, $src1_modifiers, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
   let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
   let AsmDPP16 = AsmDPP#"$fi";
   let AsmVOP3DPPBase = Asm64;
 
   let Outs32 = (outs DstRC:$vdst);
   let Outs64 = (outs DstRC:$vdst);
 
   // Suppress src2 implied by type since the 32-bit encoding uses an
   // implicit VCC use.
   let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
 
-  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
-                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
+  let HasSrc0IntMods = 0;
+  let HasSrc1IntMods = 0;
+  let HasSrc0FloatMods = 1;
+  let HasSrc1FloatMods = 1;
+  let InsSDWA = (ins FP32SDWAInputMods:$src0_modifiers, Src0SDWA:$src0,
+                     FP32SDWAInputMods:$src1_modifiers, Src1SDWA:$src1,
                      clampmod:$clamp,
                      dst_sel:$dst_sel, dst_unused:$dst_unused,
                      src0_sel:$src0_sel, src1_sel:$src1_sel);
 
   let InsDPP = (ins DstRCDPP:$old,
-                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
-                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
+                    FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,
+                    FPVRegInputMods:$src1_modifiers, Src1DPP:$src1,
                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
   let InsDPP16 = !con(InsDPP, (ins FI:$fi));
   let InsDPP8 = (ins DstRCDPP:$old,
-                     Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
-                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
+                     FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,
+                     FPVRegInputMods:$src1_modifiers, Src1DPP:$src1,
                      dpp8:$dpp8, FI:$fi);
 
+  let Src0ModVOP3DPP = FPVRegInputMods;
+  let Src1ModVOP3DPP = FPVRegInputMods;
+
   let HasExt = 1;
   let HasExtDPP = 1;
   let HasExt32BitDPP = 1;
   let HasExtSDWA = 1;
   let HasExtSDWA9 = 1;
 }
 
 def VOP2e_I32_I32_I32_I1 : VOP2e_SGPR<[i32, i32, i32, i1]>;

llvm/test/MC/AMDGPU/gfx10_asm_vop2.s

 v_cndmask_b32_e64 v5, v1, v2, s[100:101]
 // W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x92,0x01]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_cndmask_b32_e64 v5, v1, v2, vcc
 // W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc
+// W64: encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc
+// W64: encoding: [0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x68,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf8,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cndmask_b32_e32 v5, v1, v2, vcc_lo
 // W32: encoding: [0x01,0x05,0x0a,0x02]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_cndmask_b32_e32 v255, v1, v2, vcc_lo
 // W32: encoding: [0x01,0x05,0xfe,0x03]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 

 v_cndmask_b32_e64 v5, v1, v2, s100
 // W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x92,0x01]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_cndmask_b32_e64 v5, v1, v2, vcc_lo
 // W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc_lo
+// W32: encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc_lo
+// W32: encoding: [0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_sdwa v5, -v1, |v2|, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_sdwa v5, |v1|, -v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_sdwa v5, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand
+
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand
+
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x68,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf8,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_add_f32_e32 v5, v1, v2
 // GFX10: encoding: [0x01,0x05,0x0a,0x06]
 
 v_add_f32_e32 v255, v1, v2
 // GFX10: encoding: [0x01,0x05,0xfe,0x07]
 
 v_add_f32_e32 v5, v255, v2
 // GFX10: encoding: [0xff,0x05,0x0a,0x06]

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 
 //==============================================================================
 // expected a 16-bit offset
 
 ds_swizzle_b32 v8, v2 offset:0x10000
 // CHECK: error: expected a 16-bit offset
 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:0x10000
 // CHECK-NEXT:{{^}}                             ^
+
+//==============================================================================
+// not a valid operand
+
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK: error: not a valid operand.
+// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK-NEXT:{{^}}                           ^

llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s

 v_cndmask_b32 v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
 // W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_cndmask_b32 v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 // W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32 v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x68,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32 v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf8,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cndmask_b32 v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // W32: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_cndmask_b32 v5, v1, v2, vcc quad_perm:[3,2,1,0]
 // W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 

 v_cndmask_b32 v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 // W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
 v_cndmask_b32 v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // W64: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x98,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x68,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf8,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
 v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0]
 // GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
 
 v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3]
 // GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff]
 
 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_mirror
 // GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff]

llvm/test/MC/AMDGPU/gfx7_asm_vop3.s

 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xb2,0x01]
 
 v_cndmask_b32_e64 v5, v1, v2, tma
 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xba,0x01]
 
 v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11]
 // CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xea,0x01]
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc
+// CHECK: encoding: [0x05,0x02,0x00,0xd2,0x01,0x05,0xaa,0x21]
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc
+// CHECK: encoding: [0x05,0x01,0x00,0xd2,0x01,0x05,0xaa,0x41]
+
+v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc
+// CHECK: encoding: [0x05,0x03,0x00,0xd2,0x01,0x05,0xaa,0x61]
+
 v_add_f32_e64 v5, v1, v2
 // CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x00]
 
 v_add_f32_e64 v255, v1, v2
 // CHECK: [0xff,0x00,0x06,0xd2,0x01,0x05,0x02,0x00]
 
 v_add_f32_e64 v5, v255, v2
 // CHECK: [0x05,0x00,0x06,0xd2,0xff,0x05,0x02,0x00]

llvm/test/MC/AMDGPU/gfx8_asm_vop2.s

 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x03,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x04,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x05,0x06]
 
-v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x0e,0x06]
+v_cndmask_b32_sdwa v5, |v1|, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x06]
+
+v_cndmask_b32_sdwa v5, -v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x00]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x01]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x02]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x03]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x04]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x05]
 
-v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
+v_cndmask_b32_sdwa v5, v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x26]
+
+v_cndmask_b32_sdwa v5, v1, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x16]
 
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
 
 v_cndmask_b32_dpp v255, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // CHECK: [0xfa,0x04,0xfe,0x01,0x01,0xe4,0x00,0x00]
 
 v_cndmask_b32_dpp v5, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0

 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
 
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
 
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x08,0x00]
 
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x98,0x00]
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x68,0x00]
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf8,0x00]
+
 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
 
 v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0xfe,0x03,0x01,0x06,0x06,0x06]
 
 v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x02,0xff,0x06,0x06,0x06]

llvm/test/MC/AMDGPU/gfx8_asm_vop3.s

 // CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xb2,0x01]
 
 v_cndmask_b32_e64 v5, v1, v2, tma
 // CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xba,0x01]
 
 v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11]
 // CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc
+// CHECK: encoding: [0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21]
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc
+// CHECK: encoding: [0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41]
+
+v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc
+// CHECK: encoding: [0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61]
+
 v_add_f32_e64 v5, v1, v2
 // CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 
 v_add_f32_e64 v255, v1, v2
 // CHECK: [0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 
 v_add_f32_e64 v5, v255, v2
 // CHECK: [0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00]

llvm/test/MC/AMDGPU/gfx8_err_pos.s

 
 //==============================================================================
 // image data size does not match dmask and tfe
 
 image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
 // CHECK: error: image data size does not match dmask and tfe
 // CHECK-NEXT:{{^}}image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
 // CHECK-NEXT:{{^}}^
+
+//==============================================================================
+// not a valid operand
+
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK: error: not a valid operand.
+// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK-NEXT:{{^}}                           ^

llvm/test/MC/AMDGPU/gfx9_asm_vop2.s

 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x03,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x04,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x05,0x06]
 
-v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x0e,0x06]
+v_cndmask_b32_sdwa v5, -v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x06]
+
+v_cndmask_b32_sdwa v5, |v1|, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x00]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x01]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x02]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x03]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x04]
 
 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x05]
 
-v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
+v_cndmask_b32_sdwa v5, v1, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x16]
+
+v_cndmask_b32_sdwa v5, v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x26]
 
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
 
 v_cndmask_b32_dpp v255, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // CHECK: [0xfa,0x04,0xfe,0x01,0x01,0xe4,0x00,0x00]
 
 v_cndmask_b32_dpp v5, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0

 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
 
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
 
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x08,0x00]
 
+v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x98,0x00]
+
+v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x68,0x00]
+
+v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf8,0x00]
+
 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
 
 v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0xfe,0x03,0x01,0x06,0x06,0x06]
 
 v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 // CHECK: [0xf9,0x04,0x0a,0x02,0xff,0x06,0x06,0x06]

llvm/test/MC/AMDGPU/gfx9_asm_vop3.s

 // CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x9a,0x01]
 
 v_cndmask_b32_e64 v5, v1, v2, vcc
 // CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01]
 
 v_cndmask_b32_e64 v5, v1, v2, ttmp[14:15]
 // CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
 
+v_cndmask_b32_e64 v5, -v1, |v2|, vcc
+// CHECK: encoding: [0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21]
+
+v_cndmask_b32_e64 v5, |v1|, -v2, vcc
+// CHECK: encoding: [0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41]
+
+v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc
+// CHECK: encoding: [0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61]
+
 v_add_f32_e64 v5, v1, v2
 // CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 
 v_add_f32_e64 v255, v1, v2
 // CHECK: [0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 
 v_add_f32_e64 v5, v255, v2
 // CHECK: [0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00]

llvm/test/MC/AMDGPU/gfx9_err_pos.s

 // duplicate format
 
 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], dfmt:1 s0 format:[BUF_NUM_FORMAT_FLOAT]
 // CHECK: error: duplicate format
 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], dfmt:1 s0 format:[BUF_NUM_FORMAT_FLOAT]
 // CHECK-NEXT:{{^}}                                                            ^
 
 //==============================================================================
+// not a valid operand
+
+v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK: error: not a valid operand.
+// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
+// CHECK-NEXT:{{^}}                       ^
+
+//==============================================================================
 // out of range dfmt
 
 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:16 nfmt:1 s0
 // CHECK: error: out of range dfmt
 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:16 nfmt:1 s0
 // CHECK-NEXT:{{^}}                                                 ^
 
 //==============================================================================
 // out of range nfmt
 
 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:1 nfmt:-1 s0
 // CHECK: error: out of range nfmt
 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:1 nfmt:-1 s0
 // CHECK-NEXT:{{^}}                                                        ^

llvm/test/MC/AMDGPU/vop_sdwa.s

 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 
 // NOSICI: error: not a valid operand.
 // NOVI:   error: invalid operand for instruction
 // GFX9:   v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0xc1,0x06,0x86,0x06]
 v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 
 // NOSICI: error: not a valid operand.
-// GFX89:  v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
-v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX89:  v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x26]
+v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+
+// NOSICI: error: not a valid operand.
+// GFX89:  v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x16]
+v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 
 v_cndmask_b32_sdwa v5, vcc_lo, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
 // NOSICI: error: not a valid operand
 // NOVI:   error: invalid operand for instruction
 // NOGFX9: error: invalid operand (violates constant bus restrictions)
 
 //===----------------------------------------------------------------------===//
 // Check VOPC opcodes

 // Check Instructions
 //---------------------------------------------------------------------------//
 
 // NOSICI: error: instruction not supported on this GPU
 // NOVI: error: instruction not supported on this GPU
 // GFX9: v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 ; encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x00,0x00]
 v_screen_partition_4se_b32_sdwa v5, v1 src0_sel:BYTE_0
 
+// NOSICI: error: not a valid operand.
+// NOGFX89: error: not a valid operand.
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+
+// NOSICI: error: not a valid operand.
+// NOGFX89: error: not a valid operand.
+v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+
 //===----------------------------------------------------------------------===//
 // Validate register size checks (bug 37943)
 //===----------------------------------------------------------------------===//
 
 // NOSICI: error: invalid operand for instruction
 // NOGFX89: error: invalid operand for instruction
 v_add_f32 v0, s[0:1], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
 

llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_dpp16.txt

 # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x04,0x00]
 0xfa,0x04,0x0a,0x54,0x01,0x1b,0x04,0x00
 
 # GFX10: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0x00]
 0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0x00
 
 # GFX10: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
 0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00
+
+# W32: v_cndmask_b32_dpp v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff]
+# W64: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff
+
+# W32: v_cndmask_b32_dpp v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff]
+# W64: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff
+
+# W32: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
+# W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff

llvm/test/MC/Disassembler/AMDGPU/gfx10_vop2_sdwa.txt

 # GFX10: v_xor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06
 
 # GFX10: v_xor_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0x6b,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x3a,0x6b,0x06,0x86,0x06
 
 # GFX10: v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06
+
+# W32: v_cndmask_b32_sdwa v255, |v255|, -v255, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x26,0x15]
+# W64: v_cndmask_b32_sdwa v255, |v255|, -v255, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x26,0x15]
+0xf9,0xfe,0xff,0x03,0xff,0x0d,0x26,0x15
+
+# W32: v_cndmask_b32_sdwa v255, -v255, |v255|, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x16,0x25]
+# W64: v_cndmask_b32_sdwa v255, -v255, |v255|, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x16,0x25]
+0xf9,0xfe,0xff,0x03,0xff,0x0d,0x16,0x25
+
+# W32: v_cndmask_b32_sdwa v255, -|v255|, -|v255|, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x36,0x35]
+# W64: v_cndmask_b32_sdwa v255, -|v255|, -|v255|, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x03,0xff,0x0d,0x36,0x35]
+0xf9,0xfe,0xff,0x03,0xff,0x0d,0x36,0x35

llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt

 # W32: v_cndmask_b32_e64 v5, v1, v255, s6      ; encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x1b,0x00]
 # W64: v_cndmask_b32_e64 v5, v1, v255, s[6:7]  ; encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x1b,0x00]
 0x05,0x00,0x01,0xd5,0x01,0xff,0x1b,0x00
 
 # W32: v_cndmask_b32_e64 v5, v255, v2, s6      ; encoding: [0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00]
 # W64: v_cndmask_b32_e64 v5, v255, v2, s[6:7]  ; encoding: [0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00]
 0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00
 
+# W32: v_cndmask_b32_e64 v5, -v1, |v2|, vcc_lo ; encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
+# W64: v_cndmask_b32_e64 v5, -v1, |v2|, vcc    ; encoding: [0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21]
+0x05,0x02,0x01,0xd5,0x01,0x05,0xaa,0x21
+
+# W32: v_cndmask_b32_e64 v5, |v1|, -v2, vcc_lo ; encoding: [0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41]
+# W64: v_cndmask_b32_e64 v5, |v1|, -v2, vcc    ; encoding: [0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41]
+0x05,0x01,0x01,0xd5,0x01,0x05,0xaa,0x41
+
+# W32: v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc_lo ; encoding: [0x05,0x03,0x01,0xd5,0x01,0x05,0xaa,0x61]
+# W64: v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc ; encoding: [0x05,0x03,0x01,0xd5,0x01,0x05,0xaa,0x61]
+0x05,0x03,0x01,0xd5,0x01,0x05,0xaa,0x61
+
 # GFX10: v_cos_f16_e64 v255, v1                  ; encoding: [0xff,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00]
 0xff,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00
 
 # GFX10: v_cos_f16_e64 v5, -1                    ; encoding: [0x05,0x00,0xe1,0xd5,0xc1,0x00,0x00,0x00]
 0x05,0x00,0xe1,0xd5,0xc1,0x00,0x00,0x00
 
 # GFX10: v_cos_f16_e64 v5, -4.0                  ; encoding: [0x05,0x00,0xe1,0xd5,0xf7,0x00,0x00,0x00]
 0x05,0x00,0xe1,0xd5,0xf7,0x00,0x00,0x00

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt

 # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13]
 # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13]
 0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13
 
 # W32: v_cndmask_b32_dpp v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
 # W64: v_cndmask_b32_dpp v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30]
 0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30
 
+# W32: v_cndmask_b32_dpp v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff]
+# W64: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff
+
+# W32: v_cndmask_b32_dpp v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff]
+# W64: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff
+
+# W32: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
+# W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff]
+0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff
+
 # GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
 0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff
 
 # GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff]
 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff
 
 # GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff]
 0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt

 # W32: v_cndmask_b16_e64_dpp v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
 # W64: v_cndmask_b16_e64_dpp v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01]
 0x05,0x00,0x5d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x5f,0x01,0x01
 
 # W32: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp14 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
 # W64: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
 0x05,0x00,0x5d,0xd6,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13
 
+# GFX11: v_cndmask_b16_e64_dpp v5, -v1, |v2|, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 ; encoding: [0x05,0x02,0x5d,0xd6,0xfa,0x04,0xf2,0x21,0x01,0x6f,0x09,0x30]
+0x05,0x02,0x5d,0xd6,0xfa,0x04,0xf2,0x21,0x01,0x6f,0x09,0x30
+
+# GFX11: v_cndmask_b16_e64_dpp v5, |v1|, -v2, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 ; encoding: [0x05,0x01,0x5d,0xd6,0xfa,0x04,0xf2,0x41,0x01,0x6f,0x09,0x30]
+0x05,0x01,0x5d,0xd6,0xfa,0x04,0xf2,0x41,0x01,0x6f,0x09,0x30
+
 # GFX11: v_cndmask_b16_e64_dpp v255, v255, v255, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x5d,0xd6,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
 0xff,0x00,0x5d,0xd6,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
 
 # W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
 # W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
 0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff
 
 # W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]

 
 # W32: v_cndmask_b32_e64_dpp v5, v1, v2, ttmp14 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
 # W64: v_cndmask_b32_e64_dpp v5, v1, v2, ttmp[14:15] row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x00,0x01,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13]
 0x05,0x00,0x01,0xd5,0xfa,0x04,0xea,0x01,0x01,0x60,0x01,0x13
 
 # GFX11: v_cndmask_b32_e64_dpp v255, v255, v255, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x00,0x01,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30]
 0xff,0x00,0x01,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x0d,0x30
 
+# GFX11: v_cndmask_b32_e64_dpp v5, -v1, |v2|, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x05,0x02,0x01,0xd5,0xfa,0x04,0xf2,0x21,0x01,0x6f,0x0d,0x30]
+0x05,0x02,0x01,0xd5,0xfa,0x04,0xf2,0x21,0x01,0x6f,0x0d,0x30
+
+# GFX11: v_cndmask_b32_e64_dpp v5, |v1|, -v2, null row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0x05,0x01,0x01,0xd5,0xfa,0x04,0xf2,0x41,0x01,0x6f,0x0d,0x30]
+0x05,0x01,0x01,0xd5,0xfa,0x04,0xf2,0x41,0x01,0x6f,0x0d,0x30
+
 # GFX11: v_cos_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
 0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
 
 # GFX11: v_cos_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
 0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
 
 # GFX11: v_cos_f16_e64_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
 0x05,0x00,0xe1,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt

 # W32: v_cndmask_b16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
 # W64: v_cndmask_b16_e64_dpp v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
 0x05,0x00,0x5d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
 
 # W32: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp14 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
 # W64: v_cndmask_b16_e64_dpp v5, v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x5d,0xd6,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
 0x05,0x00,0x5d,0xd6,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05
 
+# GFX11: v_cndmask_b16_e64_dpp v5, -v1, |v2|, null dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x05,0x02,0x5d,0xd6,0xe9,0x04,0xf2,0x21,0x01,0x00,0x00,0x00]
+0x05,0x02,0x5d,0xd6,0xe9,0x04,0xf2,0x21,0x01,0x00,0x00,0x00
+
+# GFX11: v_cndmask_b16_e64_dpp v5, |v1|, -v2, null dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0x05,0x01,0x5d,0xd6,0xe9,0x04,0xf2,0x41,0x01,0x00,0x00,0x00]
+0x05,0x01,0x5d,0xd6,0xe9,0x04,0xf2,0x41,0x01,0x00,0x00,0x00
+
 # GFX11: v_cndmask_b16_e64_dpp v255, v255, v255, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x5d,0xd6,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
 0xff,0x00,0x5d,0xd6,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
 
 # W32: v_cndmask_b32_e64_dpp v5, v1, v2, s6 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
 # W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[6:7] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05]
 0x05,0x00,0x01,0xd5,0xe9,0x04,0x1a,0x00,0x01,0x77,0x39,0x05
 
 # W32: v_cndmask_b32_e64_dpp v5, v1, v2, s104 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
 # W64: v_cndmask_b32_e64_dpp v5, v1, v2, s[104:105] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05]
 0x05,0x00,0x01,0xd5,0xe9,0x04,0xa2,0x01,0x01,0x77,0x39,0x05
 
 # W32: v_cndmask_b32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
 # W64: v_cndmask_b32_e64_dpp v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05]
 0x05,0x00,0x01,0xd5,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05
 
 # W32: v_cndmask_b32_e64_dpp v5, v1, v2, ttmp14 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
 # W64: v_cndmask_b32_e64_dpp v5, v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x01,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05]
 0x05,0x00,0x01,0xd5,0xe9,0x04,0xea,0x01,0x01,0x77,0x39,0x05
 
 # GFX11: v_cndmask_b32_e64_dpp v255, v255, v255, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0x01,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
 0xff,0x00,0x01,0xd5,0xea,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00
 
+# GFX11: v_cndmask_b32_e64_dpp v5, -v1, |v2|, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x05,0x02,0x01,0xd5,0xea,0x04,0xf2,0x21,0x01,0x00,0x00,0x00]
+0x05,0x02,0x01,0xd5,0xea,0x04,0xf2,0x21,0x01,0x00,0x00,0x00
+
+# GFX11: v_cndmask_b32_e64_dpp v5, |v1|, -v2, null dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0x05,0x01,0x01,0xd5,0xea,0x04,0xf2,0x41,0x01,0x00,0x00,0x00]
+0x05,0x01,0x01,0xd5,0xea,0x04,0xf2,0x41,0x01,0x00,0x00,0x00
+
 # GFX11: v_cos_f16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
 0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
 
 # GFX11: v_cos_f16_e64_dpp v5, v1 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05]
 0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x08,0x01,0x77,0x39,0x05
 
 # GFX11: v_cos_f16_e64_dpp v5, v1 mul:4 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05]
 0x05,0x00,0xe1,0xd5,0xe9,0x00,0x00,0x10,0x01,0x77,0x39,0x05

llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_dpp.txt

 # CHECK: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0x1f,0x01,0x01]
 0xfa,0x04,0x0a,0x00,0x01,0x1f,0x01,0x01
 
 # CHECK: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:1 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0x21,0x01,0x13]
 0xfa,0x04,0x0a,0x00,0x01,0x21,0x01,0x13
 
 # CHECK: v_cndmask_b32_dpp v255, v255, v255, vcc row_ror:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xfe,0xff,0x01,0xff,0x2f,0x09,0x30]
 0xfa,0xfe,0xff,0x01,0xff,0x2f,0x09,0x30
+
+# CHECK: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x90,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0x90,0xff
+
+# CHECK: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x60,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0x60,0xff
+
+# CHECK: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf0,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf0,0xff

llvm/test/MC/Disassembler/AMDGPU/gfx8_vop2_sdwa.txt

 0xf9,0x04,0x0a,0x00,0x01,0x12,0x03,0x01
 
 # CHECK: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x13,0x04,0x02]
 0xf9,0x04,0x0a,0x00,0x01,0x13,0x04,0x02
 
 # CHECK: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_3 ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x04,0x05,0x03]
 0xf9,0x04,0x0a,0x00,0x01,0x04,0x05,0x03
 
-# CHECK: v_cndmask_b32_sdwa v255, sext(v255), sext(v255), vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x01,0xff,0x0d,0x0e,0x0d]
-0xf9,0xfe,0xff,0x01,0xff,0x0d,0x0e,0x0d
+# CHECK: v_cndmask_b32_sdwa v255, |v255|, -v255, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x01,0xff,0x0d,0x26,0x15]
+0xf9,0xfe,0xff,0x01,0xff,0x0d,0x26,0x15
+
+# CHECK: v_cndmask_b32_sdwa v255, -v255, |v255|, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x01,0xff,0x0d,0x16,0x25]
+0xf9,0xfe,0xff,0x01,0xff,0x0d,0x16,0x25
+
+# CHECK: v_cndmask_b32_sdwa v255, -|v255|, -|v255|, vcc dst_sel:WORD_1 dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:WORD_1 ; encoding: [0xf9,0xfe,0xff,0x01,0xff,0x0d,0x36,0x35]
+0xf9,0xfe,0xff,0x01,0xff,0x0d,0x36,0x35

llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt

 0x05,0x00,0x00,0xd1,0x01,0x05,0xb2,0x01
 
 # CHECK: v_cndmask_b32_e64 v5, v1, v2, tma       ; encoding: [0x05,0x00,0x00,0xd1,0x01,0x05,0xba,0x01]
 0x05,0x00,0x00,0xd1,0x01,0x05,0xba,0x01
 
 # CHECK: v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11] ; encoding: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
 0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01
 
+# CHECK: v_cndmask_b32_e64 v5, -v1, |v2|, vcc    ; encoding: [0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21]
+0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21
+
+# CHECK: v_cndmask_b32_e64 v5, |v1|, -v2, vcc    ; encoding: [0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41]
+0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41
+
+# CHECK: v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc ; encoding: [0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61]
+0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61
+
 # CHECK: v_add_f32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00
 
 # CHECK: v_add_f32_e64 v255, v1, v2              ; encoding: [0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00
 
 # CHECK: v_add_f32_e64 v5, v255, v2              ; encoding: [0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00]
 0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00

llvm/test/MC/Disassembler/AMDGPU/gfx9_sdwa_features.txt

 0xf9 0x06 0x02 0x3c 0x02 0x06 0x05 0x02
 
 # GFX9: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06]
 0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06
 
 # GFX9: v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0xc1,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x00,0xc1,0x06,0x86,0x06
 
-# GFX9: v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
-0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e
+# GFX9: v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x26]
+0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x26
+
+# GFX9: v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x16]
+0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x16
+
+# GFX9: v_cndmask_b32_sdwa v5, -|v1|, -|v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x36,0x36]
+0xf9,0x04,0x0a,0x00,0x01,0x06,0x36,0x36
 
 #-----------------------------------------------------------------------------#
 # VOPC
 #-----------------------------------------------------------------------------#
 
 # GFX9: v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x02,0x04]
 0xf9 0x04 0x84 0x7c 0x01 0x00 0x02 0x04
 

llvm/test/MC/Disassembler/AMDGPU/gfx9_vop2_dpp.txt

 # CHECK: v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x0f
 
 # CHECK: v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00
+
+# CHECK: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x90,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0x90,0xff
+
+# CHECK: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x60,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0x60,0xff
+
+# CHECK: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf0,0xff]
+0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf0,0xff

llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt

 0x05,0x00,0x00,0xd1,0x01,0x05,0x92,0x01
 
 # CHECK: v_cndmask_b32_e64 v5, v1, v2, flat_scratch ; encoding: [0x05,0x00,0x00,0xd1,0x01,0x05,0x9a,0x01]
 0x05,0x00,0x00,0xd1,0x01,0x05,0x9a,0x01
 
 # CHECK: v_cndmask_b32_e64 v5, v1, v2, vcc       ; encoding: [0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01]
 0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01
 
+# CHECK: v_cndmask_b32_e64 v5, -v1, |v2|, vcc    ; encoding: [0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21]
+0x05,0x02,0x00,0xd1,0x01,0x05,0xaa,0x21
+
+# CHECK: v_cndmask_b32_e64 v5, |v1|, -v2, vcc    ; encoding: [0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41]
+0x05,0x01,0x00,0xd1,0x01,0x05,0xaa,0x41
+
+# CHECK: v_cndmask_b32_e64 v5, -|v1|, -|v2|, vcc ; encoding: [0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61]
+0x05,0x03,0x00,0xd1,0x01,0x05,0xaa,0x61
+
 # CHECK: v_add_f32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00
 
 # CHECK: v_add_f32_e64 v255, v1, v2              ; encoding: [0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
 0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00
 
 # CHECK: v_add_f32_e64 v5, v255, v2              ; encoding: [0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00]
 0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00