[ARM] Add additional targets to divide tests.

[keith.walker.arm]

Summary

The main motivation for these additional targets is to cover the
differences in the instructions available between Thumb2 and Thumb1.

Ths shows up in these test due to the lack of the following in
Thumb1:

• Mulitply and Subtract instruction (mls) - used when calculating a remainder.
• Unsigned Muliple Long instruction (umull) - used in certain cases when optimising division with a constant.

[nickdesaulniers]

llvm/test/CodeGen/ARM/div.ll

0–1

You can use -check-prefixes=CHECK,CHECK-HWDIV,CHECK-HWDIV-T2 rather than repeatedly using -check-prefix=.

143

divide

[nickdesaulniers]

llvm/test/CodeGen/ARM/div.ll

1

should this RUN have a check for CHECK-THUMB as well?

3

should this RUN have a check for CHECK-THUMB as well?

[keith.walker.arm]

llvm/test/CodeGen/ARM/div.ll

0–1

Thanks, I'll update all the run lines to use this feature.

1

Maybe the name "CHECK-HWDIV-T2" could be improved because the CHECK-HWDIV-T2 case also covers the cases when ARM code is generated (rather than Thumb).

So maybe it should be "CHECK-HWDIV-NOT-T1" or possibly CHECK-HWDIV-ARM-OR-THUMB2 (and in this case change CHECK-HWDIV-T1 to CHECK-HWDIV-THUMB1).

Now I've just written that, I think the latter case is possibly the clearest in showing the intent, so I'm going to go with that unless someone provide a better suggestion.

143

Actually in this case multiply is correct.

The test cases @f7 and @f8 for checking for no libcall were added as part of this change https://reviews.llvm.org/D130862 which quote "this urem will be expand by DAGCombiner using multiply by magic constant". The lack of the necessary multiply instruction causes the optimisation in that change to not apply.

[DavidSpickett]

Can you summarise the differences you're testing for, in the commit message? I'm not very familiar with the differences but I'll quickly double check them if you list them out.

(also add [LLVM] at the start of the title while you're there)

[keith.walker.arm]

• Updated summary with description of the instructions not available in Thumb1.
• Merged the multiple --check-prefix= entries into a single --check-prefixes= entry.
• Changed CHECK-HWDIV-T2 to CHECK-HWDIV-ARM-OR-THUMB2.
• Changed CHECK-HW-DIV-T1 to CHECK-HWDIV-THUMB1.
• Tweaked comment about lack of 32-bit => 64-bit HW multiple instructions to say this prevents an optimisation.

[DavidSpickett]

Going from the architecture manual, T1 has those two instructions but for "Armv8-M Main Extension only". I see a test line for thumbv8m.base which I think does not have that, is it worth adding one with the main extension?

Otherwise this seems fine we're codifying what we already do and more coverage is a good thing.

[keith.walker.arm]

Added a mainline target "-mtriple=thumbv8m.main -mcpu=cortex-m33" as suggested.

[nickdesaulniers]

llvm/test/CodeGen/ARM/div.ll

3–5

If we're going to have added whitespace up to the pipes |, please keep these all aligned.

[DavidSpickett]

LGTM, once Nick's not done comments are addressed.

[keith.walker.arm]

Lined up all the pipes to keep them aligned.

llvm/test/CodeGen/ARM/div.ll

-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift        | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f   | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
-; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI
-; RUN: llc < %s -mtriple=armv7ve-none-linux-gnu           | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
-; RUN: llc < %s -mtriple=thumbv7ve-none-linux-gnu         | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV \
-; RUN:                  -check-prefix=CHECK-THUMB
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8      | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift          | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-HWDIV,CHECK-HWDIV-ARM-OR-THUMB2
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4      | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f     | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5      | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-HWDIV,CHECK-HWDIV-ARM-OR-THUMB2
+; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8      | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-EABI
+; RUN: llc < %s -mtriple=armv7 -mcpu=cortex-a7              | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-HWDIV,CHECK-HWDIV-ARM-OR-THUMB2
+; RUN: llc < %s -mtriple=armv7 -mcpu=cortex-a7 -march=thumb | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-HWDIV,CHECK-THUMB,CHECK-HWDIV-ARM-OR-THUMB2
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33  | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-HWDIV,CHECK-THUMB,CHECK-HWDIV-ARM-OR-THUMB2
+; RUN: llc < %s -mtriple=thumbv8m.base -mcpu=cortex-m23     | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-HWDIV,CHECK-THUMB,CHECK-HWDIV-THUMB1
+; RUN: llc < %s -mtriple=armv7ve-none-linux-gnu             | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-HWDIV
+; RUN: llc < %s -mtriple=thumbv7ve-none-linux-gnu           | \
+; RUN:     FileCheck %s -check-prefixes=CHECK,CHECK-HWDIV,CHECK-THUMB
 
 define i32 @f1(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f1
 ; CHECK-SWDIV: __divsi3
 
 ; CHECK-THUMB: .thumb_func
 ; CHECK-HWDIV: sdiv

 
 define i32 @f3(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f3
 ; CHECK-SWDIV: __modsi3
 
 ; CHECK-THUMB: .thumb_func
 ; CHECK-HWDIV: sdiv
-; CHECK-HWDIV: mls
+; CHECK-HWDIV-ARM-OR-THUMB2-NEXT: mls
+; CHECK-HWDIV-THUMB1-NEXT: muls
+; CHECK-HWDIV-THUMB1-NEXT: subs
 
 ; EABI MODE = Remainder in R1, quotient in R0
 ; CHECK-EABI: __aeabi_idivmod
 ; CHECK-EABI-NEXT: mov r0, r1
         %tmp1 = srem i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
 
 define i32 @f4(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f4
 ; CHECK-SWDIV: __umodsi3
 
 ; CHECK-THUMB: .thumb_func
 ; CHECK-HWDIV: udiv
-; CHECK-HWDIV: mls
+; CHECK-HWDIV-ARM-OR-THUMB2-NEXT: mls
+; CHECK-HWDIV-THUMB1-NEXT: muls
+; CHECK-HWDIV-THUMB1-NEXT: subs
 
 ; EABI MODE = Remainder in R1, quotient in R0
 ; CHECK-EABI: __aeabi_uidivmod
 ; CHECK-EABI-NEXT: mov r0, r1
         %tmp1 = urem i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
 

 ; CHECK-EABI-NEXT: mov r0, r2
 ; CHECK-EABI-NEXT: mov r1, r3
         %tmp1 = urem i64 %a, %b         ; <i64> [#uses=1]
         ret i64 %tmp1
 }
 
 ; Make sure we avoid a libcall for some constants.
 define i64 @f7(i64 %a) {
-; CHECK-SWDIV-LABEL: f7
+; CHECK-LABEL: f7
 ; CHECK-SWDIV: adc
 ; CHECK-SWDIV: umull
-; CHECK-HWDIV-LABEL: f7
-; CHECK-HWDIV: adc
-; CHECK-HWDIV: umull
-; CHECK-EABI-LABEL: f7
+; CHECK-HWDIV-ARM-OR-THUMB2: adc
+; CHECK-HWDIV-ARM-OR-THUMB2: umull
 ; CHECK-EABI: adc
 ; CHECK-EABI: umull
+; No 32-bit => 64-bit HW multiply instruction prevents optimisation
+; CHECK-HWDIV-THUMB1: __umoddi3
   %tmp1 = urem i64 %a, 3
   ret i64 %tmp1
 }
 
 ; Make sure we avoid a libcall for some constants.
 define i64 @f8(i64 %a) {
-; CHECK-SWDIV-LABEL: f8
+; CHECK-LABEL: f8
 ; CHECK-SWDIV: adc
 ; CHECK-SWDIV: umull
-; CHECK-HWDIV-LABEL: f8
-; CHECK-HWDIV: adc
-; CHECK-HWDIV: umull
-; CHECK-EABI-LABEL: f8
+; CHECK-HWDIV-ARM-OR-THUMB2: adc
+; CHECK-HWDIV-ARM-OR-THUMB2: umull
 ; CHECK-EABI: adc
 ; CHECK-EABI: umull
+; No 32-bit => 64-bit HW multiply instruction prevents optimisation
+; CHECK-HWDIV-THUMB1: __udivdi3
   %tmp1 = udiv i64 %a, 3
   ret i64 %tmp1
 }