[SPARC] Don't emit deprecated FP branches when targeting v9

[koakuma]

Summary

Don't emit deprecated v8-style FP compares & branches when targeting v9 processors.
For now, always use %fcc0, because currently the allocator requires allocatable registers to also be spillable, which isn't the case with v9 FCC registers.
The work to enable allocation over the entire FCC register file will be done in a future patch.

Fixes bug #17834 (https://github.com/llvm/llvm-project/issues/17834).

[koakuma]

I have a little bit of question regarding aesthetics: In the text assembly language, if the destination of FP compare is not specified, then it is taken as %fcc0.
(that is, fcmp<s|d|q> rs1, rs2 is encoded in the same way as fcmp<s|d|q> %fcc0, rs1, rs2 in the binary machine language)
Currently LLVM prefers to emit the former form. Is it okay to leave it as-is, or should it be changed so it explicitly spells out the %fcc0 destination?

[arsenm]

llvm/lib/Target/Sparc/SparcISelLowering.cpp

3252

No else after return

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

185 ↗

(On Diff #466289)

I'm assuming it would still be valid to use the old opcodes on v9. You should explicitly handle the opcodes with the additional conditional register input, rather than relying on the subtarget check

[arsenm]

llvm/lib/Target/Sparc/SparcISelLowering.cpp

1916

Should add an optimization test for this. There are handful of DAG combines and I think codegenprepare also makes use of this

[koakuma]

llvm/lib/Target/Sparc/SparcISelLowering.cpp

1916

Would rerunning the tests in 2011-01-11-CC.ll with optimization enabled be enough for this, or do I need to add other tests too?

[koakuma]

Codestyle changes + check branch opcode instead of subtarget when loading parameters.

[koakuma]

Don't include unused headers.

[arsenm]

llvm/lib/Target/Sparc/SparcISelLowering.cpp

1916

I don't know, I would kind of doubt that this changes the output there

[koakuma]

A question about the CI: It says that the build fails because of clang-format errors, yet when I run it locally it says "clang-format did not modify any files". What do I need to do?

llvm/lib/Target/Sparc/SparcISelLowering.cpp

1916

Hmm, I still don't know what extra optimizations are done by enabling setHasMultipleConditionRegisters so it's hard to me to make a suitable test case either...

Or, what about this: since currently I'm still unable to get LLVM to emit a code that would use more than one condition register, would it be okay if I remove that part for now and figure out how to deal with setHasMultipleConditionRegisters in a later patch?
For now, preventing it from emitting deprecated opcodes is enough for me.

[koakuma]

Don't do setHasMultipleConditionRegister.
For now, just disallow deprecated branch forms, the work of enabling whole-FP CCR allocation will be done in a separate patch.

[koakuma]

Simplify the implementation; in particular, do not trip into the allocator and force instructions to always use %fcc0.
This is to get around the limitation of needing allocatable registers to also be spillable, since, unfortunately, SPARC FCCs only support a very limited set of operations.

[arsenm]

Test coverage looks thin

llvm/lib/Target/Sparc/SparcISelLowering.h

 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {
   class SparcSubtarget;
 
   namespace SPISD {
   enum NodeType : unsigned {
     FIRST_NUMBER = ISD::BUILTIN_OP_END,
-    CMPICC, // Compare two GPR operands, set icc+xcc.
-    CMPFCC, // Compare two FP operands, set fcc.
-    BRICC,  // Branch to dest on icc condition
-    BPICC,  // Branch to dest on icc condition, with prediction (64-bit only).
-    BPXCC,  // Branch to dest on xcc condition, with prediction (64-bit only).
-    BRFCC,  // Branch to dest on fcc condition
+    CMPICC,    // Compare two GPR operands, set icc+xcc.
+    CMPFCC,    // Compare two FP operands, set fcc.
+    CMPFCC_V9, // Compare two FP operands, set fcc (v9 variant).
+    BRICC,     // Branch to dest on icc condition
+    BPICC,    // Branch to dest on icc condition, with prediction (64-bit only).
+    BPXCC,    // Branch to dest on xcc condition, with prediction (64-bit only).
+    BRFCC,    // Branch to dest on fcc condition
+    BRFCC_V9, // Branch to dest on fcc condition (v9 variant).
     SELECT_ICC, // Select between two values using the current ICC flags.
     SELECT_XCC, // Select between two values using the current XCC flags.
     SELECT_FCC, // Select between two values using the current FCC flags.
 
     Hi,
     Lo, // Hi/Lo operations, typically on a global address.
 
     FTOI, // FP to Int within a FP register.

llvm/lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   if (!Subtarget->is64Bit())
     setTargetDAGCombine(ISD::BITCAST);
 
   if (Subtarget->hasLeonCycleCounter())
     setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
 
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
   setMinFunctionAlignment(Align(4));
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 }
 
 bool SparcTargetLowering::useSoftFloat() const {
   return Subtarget->useSoftFloat();
 }
 
 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((SPISD::NodeType)Opcode) {
   case SPISD::FIRST_NUMBER:    break;
   case SPISD::CMPICC:          return "SPISD::CMPICC";
   case SPISD::CMPFCC:          return "SPISD::CMPFCC";
+  case SPISD::CMPFCC_V9:
+    return "SPISD::CMPFCC_V9";
   case SPISD::BRICC:           return "SPISD::BRICC";
   case SPISD::BPICC:
     return "SPISD::BPICC";
   case SPISD::BPXCC:
     return "SPISD::BPXCC";
   case SPISD::BRFCC:           return "SPISD::BRFCC";
+  case SPISD::BRFCC_V9:
+    return "SPISD::BRFCC_V9";
   case SPISD::SELECT_ICC:      return "SPISD::SELECT_ICC";
   case SPISD::SELECT_XCC:      return "SPISD::SELECT_XCC";
   case SPISD::SELECT_FCC:      return "SPISD::SELECT_FCC";
   case SPISD::Hi:              return "SPISD::Hi";
   case SPISD::Lo:              return "SPISD::Lo";
   case SPISD::FTOI:            return "SPISD::FTOI";
   case SPISD::ITOF:            return "SPISD::ITOF";
   case SPISD::FTOX:            return "SPISD::FTOX";
case SPISD::SELECT_FCC:
     break;
   }
 }
 
 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
                              ISD::CondCode CC, unsigned &SPCC) {
-  if (isNullConstant(RHS) &&
-      CC == ISD::SETNE &&
+  if (isNullConstant(RHS) && CC == ISD::SETNE &&
       (((LHS.getOpcode() == SPISD::SELECT_ICC ||
          LHS.getOpcode() == SPISD::SELECT_XCC) &&
         LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
        (LHS.getOpcode() == SPISD::SELECT_FCC &&
-        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
-      isOneConstant(LHS.getOperand(0)) &&
-      isNullConstant(LHS.getOperand(1))) {
+        (LHS.getOperand(3).getOpcode() == SPISD::CMPFCC ||
+         LHS.getOperand(3).getOpcode() == SPISD::CMPFCC_V9))) &&
+      isOneConstant(LHS.getOperand(0)) && isNullConstant(LHS.getOperand(1))) {
     SDValue CMPCC = LHS.getOperand(3);
     SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
     LHS = CMPCC.getOperand(0);
     RHS = CMPCC.getOperand(1);
   }
 }
 
 // Convert to a target node and set target flags.
else
       // Non-v9 targets don't have xcc.
       Opc = SPISD::BRICC;
   } else {
     if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
       CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
       Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
     } else {
-      CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
+      unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
+      CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
-      Opc = SPISD::BRFCC;
+      Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
     }
   }
   return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
                      DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
 }
 
 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
-                              const SparcTargetLowering &TLI,
-                              bool hasHardQuad) {
+                              const SparcTargetLowering &TLI, bool hasHardQuad,
+                              bool isV9) {
   SDValue LHS = Op.getOperand(0);
   SDValue RHS = Op.getOperand(1);
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
   SDValue TrueVal = Op.getOperand(2);
   SDValue FalseVal = Op.getOperand(3);
   SDLoc dl(Op);
   unsigned Opc, SPCC = ~0U;
 
   // If this is a select_cc of a "setcc", and if the setcc got lowered into
   // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
   LookThroughSetCC(LHS, RHS, CC, SPCC);
 
   SDValue CompareFlag;
   if (LHS.getValueType().isInteger()) {
     CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
     Opc = LHS.getValueType() == MVT::i32 ?
           SPISD::SELECT_ICC : SPISD::SELECT_XCC;
     if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
   } else {
     if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
       CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
       Opc = SPISD::SELECT_ICC;
     } else {
-      CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
+      unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
+      CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
       Opc = SPISD::SELECT_FCC;
       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
     }
   }
   return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
                      DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
 }
 
LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG, *this,
                                                        hasHardQuad);
   case ISD::FP_TO_UINT:         return LowerFP_TO_UINT(Op, DAG, *this,
                                                        hasHardQuad);
   case ISD::UINT_TO_FP:         return LowerUINT_TO_FP(Op, DAG, *this,
                                                        hasHardQuad);
   case ISD::BR_CC:
     return LowerBR_CC(Op, DAG, *this, hasHardQuad, isV9);
-  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG, *this,
-                                                      hasHardQuad);
+  case ISD::SELECT_CC:
+    return LowerSELECT_CC(Op, DAG, *this, hasHardQuad, isV9);
   case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
   case ISD::VAARG:              return LowerVAARG(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
                                                                Subtarget);
 
   case ISD::LOAD:               return LowerLOAD(Op, DAG);
   case ISD::STORE:              return LowerSTORE(Op, DAG);
   case ISD::FADD:               return LowerF128Op(Op, DAG,
SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   case SP::SELECT_CC_FP_XCC:
   case SP::SELECT_CC_DFP_XCC:
   case SP::SELECT_CC_QFP_XCC:
     return expandSelectCC(MI, BB, SP::BPXCC);
   case SP::SELECT_CC_Int_FCC:
   case SP::SELECT_CC_FP_FCC:
   case SP::SELECT_CC_DFP_FCC:
   case SP::SELECT_CC_QFP_FCC:
+    if (Subtarget->isV9())
+      return expandSelectCC(MI, BB, SP::FBCOND_V9);
     return expandSelectCC(MI, BB, SP::FBCOND);
   }
 }
 
 MachineBasicBlock *
 SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
                                     unsigned BROpcode) const {
   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
   DebugLoc dl = MI.getDebugLoc();
   unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
 

llvm/lib/Target/Sparc/SparcInstrInfo.td

 def SDTSPtlsld :
 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
 
 def SDTSPloadgdop :
 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
 
 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
+def SPcmpfccv9 : SDNode<"SPISD::CMPFCC_V9", SDTSPcmpfcc, [SDNPOutGlue]>;
 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbpicc : SDNode<"SPISD::BPICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbpxcc : SDNode<"SPISD::BPXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
+def SPbrfccv9 : SDNode<"SPISD::BRFCC_V9", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 
 def SPhi    : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
 def SPlo    : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
 
 def SPftoi  : SDNode<"SPISD::FTOI", SDTSPFTOI>;
 def SPitof  : SDNode<"SPISD::ITOF", SDTSPITOF>;
 def SPftox  : SDNode<"SPISD::FTOX", SDTSPFTOX>;
 def SPxtof  : SDNode<"SPISD::XTOF", SDTSPXTOF>;

 let Uses = [FCC0] in {
   def FBCOND  : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
                               "fb$cond $imm22",
                               [(SPbrfcc bb:$imm22, imm:$cond)]>;
   def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
                              "fb$cond,a $imm22", []>;
 }
 
+// Variants of FBCOND that uses V9 opcode
+let Predicates = [HasV9], Uses = [FCC0], cc = 0,
+    isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
+  def FBCOND_V9  : F2_3<0b101, 0, 1, (outs),
+                    (ins bprtarget:$imm19, CCOp:$cond),
+                    "fb$cond %fcc0, $imm19",
+                    [(SPbrfccv9 bb:$imm19, imm:$cond)], IIC_fpu_normal_instr>;
+  def FBCONDA_V9 : F2_3<0b101, 1, 1, (outs),
+                    (ins bprtarget:$imm19, CCOp:$cond),
+                    "fb$cond,a %fcc0, $imm19",
+                    [(SPbrfccv9 bb:$imm19, imm:$cond)], IIC_fpu_normal_instr>;
+}
+
 let Predicates = [HasV9] in
   defm BPF : FPredBranch;
 
 // Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123
 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
 
 // co-processor conditional branch class:
 class CPBranchSP<dag ins, string asmstr, list<dag> pattern>
def FCMPD  : F3_3c<2, 0b110101, 0b001010010,
                    IIC_fpu_fast_instr>;
   def FCMPQ  : F3_3c<2, 0b110101, 0b001010011,
                    (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
                    "fcmpq $rs1, $rs2",
                    [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
                    Requires<[HasHardQuad]>;
 }
 
+// A.13 Floating-Point Compare (SPARC v9)
+// Note that these always write to %fcc0 instead of having its destination
+// allocated automatically.
+// This avoids complications with the scheduler sometimes wanting to spill
+// the contents of an FCC, since SPARC v9 doesn't have facilities to spill
+// an individual FCC.
+
+let Predicates = [HasV9], Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
+  def FCMPS_V9  : F3_3c<2, 0b110101, 0b001010001,
+                   (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
+                   "fcmps %fcc0, $rs1, $rs2",
+                   [(SPcmpfccv9 f32:$rs1, f32:$rs2)],
+                   IIC_fpu_fast_instr>;
+  def FCMPD_V9  : F3_3c<2, 0b110101, 0b001010010,
+                   (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+                   "fcmpd %fcc0, $rs1, $rs2",
+                   [(SPcmpfccv9 f64:$rs1, f64:$rs2)],
+                   IIC_fpu_fast_instr>;
+  def FCMPQ_V9  : F3_3c<2, 0b110101, 0b001010011,
+                   (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
+                   "fcmpq %fcc0, $rs1, $rs2",
+                   [(SPcmpfccv9 f128:$rs1, f128:$rs2)]>,
+                   Requires<[HasHardQuad]>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions for Thread Local Storage(TLS).
 //===----------------------------------------------------------------------===//
 let isAsmParserOnly = 1 in {
 def TLS_ADDrr : F3_1<2, 0b000000,
                     (outs IntRegs:$rd),
                     (ins IntRegs:$rs1, IntRegs:$rs2, TailRelocSymTLSAdd:$sym),
                     "add $rs1, $rs2, $rd, $sym",

llvm/test/CodeGen/SPARC/2011-01-11-CC.ll

 entry:
 ; V8-LABEL: test_float_cc
 ; V8:       fcmpd
 ; V8:       {{fbl|fbuge}} .LBB
 ; V8:       fcmpd
 ; V8:       {{fbule|fbg}} .LBB
 
 ; V9-LABEL: test_float_cc
-; V9:       fcmpd
-; V9:       {{fbl|fbuge}} .LBB
-; V9:       fcmpd
-; V9:       {{fbule|fbg}} .LBB
+; V9:       fcmpd %fcc0
+; V9:       {{fbl|fbuge}} %fcc0, .LBB
+; V9:       fcmpd %fcc0
+; V9:       {{fbule|fbg}} %fcc0, .LBB
 
    %0 = fcmp uge double %a, 0.000000e+00
    br i1 %0, label %loop, label %loop.2
 
 loop:
    %1 = icmp eq i32 %c, 10
    br i1 %1, label %loop, label %exit.0
 

llvm/test/CodeGen/SPARC/64cond.ll

 entry:
   %tobool = icmp sgt i32 %x, %y
   %rv = select i1 %tobool, i64 %a, i64 %b
   ret i64 %rv
 }
 
 ; CHECK: selecti64_fcc
 ; CHECK: mov %i3, %i0
-; CHECK: fcmps %f1, %f3
+; CHECK: fcmps %fcc0, %f1, %f3
 ; CHECK: movul %fcc0, %i2, %i0
 ; CHECK: restore
 define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
 entry:
   %tobool = fcmp ult float %x, %y
   %rv = select i1 %tobool, i64 %a, i64 %b
   ret i64 %rv
 }