[GISel] Add redundant bitcast folding combine

[Pierre-vh]

Summary

Simply folds away bitcasts that cancel each other.

[Pierre-vh]

Rebase

[arsenm]

llvm/include/llvm/Target/GlobalISel/Combine.td

972–973

I think this one is actually possible with the real matcher.
Can you try something like

match (BITCAST $dst, $src1), (BITCAST $src1, $src0))

[Pierre-vh]

Move to tablegen

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

public:
 
   /// Transform G_ADD(x, G_SUB(y, x)) to y.
   /// Transform G_ADD(G_SUB(y, x), x) to y.
   bool matchAddSubSameReg(MachineInstr &MI, Register &Src);
 
   bool matchBuildVectorIdentityFold(MachineInstr &MI, Register &MatchInfo);
   bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo);
   bool matchTruncLshrBuildVectorFold(MachineInstr &MI, Register &MatchInfo);
+  bool matchBitcastBitcastFold(MachineInstr &MI, Register &MatchInfo);
 
   /// Transform:
   ///   (x + y) - y -> x
   ///   (x + y) - x -> y
   ///   x - (y + x) -> 0 - y
   ///   x - (x + z) -> 0 - z
   bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo);
 

llvm/include/llvm/Target/GlobalISel/Combine.td

 //   x - (y + x) -> 0 - y
 //   x - (x + z) -> 0 - z
 def sub_add_reg: GICombineRule <
   (defs root:$root, build_fn_matchinfo:$matchinfo),
   (match (wip_match_opcode G_SUB):$root,
          [{ return Helper.matchSubAddSameReg(*${root}, ${matchinfo}); }]),
   (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
 
+def bitcast_bitcast_fold : GICombineRule<
+  (defs root:$op, register_matchinfo:$matchinfo),
+  (match (wip_match_opcode G_BITCAST):$op,
+      [{ return Helper.matchBitcastBitcastFold(*${op}, ${matchinfo}); }]),
+  (apply [{ Helper.replaceSingleDefInstWithReg(*${op}, ${matchinfo}); }])>;
+
 def select_to_minmax: GICombineRule<
   (defs root:$root, build_fn_matchinfo:$info),
   (match (wip_match_opcode G_SELECT):$root,
          [{ return Helper.matchSimplifySelectToMinMax(*${root}, ${info}); }]),
   (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
 
 // FIXME: These should use the custom predicate feature once it lands.
 def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,

 
 def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
                                         binop_same_val, binop_left_to_zero,
                                         binop_right_to_zero, p2i_to_i2p,
                                         i2p_to_p2i, anyext_trunc_fold,
                                         fneg_fneg_fold, right_identity_one,
                                         add_sub_reg, buildvector_identity_fold,
                                         trunc_buildvector_fold,
-                                        trunc_lshr_buildvector_fold]>;
+                                        trunc_lshr_buildvector_fold,
+                                        bitcast_bitcast_fold]>;
 
 def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p,
                                      overlapping_and, mulo_by_2, mulo_by_0,
                                      addo_by_0, adde_to_addo,
                                      combine_minmax_nan]>;
 
 def known_bits_simplifications : GICombineGroup<[
   redundant_and, redundant_sext_inreg, redundant_or, urem_pow2_to_mask,

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

if (!mi_match(MI.getOperand(1).getReg(), MRI,
                         m_GCst(ShiftAmt))))
     return false;
 
   LLT MatchTy = MRI.getType(MatchInfo);
   return ShiftAmt->Value.getZExtValue() == MatchTy.getSizeInBits() &&
          MatchTy == MRI.getType(MI.getOperand(0).getReg());
 }
 
+bool CombinerHelper::matchBitcastBitcastFold(MachineInstr &MI,
+                                             Register &MatchInfo) {
+  // Matches two bitcasts in a row that cancel each-other.
+
+  Register Src = MI.getOperand(1).getReg();
+  MachineInstr *SrcMI = getDefIgnoringCopies(Src, MRI);
+
+  if (SrcMI->getOpcode() != TargetOpcode::G_BITCAST)
+    return false;
+
+  Register Dst = MI.getOperand(0).getReg();
+  MatchInfo = SrcMI->getOperand(1).getReg();
+  return MRI.getType(MatchInfo) == MRI.getType(Dst);
+}
+
 unsigned CombinerHelper::getFPMinMaxOpcForSelect(
     CmpInst::Predicate Pred, LLT DstTy,
     SelectPatternNaNBehaviour VsNaNRetVal) const {
   assert(VsNaNRetVal != SelectPatternNaNBehaviour::NOT_APPLICABLE &&
          "Expected a NaN behaviour?");
   // Choose an opcode based off of legality or the behaviour when one of the
   // LHS/RHS may be NaN.
   switch (Pred) {

llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-redundant-bitcast.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: s32_bitcast
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: s32_bitcast
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK-NEXT: $vgpr0 = COPY %src(<2 x s16>)
+    %src:_(<2 x s16>) = COPY $vgpr0
+    %b1:_(s32) = G_BITCAST %src
+    %b2:_(<2 x s16>) = G_BITCAST %b1
+    $vgpr0 = COPY %b2
+...
+
+---
+name: s64_bitcast
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: s64_bitcast
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %src(<2 x s32>)
+    %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %b1:_(s64) = G_BITCAST %src
+    %b2:_(<2 x s32>) = G_BITCAST %b1
+    $vgpr0_vgpr1 = COPY %b2
+...
+
+---
+name: s64_bitcast_differentypes_nofold
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: s64_bitcast_differentypes_nofold
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: %b1:_(s64) = G_BITCAST %src(<2 x s32>)
+    ; CHECK-NEXT: %b2:_(<4 x s16>) = G_BITCAST %b1(s64)
+    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %b2(<4 x s16>)
+    %src:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %b1:_(s64) = G_BITCAST %src
+    %b2:_(<4 x s16>) = G_BITCAST %b1
+    $vgpr0_vgpr1 = COPY %b2
+...