[RISCV][ISel] Remove the commutative flag on SUB

[qcolombet]

Summary

I wasn't able to produce a testcase for that because right now VWSUB is only generated from VWSUB_W and to trigger the commutative bug we would need to turn that VWSUB_W into VWSUB while having the splat value on the LHS, which is currently not matched by the existing combine.

Presumably we could hit this issue directly with vwsub intrinsics, but I didn't know how to produce a splat value for a vscale type and I don't know if it is possible to use the intrinsic without the vscale type.

[craig.topper]

The vwsub intrinsic doesn't go through RISCVISD::VWSUB_VL/VWSUBU_VL. It's pattern matched separately in RISCVInstrInfoVPseudos.td

vscale splat is insertelement into element 0 followed by shufflevector with zeroinitializer for the mask.

LGTM

[qcolombet]

Thanks @craig.topper for the details!

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>,
                                                SDTCisSameNumEltsAs<1, 4>,
                                                SDTCVecEltisVT<4, i1>,
                                                SDTCisVT<5, XLenVT>]>;
 def riscv_vwmul_vl  : SDNode<"RISCVISD::VWMUL_VL",  SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
 def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
 def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>;
 def riscv_vwadd_vl :  SDNode<"RISCVISD::VWADD_VL",  SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
 def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
-def riscv_vwsub_vl :  SDNode<"RISCVISD::VWSUB_VL",  SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
-def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>;
+def riscv_vwsub_vl :  SDNode<"RISCVISD::VWSUB_VL",  SDT_RISCVVWBinOp_VL, []>;
+def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, []>;
 
 def SDT_RISCVVNBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>,
                                                SDTCisSameNumEltsAs<0, 1>,
                                                SDTCisOpSmallerThanOp<0, 1>,
                                                SDTCisSameAs<0, 2>,
                                                SDTCisSameAs<0, 3>,
                                                SDTCisSameNumEltsAs<0, 4>,
                                                SDTCVecEltisVT<4, i1>,