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Differential D134643

[AArch64] Add tests for selecting SMULL instruction where the operand is zero extended and the top bit value is 0
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Authored by zjaffal on Sep 26 2022, 6:36 AM.

Details

Reviewers
fhahn
t.p.northover
spatel
dmgreen
Commits
rG4fbbfd2530aa: [AArch64] Add tests for selecting SMULL instruction where the operand is zero…
Summary

This covers the case where we can convert a zext instruction to a sext and then select smull

Diff Detail

Event Timeline

zjaffal created this revision.Sep 26 2022, 6:36 AM
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zjaffal requested review of this revision.Sep 26 2022, 6:36 AM
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fhahn added inline comments.Sep 26 2022, 6:49 AM
llvm/test/CodeGen/AArch64/aarch64-smull.ll
62

It would make the test slightly easier to read if more descriptive names for the values would be used, e.g. %tmp2 -> load.B, %tmp4 -> %sext.B`.

fhahn added a reviewer: dmgreen.Sep 26 2022, 6:49 AM
Harbormaster completed remote builds in B188695: Diff 462893.Sep 26 2022, 7:47 AM
zjaffal updated this revision to Diff 463127.Sep 27 2022, 12:51 AM

rename variables in tests

fhahn added a child revision: D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero.Sep 27 2022, 2:09 AM
Harbormaster completed remote builds in B188874: Diff 463127.Sep 27 2022, 2:34 AM
This revision was not accepted when it landed; it landed in state Needs Review.Sep 27 2022, 11:44 AM
Closed by commit rG4fbbfd2530aa: [AArch64] Add tests for selecting SMULL instruction where the operand is zero… (authored by zjaffal, committed by fhahn). · Explain Why
This revision was automatically updated to reflect the committed changes.
fhahn added a commit: rG4fbbfd2530aa: [AArch64] Add tests for selecting SMULL instruction where the operand is zero….
fhahn added a comment.Sep 27 2022, 11:46 AM

LGTM, thanks!

Revision Contents

PathSize
llvm/
test/
CodeGen/
AArch64/
88 lines

Diff 463127

llvm/test/CodeGen/AArch64/aarch64-smull.ll

Show All 40 Lines; CHECK-NEXT: ret
%tmp1 = load <2 x i32>, <2 x i32>* %A %tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = sext <2 x i32> %tmp1 to <2 x i64> %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
%tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = mul <2 x i64> %tmp3, %tmp4 %tmp5 = mul <2 x i64> %tmp3, %tmp4
ret <2 x i64> %tmp5 ret <2 x i64> %tmp5
} }
define <8 x i32> @smull_zext_v8i8_v8i32(<8 x i8>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: smull_zext_v8i8_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr q1, [x1]
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: sshll v2.4s, v1.4h, #0
; CHECK-NEXT: sshll2 v1.4s, v1.8h, #0
; CHECK-NEXT: ushll2 v3.4s, v0.8h, #0
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: mul v1.4s, v3.4s, v1.4s
; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ret
%load.A = load <8 x i8>, <8 x i8>* %A
fhahnUnsubmitted
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ReplyInline Actions

It would make the test slightly easier to read if more descriptive names for the values would be used, e.g. %tmp2 -> load.B, %tmp4 -> %sext.B`.

fhahn: It would make the test slightly easier to read if more descriptive names for the values would…
%load.B = load <8 x i16>, <8 x i16>* %B
%zext.A = zext <8 x i8> %load.A to <8 x i32>
%sext.B = sext <8 x i16> %load.B to <8 x i32>
%res = mul <8 x i32> %zext.A, %sext.B
ret <8 x i32> %res
}
define <4 x i32> @smull_zext_v4i16_v4i32(<4 x i8>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: smull_zext_v4i16_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr s0, [x0]
; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: sshll v1.4s, v1.4h, #0
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%load.A = load <4 x i8>, <4 x i8>* %A
%load.B = load <4 x i16>, <4 x i16>* %B
%zext.A = zext <4 x i8> %load.A to <4 x i32>
%sext.B = sext <4 x i16> %load.B to <4 x i32>
%res = mul <4 x i32> %zext.A, %sext.B
ret <4 x i32> %res
}
define <2 x i64> @smull_zext_v2i32_v2i64(<2 x i16>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: smull_zext_v2i32_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: ldrh w8, [x0]
; CHECK-NEXT: ldrh w11, [x0, #2]
; CHECK-NEXT: sshll v0.2d, v0.2s, #0
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: mov x10, v0.d[1]
; CHECK-NEXT: mul x8, x8, x9
; CHECK-NEXT: mul x9, x11, x10
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: ret
%load.A = load <2 x i16>, <2 x i16>* %A
%load.B = load <2 x i32>, <2 x i32>* %B
%zext.A = zext <2 x i16> %load.A to <2 x i64>
%sext.B = sext <2 x i32> %load.B to <2 x i64>
%res = mul <2 x i64> %zext.A, %sext.B
ret <2 x i64> %res
}
define <2 x i64> @smull_zext_and_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: smull_zext_and_v2i32_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: bic v0.2s, #128, lsl #24
; CHECK-NEXT: sshll v1.2d, v1.2s, #0
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-NEXT: fmov x9, d1
; CHECK-NEXT: fmov x10, d0
; CHECK-NEXT: mov x8, v1.d[1]
; CHECK-NEXT: mov x11, v0.d[1]
; CHECK-NEXT: mul x9, x10, x9
; CHECK-NEXT: mul x8, x11, x8
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret
%load.A = load <2 x i32>, <2 x i32>* %A
%and.A = and <2 x i32> %load.A, <i32 u0x7FFFFFFF, i32 u0x7FFFFFFF>
%load.B = load <2 x i32>, <2 x i32>* %B
%zext.A = zext <2 x i32> %and.A to <2 x i64>
%sext.B = sext <2 x i32> %load.B to <2 x i64>
%res = mul <2 x i64> %zext.A, %sext.B
ret <2 x i64> %res
}
define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: umull_v8i8_v8i16: ; CHECK-LABEL: umull_v8i8_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b ; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
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