[GlobalISel] Fix crash when lowering G_SELECT of pointer vectors.

[aemerson]

Summary

The bit masking lowering only works for vectors of scalars, so for pointer element types we need to add some casting.

[tschuett]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

7275

Could you hoist the buildOr out of the if-statement? Then you only need the cast if IsEltPtr.

[aemerson]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

7275

Not really, because in the !IsEltPtr case we're trying to re-use the DstReg register, while in the other branch we're creating a new value since we need to then cast it.

[tschuett]

Sorry. I didn't notice that they are different.

[foad]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

7272

Nit: when there's an "else" I prefer to put the "if (IsEltPtr)" case first to avoid an implied double negative.

[aemerson]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

7272

Ok I'll change that before commit.

[arsenm]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

7235

Can sink this into the if

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
   Register MaskReg = MI.getOperand(1).getReg();
   Register Op1Reg = MI.getOperand(2).getReg();
   Register Op2Reg = MI.getOperand(3).getReg();
   LLT DstTy = MRI.getType(DstReg);
   LLT MaskTy = MRI.getType(MaskReg);
   if (!DstTy.isVector())
     return UnableToLegalize;
 
+  bool IsEltPtr = DstTy.getElementType().isPointer();
+  LLT ScalarPtrTy = LLT::scalar(DstTy.getScalarSizeInBits());
+  if (IsEltPtr) {
+    LLT NewTy = DstTy.changeElementType(ScalarPtrTy);
+    Op1Reg = MIRBuilder.buildPtrToInt(NewTy, Op1Reg).getReg(0);
+    Op2Reg = MIRBuilder.buildPtrToInt(NewTy, Op2Reg).getReg(0);
+    DstTy = NewTy;
+  }
+
   if (MaskTy.isScalar()) {
     // Turn the scalar condition into a vector condition mask.
 
     Register MaskElt = MaskReg;
 
     // The condition was potentially zero extended before, but we want a sign
     // extended boolean.
     if (MaskTy.getSizeInBits() <= DstTy.getScalarSizeInBits() &&
LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
 
   if (MaskTy.getSizeInBits() != DstTy.getSizeInBits()) {
     return UnableToLegalize;
   }
 
   auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg);
   auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg);
   auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask);
+  if (!IsEltPtr)
     MIRBuilder.buildOr(DstReg, NewOp1, NewOp2);
+  else {
+    auto Or = MIRBuilder.buildOr(DstTy, NewOp1, NewOp2);
+    MIRBuilder.buildIntToPtr(DstReg, Or);
+  }
   MI.eraseFromParent();
   return Legalized;
 }
 
 LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) {
   // Split DIVREM into individual instructions.
   unsigned Opcode = MI.getOpcode();
 

llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir

bb.0:
     %5:_(<4 x s32>) = G_BUILD_VECTOR %6(s32), %6(s32), %6(s32), %6(s32)
     %cmp:_(s1) = G_ICMP intpred(eq), %w0, %2
     %select:_(<4 x s1>) = G_SELECT %cmp, %vec_cond0, %vec_cond1
     %zext_select:_(<4 x s32>) = G_ZEXT %select
     $q0 = COPY %zext_select
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            lower_select_vec_ptr
+liveins:
+  - { reg: '$x0' }
+  - { reg: '$q0' }
+body:             |
+  bb.1:
+    liveins: $q0, $x0
+
+    ; CHECK-LABEL: name: lower_select_vec_ptr
+    ; CHECK: liveins: $q0, $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $q0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[C]](p0), [[C]](p0)
+    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[C]]
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[COPY1]](<2 x p0>)
+    ; CHECK-NEXT: [[PTRTOINT1:%[0-9]+]]:_(<2 x s64>) = G_PTRTOINT [[BUILD_VECTOR]](<2 x p0>)
+    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[AND]], 1
+    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT]](s64), [[C2]](s64)
+    ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C3]](s64), [[C3]](s64)
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT]], [[SHUF]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[PTRTOINT1]], [[XOR]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND2]]
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(<2 x p0>) = G_INTTOPTR [[OR]](<2 x s64>)
+    ; CHECK-NEXT: $q0 = COPY [[INTTOPTR]](<2 x p0>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
+    %0:_(p0) = COPY $x0
+    %1:_(<2 x p0>) = COPY $q0
+    %2:_(p0) = G_CONSTANT i64 0
+    %5:_(<2 x p0>) = G_BUILD_VECTOR %2(p0), %2(p0)
+    %3:_(s1) = G_ICMP intpred(eq), %0(p0), %2
+    %4:_(<2 x p0>) = G_SELECT %3(s1), %1, %5
+    $q0 = COPY %4(<2 x p0>)
+    RET_ReallyLR implicit $q0
+
+...