[PowerPC] Change CRNOT to a code gen single operand instruction

[nemanjai]

Summary

Inputs to crnor can come from operands with chains so if it is being used simply to negate such an operand, the repeated input cannot be CSE'd. This patch just adds a code-gen only instruction for this that takes a single input and duplicates it in the encoding of the underlying crnor.

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2484

Looks like I accidentally removed this line. I'll get rid of the unrelated change.

[craig.topper]

LGTM

[lei]

LGTM
Thx

llvm/lib/Target/PowerPC/P10InstrResources.td

def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read],
     CMPB, CMPB8,
     CMPDI, CMPWI,
     CMPLD, CMPLW,
     CMPLDI, CMPLWI,
     CRAND,
     CRANDC,
     CRNAND,
     CRNOR,
+    CRNOT,
     CROR,
     CRORC,
     CR6UNSET, CRUNSET, CRXOR,
     EQV, EQV8,
     EQV8_rec, EQV_rec,
     EXTSWSLI, EXTSWSLI_32_64,
     FCPSGND, FCPSGNS,
     NAND, NAND8,

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_3SLOTS_1C],
     (instregex "FNEG(D|S)$"),
     (instregex "FCPSGN(D|S)$"),
     (instregex "SRAW(I)?$"),
     (instregex "ISEL(8)?$"),
     RLDIMI,
     XSIEXPDP,
     FMR,
     CREQV,
+    CRNOT,
     CRXOR,
     TRECLAIM,
     TSR,
     TABORT
 )>;
 
 // Three cycle ALU vector operation that uses an entire superslice.
 // Uses both ALU units (the even ALUE and odd ALUO units), two pipelines

llvm/lib/Target/PowerPC/PPCBack2BackFusion.def

FUSION_OP_SET(ADD4,
     CNTTZW_rec,
     CR6SET,
     CR6UNSET,
     CRAND,
     CRANDC,
     CREQV,
     CRNAND,
     CRNOR,
+    CRNOT,
     CROR,
     CRORC,
     CRSET,
     CRUNSET,
     CRXOR,
     DSS,
     DSSALL,
     DST,
FUSION_OP_SET(ADD4,
     XXLNOR,
     XXLOR,
     XXLORC,
     XXLORf,
     XXLXOR,
     XXLXORdpz,
     XXLXORspz,
     XXLXORz,
-    XXSEL))
+    XXSEL))
 

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

for (SDNode &Node : CurDAG->allnodes()) {
       case PPC::CRANDC:
       case PPC::CRORC: {
         SDValue Op = MachineNode->getOperand(1);
         if (Op.isMachineOpcode()) {
           if (Op.getMachineOpcode() == PPC::CRSET)
             Op2Set = true;
           else if (Op.getMachineOpcode() == PPC::CRUNSET)
             Op2Unset = true;
-          else if (Op.getMachineOpcode() == PPC::CRNOR &&
-                   Op.getOperand(0) == Op.getOperand(1))
+          else if ((Op.getMachineOpcode() == PPC::CRNOR &&
+                    Op.getOperand(0) == Op.getOperand(1)) ||
+                   Op.getMachineOpcode() == PPC::CRNOT)
             Op2Not = true;
         }
         [[fallthrough]];
       }
       case PPC::BC:
       case PPC::BCn:
       case PPC::SELECT_I4:
       case PPC::SELECT_I8:
       case PPC::SELECT_F4:
       case PPC::SELECT_F8:
       case PPC::SELECT_SPE:
       case PPC::SELECT_SPE4:
       case PPC::SELECT_VRRC:
       case PPC::SELECT_VSFRC:
       case PPC::SELECT_VSSRC:
       case PPC::SELECT_VSRC: {
         SDValue Op = MachineNode->getOperand(0);
         if (Op.isMachineOpcode()) {
           if (Op.getMachineOpcode() == PPC::CRSET)
             Op1Set = true;
           else if (Op.getMachineOpcode() == PPC::CRUNSET)
             Op1Unset = true;
-          else if (Op.getMachineOpcode() == PPC::CRNOR &&
-                   Op.getOperand(0) == Op.getOperand(1))
+          else if ((Op.getMachineOpcode() == PPC::CRNOR &&
+                    Op.getOperand(0) == Op.getOperand(1)) ||
+                   Op.getMachineOpcode() == PPC::CRNOT)
             Op1Not = true;
         }
         }
         break;
       }
 
       bool SelectSwap = false;
       switch (Opcode) {

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   
   let Inst{6-10}  = CRD;
   let Inst{11-15} = CRA;
   let Inst{16-20} = CRB;
   let Inst{21-30} = xo;
   let Inst{31}    = 0;
 }
 
+// XL-Form for unary alias for CRNOR (CRNOT)
+class XLForm_1s<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+                InstrItinClass itin, list<dag> pattern>
+    : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let CRB = CRA;
+}
+
 class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                   InstrItinClass itin, list<dag> pattern>
   : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
   let CRD = 0;
   let CRA = 0;
   let CRB = 0;
 }
 

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def CRXOR  : XLForm_1<19, 193, (outs crbitrc:$CRD),
                                (ins crbitrc:$CRA, crbitrc:$CRB),
                       "crxor $CRD, $CRA, $CRB", IIC_BrCR,
                       [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
 
 def CRNOR  : XLForm_1<19, 33, (outs crbitrc:$CRD),
                               (ins crbitrc:$CRA, crbitrc:$CRB),
                       "crnor $CRD, $CRA, $CRB", IIC_BrCR,
                       [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
-
 def CREQV  : XLForm_1<19, 289, (outs crbitrc:$CRD),
                                (ins crbitrc:$CRA, crbitrc:$CRB),
                       "creqv $CRD, $CRA, $CRB", IIC_BrCR,
                       [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
 } // isCommutable
 
+let isCodeGenOnly = 1 in
+def CRNOT  : XLForm_1s<19, 33, (outs crbitrc:$CRD), (ins crbitrc:$CRA),
+                       "crnot $CRD, $CRA", IIC_BrCR,
+                       [(set i1:$CRD, (not i1:$CRA))]>;
+
 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
                                (ins crbitrc:$CRA, crbitrc:$CRB),
                       "crandc $CRD, $CRA, $CRB", IIC_BrCR,
                       [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
 
 def CRORC  : XLForm_1<19, 417, (outs crbitrc:$CRD),
                                (ins crbitrc:$CRA, crbitrc:$CRB),
                       "crorc $CRD, $CRA, $CRB", IIC_BrCR,

 
 include "PPCInstrAltivec.td"
 include "PPCInstrSPE.td"
 include "PPCInstr64Bit.td"
 include "PPCInstrVSX.td"
 include "PPCInstrHTM.td"
 
 def crnot : OutPatFrag<(ops node:$in),
-                       (CRNOR $in, $in)>;
+                       (CRNOT $in)>;
 def       : Pat<(not i1:$in),
                 (crnot $in)>;
 
 // Prefixed instructions may require access to the above defs at a later
 // time so we include this after the def.
 include "PPCInstrP10.td"
 include "PPCInstrMMA.td"
 

llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp

private:
   SmallVector<CRLogicalOpInfo, 16> AllCRLogicalOps;
   void initialize(MachineFunction &MFParm);
   void collectCRLogicals();
   bool handleCROp(unsigned Idx);
   bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);
   static bool isCRLogical(MachineInstr &MI) {
     unsigned Opc = MI.getOpcode();
     return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR ||
-      Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CREQV ||
-      Opc == PPC::CRANDC || Opc == PPC::CRORC || Opc == PPC::CRSET ||
-      Opc == PPC::CRUNSET || Opc == PPC::CR6SET || Opc == PPC::CR6UNSET;
+           Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CRNOT ||
+           Opc == PPC::CREQV || Opc == PPC::CRANDC || Opc == PPC::CRORC ||
+           Opc == PPC::CRSET || Opc == PPC::CRUNSET || Opc == PPC::CR6SET ||
+           Opc == PPC::CR6UNSET;
   }
   bool simplifyCode() {
     bool Changed = false;
     // Not using a range-based for loop here as the vector may grow while being
     // operated on.
     for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)
       Changed |= handleCROp(i);
     return Changed;

llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll

entry:
   ret i32 %1
 }
 
 define i1 @test_f128(fp128 %a, fp128 %b) #0 {
 ; CHECK-LABEL: test_f128:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscmpuqp cr0, v2, v3
 ; CHECK-NEXT:    crmove 4*cr5+lt, eq
-; CHECK-NEXT:    xscmpuqp cr0, v2, v3
-; CHECK-NEXT:    crmove 4*cr5+gt, eq
-; CHECK-NEXT:    crnor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-NEXT:    crnot 4*cr5+lt, 4*cr5+lt
 ; CHECK-NEXT:    li r4, 0
 ; CHECK-NEXT:    li r3, 1
 ; CHECK-NEXT:    isel r3, r3, r4, 4*cr5+lt
 ; CHECK-NEXT:    blr
 entry:
   %0 = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
   ret i1 %0
 }

llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll

; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ogt", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; SPE-LABEL: test_f32_oge_s:
 ; SPE:       # %bb.0:
-; SPE-NEXT:    efscmplt cr0, r5, r6
-; SPE-NEXT:    efscmplt cr1, r5, r6
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
 ; SPE-NEXT:    efscmpeq cr0, r6, r6
 ; SPE-NEXT:    efscmpeq cr1, r5, r5
-; SPE-NEXT:    crand 4*cr5+gt, 4*cr1+gt, gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; SPE-NEXT:    crand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT:    efscmplt cr0, r5, r6
+; SPE-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oge", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"olt", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; SPE-LABEL: test_f32_ole_s:
 ; SPE:       # %bb.0:
-; SPE-NEXT:    efscmpgt cr0, r5, r6
-; SPE-NEXT:    efscmpgt cr1, r5, r6
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
 ; SPE-NEXT:    efscmpeq cr0, r6, r6
 ; SPE-NEXT:    efscmpeq cr1, r5, r5
-; SPE-NEXT:    crand 4*cr5+gt, 4*cr1+gt, gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; SPE-NEXT:    crand 4*cr5+lt, 4*cr1+gt, gt
+; SPE-NEXT:    efscmpgt cr0, r5, r6
+; SPE-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ole", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ueq", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; SPE-LABEL: test_f32_ugt_s:
 ; SPE:       # %bb.0:
-; SPE-NEXT:    efscmpeq cr0, r6, r6
-; SPE-NEXT:    efscmpeq cr1, r6, r6
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
 ; SPE-NEXT:    efscmpeq cr0, r5, r5
-; SPE-NEXT:    efscmpeq cr1, r5, r5
-; SPE-NEXT:    crnor 4*cr5+gt, gt, 4*cr1+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; SPE-NEXT:    efscmpeq cr1, r6, r6
+; SPE-NEXT:    crnand 4*cr5+lt, 4*cr1+gt, gt
 ; SPE-NEXT:    efscmpgt cr0, r5, r6
 ; SPE-NEXT:    cror 4*cr5+lt, gt, 4*cr5+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ugt", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; SPE-LABEL: test_f32_uge_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    efscmplt cr0, r5, r6
-; SPE-NEXT:    efscmplt cr1, r5, r6
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
-; SPE-NEXT:  # %bb.1:
-; SPE-NEXT:    ori r3, r4, 0
+; SPE-NEXT:    bc 12, gt, .LBB9_1
+; SPE-NEXT:    blr
+; SPE-NEXT:  .LBB9_1:
+; SPE-NEXT:    addi r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uge", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; SPE-LABEL: test_f32_ult_s:
 ; SPE:       # %bb.0:
-; SPE-NEXT:    efscmpeq cr0, r6, r6
-; SPE-NEXT:    efscmpeq cr1, r6, r6
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
 ; SPE-NEXT:    efscmpeq cr0, r5, r5
-; SPE-NEXT:    efscmpeq cr1, r5, r5
-; SPE-NEXT:    crnor 4*cr5+gt, gt, 4*cr1+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; SPE-NEXT:    efscmpeq cr1, r6, r6
+; SPE-NEXT:    crnand 4*cr5+lt, 4*cr1+gt, gt
 ; SPE-NEXT:    efscmplt cr0, r5, r6
 ; SPE-NEXT:    cror 4*cr5+lt, gt, 4*cr5+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ult", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; SPE-LABEL: test_f32_ule_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    efscmpgt cr0, r5, r6
-; SPE-NEXT:    efscmpgt cr1, r5, r6
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
-; SPE-NEXT:  # %bb.1:
-; SPE-NEXT:    ori r3, r4, 0
+; SPE-NEXT:    bc 12, gt, .LBB11_1
+; SPE-NEXT:    blr
+; SPE-NEXT:  .LBB11_1:
+; SPE-NEXT:    addi r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ule", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; SPE-LABEL: test_f32_une_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    efscmpeq cr0, r5, r6
-; SPE-NEXT:    efscmpeq cr1, r5, r6
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
-; SPE-NEXT:  # %bb.1:
-; SPE-NEXT:    ori r3, r4, 0
+; SPE-NEXT:    bc 12, gt, .LBB12_1
+; SPE-NEXT:    blr
+; SPE-NEXT:  .LBB12_1:
+; SPE-NEXT:    addi r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"une", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
 ; SPE-LABEL: test_f32_uno_s:
 ; SPE:       # %bb.0:
-; SPE-NEXT:    efscmpeq cr0, r6, r6
-; SPE-NEXT:    efscmpeq cr1, r6, r6
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
 ; SPE-NEXT:    efscmpeq cr0, r5, r5
-; SPE-NEXT:    efscmpeq cr1, r5, r5
-; SPE-NEXT:    crnor 4*cr5+gt, gt, 4*cr1+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; SPE-NEXT:    efscmpeq cr1, r6, r6
+; SPE-NEXT:    crnand 4*cr5+lt, 4*cr1+gt, gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uno", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ogt", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_oge_s:
 ; SPE:       # %bb.0:
-; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
-; SPE-NEXT:    efdcmplt cr0, r5, r7
-; SPE-NEXT:    efdcmplt cr1, r5, r7
-; SPE-NEXT:    efdcmpeq cr5, r7, r7
-; SPE-NEXT:    efdcmpeq cr6, r5, r5
-; SPE-NEXT:    crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr6+gt, 4*cr5+gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
+; SPE-NEXT:    evmergelo r6, r7, r8
+; SPE-NEXT:    efdcmpeq cr0, r6, r6
+; SPE-NEXT:    efdcmpeq cr1, r5, r5
+; SPE-NEXT:    efdcmplt cr5, r5, r6
+; SPE-NEXT:    crand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT:    crandc 4*cr5+lt, 4*cr6+lt, 4*cr5+gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oge", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"olt", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_ole_s:
 ; SPE:       # %bb.0:
-; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
-; SPE-NEXT:    efdcmpgt cr0, r5, r7
-; SPE-NEXT:    efdcmpgt cr1, r5, r7
-; SPE-NEXT:    efdcmpeq cr5, r7, r7
-; SPE-NEXT:    efdcmpeq cr6, r5, r5
-; SPE-NEXT:    crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr6+gt, 4*cr5+gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
+; SPE-NEXT:    evmergelo r6, r7, r8
+; SPE-NEXT:    efdcmpeq cr0, r6, r6
+; SPE-NEXT:    efdcmpeq cr1, r5, r5
+; SPE-NEXT:    efdcmpgt cr5, r5, r6
+; SPE-NEXT:    crand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT:    crandc 4*cr5+lt, 4*cr6+lt, 4*cr5+gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ole", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ueq", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_ugt_s:
 ; SPE:       # %bb.0:
+; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
-; SPE-NEXT:    evmergelo r6, r7, r8
-; SPE-NEXT:    efdcmpeq cr0, r6, r6
-; SPE-NEXT:    efdcmpeq cr1, r6, r6
-; SPE-NEXT:    efdcmpeq cr5, r5, r5
-; SPE-NEXT:    efdcmpeq cr6, r5, r5
-; SPE-NEXT:    efdcmpgt cr7, r5, r6
-; SPE-NEXT:    crnor 4*cr1+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+lt, 4*cr1+lt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr7+gt, 4*cr5+lt
+; SPE-NEXT:    efdcmpeq cr0, r5, r5
+; SPE-NEXT:    efdcmpeq cr1, r7, r7
+; SPE-NEXT:    efdcmpgt cr5, r5, r7
+; SPE-NEXT:    crnand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr6+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ugt", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_uge_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    efdcmplt cr0, r5, r7
-; SPE-NEXT:    efdcmplt cr1, r5, r7
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
-; SPE-NEXT:  # %bb.1:
-; SPE-NEXT:    ori r3, r4, 0
+; SPE-NEXT:    bc 12, gt, .LBB23_1
+; SPE-NEXT:    blr
+; SPE-NEXT:  .LBB23_1:
+; SPE-NEXT:    addi r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uge", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_ult_s:
 ; SPE:       # %bb.0:
+; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
-; SPE-NEXT:    evmergelo r6, r7, r8
-; SPE-NEXT:    efdcmpeq cr0, r6, r6
-; SPE-NEXT:    efdcmpeq cr1, r6, r6
-; SPE-NEXT:    efdcmpeq cr5, r5, r5
-; SPE-NEXT:    efdcmpeq cr6, r5, r5
-; SPE-NEXT:    efdcmplt cr7, r5, r6
-; SPE-NEXT:    crnor 4*cr1+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+lt, 4*cr1+lt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr7+gt, 4*cr5+lt
+; SPE-NEXT:    efdcmpeq cr0, r5, r5
+; SPE-NEXT:    efdcmpeq cr1, r7, r7
+; SPE-NEXT:    efdcmplt cr5, r5, r7
+; SPE-NEXT:    crnand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr6+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ult", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_ule_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    efdcmpgt cr0, r5, r7
-; SPE-NEXT:    efdcmpgt cr1, r5, r7
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
-; SPE-NEXT:  # %bb.1:
-; SPE-NEXT:    ori r3, r4, 0
+; SPE-NEXT:    bc 12, gt, .LBB25_1
+; SPE-NEXT:    blr
+; SPE-NEXT:  .LBB25_1:
+; SPE-NEXT:    addi r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ule", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_une_s:
 ; SPE:       # %bb.0:
 ; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
 ; SPE-NEXT:    efdcmpeq cr0, r5, r7
-; SPE-NEXT:    efdcmpeq cr1, r5, r7
-; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
-; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
-; SPE-NEXT:  # %bb.1:
-; SPE-NEXT:    ori r3, r4, 0
+; SPE-NEXT:    bc 12, gt, .LBB26_1
+; SPE-NEXT:    blr
+; SPE-NEXT:  .LBB26_1:
+; SPE-NEXT:    addi r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"une", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
 ; SPE-LABEL: test_f64_uno_s:
 ; SPE:       # %bb.0:
+; SPE-NEXT:    evmergelo r7, r7, r8
 ; SPE-NEXT:    evmergelo r5, r5, r6
-; SPE-NEXT:    evmergelo r6, r7, r8
-; SPE-NEXT:    efdcmpeq cr0, r6, r6
-; SPE-NEXT:    efdcmpeq cr1, r6, r6
-; SPE-NEXT:    efdcmpeq cr5, r5, r5
-; SPE-NEXT:    efdcmpeq cr6, r5, r5
-; SPE-NEXT:    crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+lt, 4*cr7+lt
+; SPE-NEXT:    efdcmpeq cr0, r5, r5
+; SPE-NEXT:    efdcmpeq cr1, r7, r7
+; SPE-NEXT:    crnand 4*cr5+lt, 4*cr1+gt, gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
 ; SPE-NEXT:    blr
   %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uno", metadata !"fpexcept.strict") #0
   %res = select i1 %cond, i32 %a, i32 %b
   ret i32 %res
 }
 
 attributes #0 = { strictfp nounwind }
 
 declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)
 declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)

llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ole_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpuqp cr0, v2, v3
-; P9-NEXT:    xscmpuqp cr1, v2, v3
 ; P9-NEXT:    li r3, 1
-; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT:    crnor 4*cr5+gt, gt, 4*cr1+gt
-; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT:    cror 4*cr5+lt, un, gt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ole_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)

 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_oge_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpuqp cr0, v2, v3
-; P9-NEXT:    xscmpuqp cr1, v2, v3
 ; P9-NEXT:    li r3, 1
-; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT:    crnor 4*cr5+gt, lt, 4*cr1+lt
-; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT:    cror 4*cr5+lt, un, lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_oge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)

 ; P8-NEXT:    addi r1, r1, 176
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_one_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpuqp cr0, v2, v3
-; P9-NEXT:    xscmpuqp cr1, v2, v3
 ; P9-NEXT:    li r3, 1
-; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT:    crnor 4*cr5+gt, eq, 4*cr1+eq
-; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT:    cror 4*cr5+lt, un, eq
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_one_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
 ; NOVSX-NEXT:    std r27, -40(r1) # 8-byte Folded Spill

 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ole_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpoqp cr0, v2, v3
-; P9-NEXT:    xscmpoqp cr1, v2, v3
 ; P9-NEXT:    li r3, 1
-; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT:    crnor 4*cr5+gt, gt, 4*cr1+gt
-; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT:    cror 4*cr5+lt, un, gt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ole_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)

 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_oge_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpoqp cr0, v2, v3
-; P9-NEXT:    xscmpoqp cr1, v2, v3
 ; P9-NEXT:    li r3, 1
-; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT:    crnor 4*cr5+gt, lt, 4*cr1+lt
-; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT:    cror 4*cr5+lt, un, lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_oge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)

 ; P8-NEXT:    addi r1, r1, 176
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_one_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpoqp cr0, v2, v3
-; P9-NEXT:    xscmpoqp cr1, v2, v3
 ; P9-NEXT:    li r3, 1
-; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
-; P9-NEXT:    crnor 4*cr5+gt, eq, 4*cr1+eq
-; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT:    cror 4*cr5+lt, un, eq
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_one_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
 ; NOVSX-NEXT:    std r27, -40(r1) # 8-byte Folded Spill