[PowerPC] Remove redundant spill/reload of callee saved vector registers

[tingwang]

Summary

This is AIX part of update after https://reviews.llvm.org/D117225

Fixed the issue that AIX64 with vector pair enabled saw redundant spill/reload of callee saved vector registers.

I will pre-commit the base test case after finalize. Right now the diff shows the error on AIX64

Based on original patch by: Kai Luo

[lkail]

llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll

73–80

Please include all spill slot information for each register.

[tingwang]

Address comments: update test case to include more information.

[tingwang]

Drop change related with CallingConv::AnyReg, which seems not supported on AIX.

[tingwang]

Update base test case:
Use CHECK-LABEL to match function name.

[tingwang]

Added virtual call case to show improvement.

[tingwang]

Update base test case.

[lkail]

LGTM.

llvm/lib/Target/PowerPC/PPCCallingConv.td

 
 def CSR_SVR64_ColdCC_VSRP : CalleeSavedRegs<(add CSR_SVR64_ColdCC,
                                             (sub CSR_ALL_VSRP, VSRp17))>;
 
 def CSR_SVR64_ColdCC_R2_VSRP : CalleeSavedRegs<(add CSR_SVR64_ColdCC_VSRP, X2)>;
 
 def CSR_64_AllRegs_VSRP :
   CalleeSavedRegs<(add CSR_64_AllRegs_VSX, CSR_ALL_VSRP)>;
+
+def CSR_AIX64_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;
+
+def CSR_AIX64_R2_VSRP : CalleeSavedRegs<(add CSR_AIX64_VSRP, X2)>;
+
+def CSR_AIX32_VSRP : CalleeSavedRegs<(add CSR_AIX32_Altivec, CSR_VSRP)>;

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
     else if (Subtarget.hasAltivec())
       return CSR_SVR32_ColdCC_Altivec_SaveList;
     else if (Subtarget.hasSPE())
       return CSR_SVR32_ColdCC_SPE_SaveList;
     return CSR_SVR32_ColdCC_SaveList;
   }
   // Standard calling convention CSRs.
   if (TM.isPPC64()) {
-    if (Subtarget.pairedVectorMemops())
+    if (Subtarget.pairedVectorMemops()) {
+      if (Subtarget.isAIXABI()) {
+        if (!TM.getAIXExtendedAltivecABI())
+          return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
+        return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
+      }
       return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
+    }
     if (Subtarget.hasAltivec() &&
         (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
       return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
                     : CSR_PPC64_Altivec_SaveList;
     }
     return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
   }
   // 32-bit targets.
   if (Subtarget.isAIXABI()) {
+    if (Subtarget.pairedVectorMemops())
+      return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList
+                                           : CSR_AIX32_SaveList;
     if (Subtarget.hasAltivec())
       return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
                                            : CSR_AIX32_SaveList;
     return CSR_AIX32_SaveList;
   }
   if (Subtarget.pairedVectorMemops())
     return CSR_SVR432_VSRP_SaveList;
   if (Subtarget.hasAltivec())
if (Subtarget.hasAltivec()) {
       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
         return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask;
       return CSR_64_AllRegs_Altivec_RegMask;
     }
     return CSR_64_AllRegs_RegMask;
   }
 
   if (Subtarget.isAIXABI()) {
+    if (Subtarget.pairedVectorMemops()) {
+      if (!TM.getAIXExtendedAltivecABI())
+        return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
+      return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask;
+    }
     return TM.isPPC64()
                ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
                       ? CSR_PPC64_Altivec_RegMask
                       : CSR_PPC64_RegMask)
                : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
                       ? CSR_AIX32_Altivec_RegMask
                       : CSR_AIX32_RegMask);
   }

llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll

 ; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prologepilog -verify-machineinstrs < %s | \
 ; RUN: FileCheck --check-prefix=CHECK %s
 ; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
 ; RUN: FileCheck --check-prefix=CHECK-VEXT %s
 
-; Error pattern will be fixed in https://reviews.llvm.org/D133466
 ; CHECK-LABEL: name: foo
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v31'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v30'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v29'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v28'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v27'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v26'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v25'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v24'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v23'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v22'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v21'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v20'
+; CHECK-NOT: spill-slot
+; CHECK-NOT: callee-saved-register: '$v31'
+; CHECK-NOT: callee-saved-register: '$v30'
+; CHECK-NOT: callee-saved-register: '$v29'
+; CHECK-NOT: callee-saved-register: '$v28'
+; CHECK-NOT: callee-saved-register: '$v27'
+; CHECK-NOT: callee-saved-register: '$v26'
+; CHECK-NOT: callee-saved-register: '$v25'
+; CHECK-NOT: callee-saved-register: '$v24'
+; CHECK-NOT: callee-saved-register: '$v23'
+; CHECK-NOT: callee-saved-register: '$v22'
+; CHECK-NOT: callee-saved-register: '$v21'
+; CHECK-NOT: callee-saved-register: '$v20'
 
 ; CHECK-VEXT-LABEL: name: foo
 ; CHECK-VEXT-NOT: spill-slot
 ; CHECK-VEXT-NOT: callee-saved-register: '$v31'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v30'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v29'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v28'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v27'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v26'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v25'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v24'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v23'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v22'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v21'
 ; CHECK-VEXT-NOT: callee-saved-register: '$v20'
 define void @foo() {
 entry:
   call void @bar(i32 0)
   ret void
 }
 
-; Error pattern will be fixed in https://reviews.llvm.org/D133466
 ; CHECK-LABEL: name: spill
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v31'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v30'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v29'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v28'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v27'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v26'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v25'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v24'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v23'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v22'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v21'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v20'
+; CHECK-NOT: spill-slot
+; CHECK-NOT: callee-saved-register: '$v31'
+; CHECK-NOT: callee-saved-register: '$v30'
+; CHECK-NOT: callee-saved-register: '$v29'
+; CHECK-NOT: callee-saved-register: '$v28'
+; CHECK-NOT: callee-saved-register: '$v27'
+; CHECK-NOT: callee-saved-register: '$v26'
+; CHECK-NOT: callee-saved-register: '$v25'
+; CHECK-NOT: callee-saved-register: '$v24'
+; CHECK-NOT: callee-saved-register: '$v23'
+; CHECK-NOT: callee-saved-register: '$v22'
+; CHECK-NOT: callee-saved-register: '$v21'
+; CHECK-NOT: callee-saved-register: '$v20'
 
 ; CHECK-VEXT-LABEL: name: spill
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v31'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v30'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v29'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v28'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v27'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v26'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v25'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v24'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v23'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v22'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v21'
 ; CHECK-VEXT: spill-slot
 ; CHECK-VEXT-NEXT: callee-saved-register: '$v20'
 define void @spill() {
 entry:
   call void asm sideeffect "nop", "~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
   call void @bar(i32 0)
   ret void
 }
 
 declare void @bar(i32)

llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10  < %s | \
 ; RUN: FileCheck --check-prefix=CHECK %s
 ; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi < %s | \
 ; RUN: FileCheck --check-prefix=CHECK-VEXT %s
 
 define dso_local noundef signext i32 @virtualCall(ptr noundef %b) #0 {
 ; CHECK-LABEL: virtualCall:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    std 0, 16(1)
-; CHECK-NEXT:    stdu 1, -320(1)
-; CHECK-NEXT:    stxv 52, 128(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 53, 144(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 54, 160(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 55, 176(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 56, 192(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 57, 208(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 58, 224(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 59, 240(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 60, 256(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 61, 272(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 62, 288(1) # 16-byte Folded Spill
-; CHECK-NEXT:    stxv 63, 304(1) # 16-byte Folded Spill
+; CHECK-NEXT:    stdu 1, -128(1)
 ; CHECK-NEXT:    std 3, 120(1)
 ; CHECK-NEXT:    ld 3, 120(1)
 ; CHECK-NEXT:    ld 4, 0(3)
 ; CHECK-NEXT:    ld 4, 0(4)
 ; CHECK-NEXT:    mr 5, 2
 ; CHECK-NEXT:    std 5, 40(1)
 ; CHECK-NEXT:    ld 5, 8(4)
 ; CHECK-NEXT:    ld 11, 16(4)
 ; CHECK-NEXT:    ld 4, 0(4)
 ; CHECK-NEXT:    mr 2, 5
 ; CHECK-NEXT:    mtctr 4
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    ld 2, 40(1)
 ; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $x3
 ; CHECK-NEXT:    extsw 3, 3
-; CHECK-NEXT:    lxv 63, 304(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 62, 288(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 61, 272(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 60, 256(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 59, 240(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 58, 224(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 57, 208(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 56, 192(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 55, 176(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 54, 160(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 53, 144(1) # 16-byte Folded Reload
-; CHECK-NEXT:    lxv 52, 128(1) # 16-byte Folded Reload
-; CHECK-NEXT:    addi 1, 1, 320
+; CHECK-NEXT:    addi 1, 1, 128
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-VEXT-LABEL: virtualCall:
 ; CHECK-VEXT:       # %bb.0: # %entry
 ; CHECK-VEXT-NEXT:    mflr 0
 ; CHECK-VEXT-NEXT:    std 0, 16(1)