[mlir][spirv] Define various spv.GroupNonUniformShuffle ops

[antiagainst]

Fix examples

[kuhar]

LGTM

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td

676

nit: there seem to be some duplicated spaces in this description. Also below, e.g., between Id and must.

[antiagainst]

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td

676

These are automatically pulled from the HTML spec; so we need to fix the generator for it. I won't bother for now.

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

class SPV_OpCode<string name, int val> {
   string opname = name;
 
   // Opcode associated with the name
   int opcode = val;
 }
 
 // Begin opcode section. Generated from SPIR-V spec; DO NOT MODIFY!
 
-def SPV_OC_OpNop                       : I32EnumAttrCase<"OpNop", 0>;
-def SPV_OC_OpUndef                     : I32EnumAttrCase<"OpUndef", 1>;
-def SPV_OC_OpSourceContinued           : I32EnumAttrCase<"OpSourceContinued", 2>;
-def SPV_OC_OpSource                    : I32EnumAttrCase<"OpSource", 3>;
-def SPV_OC_OpSourceExtension           : I32EnumAttrCase<"OpSourceExtension", 4>;
-def SPV_OC_OpName                      : I32EnumAttrCase<"OpName", 5>;
-def SPV_OC_OpMemberName                : I32EnumAttrCase<"OpMemberName", 6>;
-def SPV_OC_OpString                    : I32EnumAttrCase<"OpString", 7>;
-def SPV_OC_OpLine                      : I32EnumAttrCase<"OpLine", 8>;
-def SPV_OC_OpExtension                 : I32EnumAttrCase<"OpExtension", 10>;
-def SPV_OC_OpExtInstImport             : I32EnumAttrCase<"OpExtInstImport", 11>;
-def SPV_OC_OpExtInst                   : I32EnumAttrCase<"OpExtInst", 12>;
-def SPV_OC_OpMemoryModel               : I32EnumAttrCase<"OpMemoryModel", 14>;
-def SPV_OC_OpEntryPoint                : I32EnumAttrCase<"OpEntryPoint", 15>;
-def SPV_OC_OpExecutionMode             : I32EnumAttrCase<"OpExecutionMode", 16>;
-def SPV_OC_OpCapability                : I32EnumAttrCase<"OpCapability", 17>;
-def SPV_OC_OpTypeVoid                  : I32EnumAttrCase<"OpTypeVoid", 19>;
-def SPV_OC_OpTypeBool                  : I32EnumAttrCase<"OpTypeBool", 20>;
-def SPV_OC_OpTypeInt                   : I32EnumAttrCase<"OpTypeInt", 21>;
-def SPV_OC_OpTypeFloat                 : I32EnumAttrCase<"OpTypeFloat", 22>;
-def SPV_OC_OpTypeVector                : I32EnumAttrCase<"OpTypeVector", 23>;
-def SPV_OC_OpTypeMatrix                : I32EnumAttrCase<"OpTypeMatrix", 24>;
-def SPV_OC_OpTypeImage                 : I32EnumAttrCase<"OpTypeImage", 25>;
-def SPV_OC_OpTypeSampledImage          : I32EnumAttrCase<"OpTypeSampledImage", 27>;
-def SPV_OC_OpTypeArray                 : I32EnumAttrCase<"OpTypeArray", 28>;
-def SPV_OC_OpTypeRuntimeArray          : I32EnumAttrCase<"OpTypeRuntimeArray", 29>;
-def SPV_OC_OpTypeStruct                : I32EnumAttrCase<"OpTypeStruct", 30>;
-def SPV_OC_OpTypePointer               : I32EnumAttrCase<"OpTypePointer", 32>;
-def SPV_OC_OpTypeFunction              : I32EnumAttrCase<"OpTypeFunction", 33>;
-def SPV_OC_OpTypeForwardPointer        : I32EnumAttrCase<"OpTypeForwardPointer", 39>;
-def SPV_OC_OpConstantTrue              : I32EnumAttrCase<"OpConstantTrue", 41>;
-def SPV_OC_OpConstantFalse             : I32EnumAttrCase<"OpConstantFalse", 42>;
-def SPV_OC_OpConstant                  : I32EnumAttrCase<"OpConstant", 43>;
-def SPV_OC_OpConstantComposite         : I32EnumAttrCase<"OpConstantComposite", 44>;
-def SPV_OC_OpConstantNull              : I32EnumAttrCase<"OpConstantNull", 46>;
-def SPV_OC_OpSpecConstantTrue          : I32EnumAttrCase<"OpSpecConstantTrue", 48>;
-def SPV_OC_OpSpecConstantFalse         : I32EnumAttrCase<"OpSpecConstantFalse", 49>;
-def SPV_OC_OpSpecConstant              : I32EnumAttrCase<"OpSpecConstant", 50>;
-def SPV_OC_OpSpecConstantComposite     : I32EnumAttrCase<"OpSpecConstantComposite", 51>;
-def SPV_OC_OpSpecConstantOp            : I32EnumAttrCase<"OpSpecConstantOp", 52>;
-def SPV_OC_OpFunction                  : I32EnumAttrCase<"OpFunction", 54>;
-def SPV_OC_OpFunctionParameter         : I32EnumAttrCase<"OpFunctionParameter", 55>;
-def SPV_OC_OpFunctionEnd               : I32EnumAttrCase<"OpFunctionEnd", 56>;
-def SPV_OC_OpFunctionCall              : I32EnumAttrCase<"OpFunctionCall", 57>;
-def SPV_OC_OpVariable                  : I32EnumAttrCase<"OpVariable", 59>;
-def SPV_OC_OpLoad                      : I32EnumAttrCase<"OpLoad", 61>;
-def SPV_OC_OpStore                     : I32EnumAttrCase<"OpStore", 62>;
-def SPV_OC_OpCopyMemory                : I32EnumAttrCase<"OpCopyMemory", 63>;
-def SPV_OC_OpAccessChain               : I32EnumAttrCase<"OpAccessChain", 65>;
-def SPV_OC_OpPtrAccessChain            : I32EnumAttrCase<"OpPtrAccessChain", 67>;
-def SPV_OC_OpInBoundsPtrAccessChain    : I32EnumAttrCase<"OpInBoundsPtrAccessChain", 70>;
-def SPV_OC_OpDecorate                  : I32EnumAttrCase<"OpDecorate", 71>;
-def SPV_OC_OpMemberDecorate            : I32EnumAttrCase<"OpMemberDecorate", 72>;
-def SPV_OC_OpVectorExtractDynamic      : I32EnumAttrCase<"OpVectorExtractDynamic", 77>;
-def SPV_OC_OpVectorInsertDynamic       : I32EnumAttrCase<"OpVectorInsertDynamic", 78>;
-def SPV_OC_OpVectorShuffle             : I32EnumAttrCase<"OpVectorShuffle", 79>;
-def SPV_OC_OpCompositeConstruct        : I32EnumAttrCase<"OpCompositeConstruct", 80>;
-def SPV_OC_OpCompositeExtract          : I32EnumAttrCase<"OpCompositeExtract", 81>;
-def SPV_OC_OpCompositeInsert           : I32EnumAttrCase<"OpCompositeInsert", 82>;
-def SPV_OC_OpTranspose                 : I32EnumAttrCase<"OpTranspose", 84>;
-def SPV_OC_OpImageDrefGather           : I32EnumAttrCase<"OpImageDrefGather", 97>;
-def SPV_OC_OpImage                     : I32EnumAttrCase<"OpImage", 100>;
-def SPV_OC_OpImageQuerySize            : I32EnumAttrCase<"OpImageQuerySize", 104>;
-def SPV_OC_OpConvertFToU               : I32EnumAttrCase<"OpConvertFToU", 109>;
-def SPV_OC_OpConvertFToS               : I32EnumAttrCase<"OpConvertFToS", 110>;
-def SPV_OC_OpConvertSToF               : I32EnumAttrCase<"OpConvertSToF", 111>;
-def SPV_OC_OpConvertUToF               : I32EnumAttrCase<"OpConvertUToF", 112>;
-def SPV_OC_OpUConvert                  : I32EnumAttrCase<"OpUConvert", 113>;
-def SPV_OC_OpSConvert                  : I32EnumAttrCase<"OpSConvert", 114>;
-def SPV_OC_OpFConvert                  : I32EnumAttrCase<"OpFConvert", 115>;
-def SPV_OC_OpBitcast                   : I32EnumAttrCase<"OpBitcast", 124>;
-def SPV_OC_OpSNegate                   : I32EnumAttrCase<"OpSNegate", 126>;
-def SPV_OC_OpFNegate                   : I32EnumAttrCase<"OpFNegate", 127>;
-def SPV_OC_OpIAdd                      : I32EnumAttrCase<"OpIAdd", 128>;
-def SPV_OC_OpFAdd                      : I32EnumAttrCase<"OpFAdd", 129>;
-def SPV_OC_OpISub                      : I32EnumAttrCase<"OpISub", 130>;
-def SPV_OC_OpFSub                      : I32EnumAttrCase<"OpFSub", 131>;
-def SPV_OC_OpIMul                      : I32EnumAttrCase<"OpIMul", 132>;
-def SPV_OC_OpFMul                      : I32EnumAttrCase<"OpFMul", 133>;
-def SPV_OC_OpUDiv                      : I32EnumAttrCase<"OpUDiv", 134>;
-def SPV_OC_OpSDiv                      : I32EnumAttrCase<"OpSDiv", 135>;
-def SPV_OC_OpFDiv                      : I32EnumAttrCase<"OpFDiv", 136>;
-def SPV_OC_OpUMod                      : I32EnumAttrCase<"OpUMod", 137>;
-def SPV_OC_OpSRem                      : I32EnumAttrCase<"OpSRem", 138>;
-def SPV_OC_OpSMod                      : I32EnumAttrCase<"OpSMod", 139>;
-def SPV_OC_OpFRem                      : I32EnumAttrCase<"OpFRem", 140>;
-def SPV_OC_OpFMod                      : I32EnumAttrCase<"OpFMod", 141>;
-def SPV_OC_OpVectorTimesScalar         : I32EnumAttrCase<"OpVectorTimesScalar", 142>;
-def SPV_OC_OpMatrixTimesScalar         : I32EnumAttrCase<"OpMatrixTimesScalar", 143>;
-def SPV_OC_OpMatrixTimesMatrix         : I32EnumAttrCase<"OpMatrixTimesMatrix", 146>;
-def SPV_OC_OpIAddCarry                 : I32EnumAttrCase<"OpIAddCarry", 149>;
-def SPV_OC_OpISubBorrow                : I32EnumAttrCase<"OpISubBorrow", 150>;
-def SPV_OC_OpIsNan                     : I32EnumAttrCase<"OpIsNan", 156>;
-def SPV_OC_OpIsInf                     : I32EnumAttrCase<"OpIsInf", 157>;
-def SPV_OC_OpOrdered                   : I32EnumAttrCase<"OpOrdered", 162>;
-def SPV_OC_OpUnordered                 : I32EnumAttrCase<"OpUnordered", 163>;
-def SPV_OC_OpLogicalEqual              : I32EnumAttrCase<"OpLogicalEqual", 164>;
-def SPV_OC_OpLogicalNotEqual           : I32EnumAttrCase<"OpLogicalNotEqual", 165>;
-def SPV_OC_OpLogicalOr                 : I32EnumAttrCase<"OpLogicalOr", 166>;
-def SPV_OC_OpLogicalAnd                : I32EnumAttrCase<"OpLogicalAnd", 167>;
-def SPV_OC_OpLogicalNot                : I32EnumAttrCase<"OpLogicalNot", 168>;
-def SPV_OC_OpSelect                    : I32EnumAttrCase<"OpSelect", 169>;
-def SPV_OC_OpIEqual                    : I32EnumAttrCase<"OpIEqual", 170>;
-def SPV_OC_OpINotEqual                 : I32EnumAttrCase<"OpINotEqual", 171>;
-def SPV_OC_OpUGreaterThan              : I32EnumAttrCase<"OpUGreaterThan", 172>;
-def SPV_OC_OpSGreaterThan              : I32EnumAttrCase<"OpSGreaterThan", 173>;
-def SPV_OC_OpUGreaterThanEqual         : I32EnumAttrCase<"OpUGreaterThanEqual", 174>;
-def SPV_OC_OpSGreaterThanEqual         : I32EnumAttrCase<"OpSGreaterThanEqual", 175>;
-def SPV_OC_OpULessThan                 : I32EnumAttrCase<"OpULessThan", 176>;
-def SPV_OC_OpSLessThan                 : I32EnumAttrCase<"OpSLessThan", 177>;
-def SPV_OC_OpULessThanEqual            : I32EnumAttrCase<"OpULessThanEqual", 178>;
-def SPV_OC_OpSLessThanEqual            : I32EnumAttrCase<"OpSLessThanEqual", 179>;
-def SPV_OC_OpFOrdEqual                 : I32EnumAttrCase<"OpFOrdEqual", 180>;
-def SPV_OC_OpFUnordEqual               : I32EnumAttrCase<"OpFUnordEqual", 181>;
-def SPV_OC_OpFOrdNotEqual              : I32EnumAttrCase<"OpFOrdNotEqual", 182>;
-def SPV_OC_OpFUnordNotEqual            : I32EnumAttrCase<"OpFUnordNotEqual", 183>;
-def SPV_OC_OpFOrdLessThan              : I32EnumAttrCase<"OpFOrdLessThan", 184>;
-def SPV_OC_OpFUnordLessThan            : I32EnumAttrCase<"OpFUnordLessThan", 185>;
-def SPV_OC_OpFOrdGreaterThan           : I32EnumAttrCase<"OpFOrdGreaterThan", 186>;
-def SPV_OC_OpFUnordGreaterThan         : I32EnumAttrCase<"OpFUnordGreaterThan", 187>;
-def SPV_OC_OpFOrdLessThanEqual         : I32EnumAttrCase<"OpFOrdLessThanEqual", 188>;
-def SPV_OC_OpFUnordLessThanEqual       : I32EnumAttrCase<"OpFUnordLessThanEqual", 189>;
-def SPV_OC_OpFOrdGreaterThanEqual      : I32EnumAttrCase<"OpFOrdGreaterThanEqual", 190>;
-def SPV_OC_OpFUnordGreaterThanEqual    : I32EnumAttrCase<"OpFUnordGreaterThanEqual", 191>;
-def SPV_OC_OpShiftRightLogical         : I32EnumAttrCase<"OpShiftRightLogical", 194>;
-def SPV_OC_OpShiftRightArithmetic      : I32EnumAttrCase<"OpShiftRightArithmetic", 195>;
-def SPV_OC_OpShiftLeftLogical          : I32EnumAttrCase<"OpShiftLeftLogical", 196>;
-def SPV_OC_OpBitwiseOr                 : I32EnumAttrCase<"OpBitwiseOr", 197>;
-def SPV_OC_OpBitwiseXor                : I32EnumAttrCase<"OpBitwiseXor", 198>;
-def SPV_OC_OpBitwiseAnd                : I32EnumAttrCase<"OpBitwiseAnd", 199>;
-def SPV_OC_OpNot                       : I32EnumAttrCase<"OpNot", 200>;
-def SPV_OC_OpBitFieldInsert            : I32EnumAttrCase<"OpBitFieldInsert", 201>;
-def SPV_OC_OpBitFieldSExtract          : I32EnumAttrCase<"OpBitFieldSExtract", 202>;
-def SPV_OC_OpBitFieldUExtract          : I32EnumAttrCase<"OpBitFieldUExtract", 203>;
-def SPV_OC_OpBitReverse                : I32EnumAttrCase<"OpBitReverse", 204>;
-def SPV_OC_OpBitCount                  : I32EnumAttrCase<"OpBitCount", 205>;
-def SPV_OC_OpControlBarrier            : I32EnumAttrCase<"OpControlBarrier", 224>;
-def SPV_OC_OpMemoryBarrier             : I32EnumAttrCase<"OpMemoryBarrier", 225>;
-def SPV_OC_OpAtomicExchange            : I32EnumAttrCase<"OpAtomicExchange", 229>;
-def SPV_OC_OpAtomicCompareExchange     : I32EnumAttrCase<"OpAtomicCompareExchange", 230>;
-def SPV_OC_OpAtomicCompareExchangeWeak : I32EnumAttrCase<"OpAtomicCompareExchangeWeak", 231>;
-def SPV_OC_OpAtomicIIncrement          : I32EnumAttrCase<"OpAtomicIIncrement", 232>;
-def SPV_OC_OpAtomicIDecrement          : I32EnumAttrCase<"OpAtomicIDecrement", 233>;
-def SPV_OC_OpAtomicIAdd                : I32EnumAttrCase<"OpAtomicIAdd", 234>;
-def SPV_OC_OpAtomicISub                : I32EnumAttrCase<"OpAtomicISub", 235>;
-def SPV_OC_OpAtomicSMin                : I32EnumAttrCase<"OpAtomicSMin", 236>;
-def SPV_OC_OpAtomicUMin                : I32EnumAttrCase<"OpAtomicUMin", 237>;
-def SPV_OC_OpAtomicSMax                : I32EnumAttrCase<"OpAtomicSMax", 238>;
-def SPV_OC_OpAtomicUMax                : I32EnumAttrCase<"OpAtomicUMax", 239>;
-def SPV_OC_OpAtomicAnd                 : I32EnumAttrCase<"OpAtomicAnd", 240>;
-def SPV_OC_OpAtomicOr                  : I32EnumAttrCase<"OpAtomicOr", 241>;
-def SPV_OC_OpAtomicXor                 : I32EnumAttrCase<"OpAtomicXor", 242>;
-def SPV_OC_OpPhi                       : I32EnumAttrCase<"OpPhi", 245>;
-def SPV_OC_OpLoopMerge                 : I32EnumAttrCase<"OpLoopMerge", 246>;
-def SPV_OC_OpSelectionMerge            : I32EnumAttrCase<"OpSelectionMerge", 247>;
-def SPV_OC_OpLabel                     : I32EnumAttrCase<"OpLabel", 248>;
-def SPV_OC_OpBranch                    : I32EnumAttrCase<"OpBranch", 249>;
-def SPV_OC_OpBranchConditional         : I32EnumAttrCase<"OpBranchConditional", 250>;
-def SPV_OC_OpReturn                    : I32EnumAttrCase<"OpReturn", 253>;
-def SPV_OC_OpReturnValue               : I32EnumAttrCase<"OpReturnValue", 254>;
-def SPV_OC_OpUnreachable               : I32EnumAttrCase<"OpUnreachable", 255>;
-def SPV_OC_OpGroupBroadcast            : I32EnumAttrCase<"OpGroupBroadcast", 263>;
-def SPV_OC_OpNoLine                    : I32EnumAttrCase<"OpNoLine", 317>;
-def SPV_OC_OpModuleProcessed           : I32EnumAttrCase<"OpModuleProcessed", 330>;
-def SPV_OC_OpGroupNonUniformElect      : I32EnumAttrCase<"OpGroupNonUniformElect", 333>;
-def SPV_OC_OpGroupNonUniformBroadcast  : I32EnumAttrCase<"OpGroupNonUniformBroadcast", 337>;
-def SPV_OC_OpGroupNonUniformBallot     : I32EnumAttrCase<"OpGroupNonUniformBallot", 339>;
-def SPV_OC_OpGroupNonUniformIAdd       : I32EnumAttrCase<"OpGroupNonUniformIAdd", 349>;
-def SPV_OC_OpGroupNonUniformFAdd       : I32EnumAttrCase<"OpGroupNonUniformFAdd", 350>;
-def SPV_OC_OpGroupNonUniformIMul       : I32EnumAttrCase<"OpGroupNonUniformIMul", 351>;
-def SPV_OC_OpGroupNonUniformFMul       : I32EnumAttrCase<"OpGroupNonUniformFMul", 352>;
-def SPV_OC_OpGroupNonUniformSMin       : I32EnumAttrCase<"OpGroupNonUniformSMin", 353>;
-def SPV_OC_OpGroupNonUniformUMin       : I32EnumAttrCase<"OpGroupNonUniformUMin", 354>;
-def SPV_OC_OpGroupNonUniformFMin       : I32EnumAttrCase<"OpGroupNonUniformFMin", 355>;
-def SPV_OC_OpGroupNonUniformSMax       : I32EnumAttrCase<"OpGroupNonUniformSMax", 356>;
-def SPV_OC_OpGroupNonUniformUMax       : I32EnumAttrCase<"OpGroupNonUniformUMax", 357>;
-def SPV_OC_OpGroupNonUniformFMax       : I32EnumAttrCase<"OpGroupNonUniformFMax", 358>;
-def SPV_OC_OpSubgroupBallotKHR         : I32EnumAttrCase<"OpSubgroupBallotKHR", 4421>;
-def SPV_OC_OpTypeCooperativeMatrixNV   : I32EnumAttrCase<"OpTypeCooperativeMatrixNV", 5358>;
-def SPV_OC_OpCooperativeMatrixLoadNV   : I32EnumAttrCase<"OpCooperativeMatrixLoadNV", 5359>;
-def SPV_OC_OpCooperativeMatrixStoreNV  : I32EnumAttrCase<"OpCooperativeMatrixStoreNV", 5360>;
-def SPV_OC_OpCooperativeMatrixMulAddNV : I32EnumAttrCase<"OpCooperativeMatrixMulAddNV", 5361>;
-def SPV_OC_OpCooperativeMatrixLengthNV : I32EnumAttrCase<"OpCooperativeMatrixLengthNV", 5362>;
-def SPV_OC_OpSubgroupBlockReadINTEL    : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>;
-def SPV_OC_OpSubgroupBlockWriteINTEL   : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>;
-def SPV_OC_OpAssumeTrueKHR             : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>;
-def SPV_OC_OpAtomicFAddEXT             : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
-def SPV_OC_OpTypeJointMatrixINTEL      : I32EnumAttrCase<"OpTypeJointMatrixINTEL", 6119>;
-def SPV_OC_OpJointMatrixLoadINTEL      : I32EnumAttrCase<"OpJointMatrixLoadINTEL", 6120>;
-def SPV_OC_OpJointMatrixStoreINTEL     : I32EnumAttrCase<"OpJointMatrixStoreINTEL", 6121>;
-def SPV_OC_OpJointMatrixMadINTEL       : I32EnumAttrCase<"OpJointMatrixMadINTEL", 6122>;
+def SPV_OC_OpNop                        : I32EnumAttrCase<"OpNop", 0>;
+def SPV_OC_OpUndef                      : I32EnumAttrCase<"OpUndef", 1>;
+def SPV_OC_OpSourceContinued            : I32EnumAttrCase<"OpSourceContinued", 2>;
+def SPV_OC_OpSource                     : I32EnumAttrCase<"OpSource", 3>;
+def SPV_OC_OpSourceExtension            : I32EnumAttrCase<"OpSourceExtension", 4>;
+def SPV_OC_OpName                       : I32EnumAttrCase<"OpName", 5>;
+def SPV_OC_OpMemberName                 : I32EnumAttrCase<"OpMemberName", 6>;
+def SPV_OC_OpString                     : I32EnumAttrCase<"OpString", 7>;
+def SPV_OC_OpLine                       : I32EnumAttrCase<"OpLine", 8>;
+def SPV_OC_OpExtension                  : I32EnumAttrCase<"OpExtension", 10>;
+def SPV_OC_OpExtInstImport              : I32EnumAttrCase<"OpExtInstImport", 11>;
+def SPV_OC_OpExtInst                    : I32EnumAttrCase<"OpExtInst", 12>;
+def SPV_OC_OpMemoryModel                : I32EnumAttrCase<"OpMemoryModel", 14>;
+def SPV_OC_OpEntryPoint                 : I32EnumAttrCase<"OpEntryPoint", 15>;
+def SPV_OC_OpExecutionMode              : I32EnumAttrCase<"OpExecutionMode", 16>;
+def SPV_OC_OpCapability                 : I32EnumAttrCase<"OpCapability", 17>;
+def SPV_OC_OpTypeVoid                   : I32EnumAttrCase<"OpTypeVoid", 19>;
+def SPV_OC_OpTypeBool                   : I32EnumAttrCase<"OpTypeBool", 20>;
+def SPV_OC_OpTypeInt                    : I32EnumAttrCase<"OpTypeInt", 21>;
+def SPV_OC_OpTypeFloat                  : I32EnumAttrCase<"OpTypeFloat", 22>;
+def SPV_OC_OpTypeVector                 : I32EnumAttrCase<"OpTypeVector", 23>;
+def SPV_OC_OpTypeMatrix                 : I32EnumAttrCase<"OpTypeMatrix", 24>;
+def SPV_OC_OpTypeImage                  : I32EnumAttrCase<"OpTypeImage", 25>;
+def SPV_OC_OpTypeSampledImage           : I32EnumAttrCase<"OpTypeSampledImage", 27>;
+def SPV_OC_OpTypeArray                  : I32EnumAttrCase<"OpTypeArray", 28>;
+def SPV_OC_OpTypeRuntimeArray           : I32EnumAttrCase<"OpTypeRuntimeArray", 29>;
+def SPV_OC_OpTypeStruct                 : I32EnumAttrCase<"OpTypeStruct", 30>;
+def SPV_OC_OpTypePointer                : I32EnumAttrCase<"OpTypePointer", 32>;
+def SPV_OC_OpTypeFunction               : I32EnumAttrCase<"OpTypeFunction", 33>;
+def SPV_OC_OpTypeForwardPointer         : I32EnumAttrCase<"OpTypeForwardPointer", 39>;
+def SPV_OC_OpConstantTrue               : I32EnumAttrCase<"OpConstantTrue", 41>;
+def SPV_OC_OpConstantFalse              : I32EnumAttrCase<"OpConstantFalse", 42>;
+def SPV_OC_OpConstant                   : I32EnumAttrCase<"OpConstant", 43>;
+def SPV_OC_OpConstantComposite          : I32EnumAttrCase<"OpConstantComposite", 44>;
+def SPV_OC_OpConstantNull               : I32EnumAttrCase<"OpConstantNull", 46>;
+def SPV_OC_OpSpecConstantTrue           : I32EnumAttrCase<"OpSpecConstantTrue", 48>;
+def SPV_OC_OpSpecConstantFalse          : I32EnumAttrCase<"OpSpecConstantFalse", 49>;
+def SPV_OC_OpSpecConstant               : I32EnumAttrCase<"OpSpecConstant", 50>;
+def SPV_OC_OpSpecConstantComposite      : I32EnumAttrCase<"OpSpecConstantComposite", 51>;
+def SPV_OC_OpSpecConstantOp             : I32EnumAttrCase<"OpSpecConstantOp", 52>;
+def SPV_OC_OpFunction                   : I32EnumAttrCase<"OpFunction", 54>;
+def SPV_OC_OpFunctionParameter          : I32EnumAttrCase<"OpFunctionParameter", 55>;
+def SPV_OC_OpFunctionEnd                : I32EnumAttrCase<"OpFunctionEnd", 56>;
+def SPV_OC_OpFunctionCall               : I32EnumAttrCase<"OpFunctionCall", 57>;
+def SPV_OC_OpVariable                   : I32EnumAttrCase<"OpVariable", 59>;
+def SPV_OC_OpLoad                       : I32EnumAttrCase<"OpLoad", 61>;
+def SPV_OC_OpStore                      : I32EnumAttrCase<"OpStore", 62>;
+def SPV_OC_OpCopyMemory                 : I32EnumAttrCase<"OpCopyMemory", 63>;
+def SPV_OC_OpAccessChain                : I32EnumAttrCase<"OpAccessChain", 65>;
+def SPV_OC_OpPtrAccessChain             : I32EnumAttrCase<"OpPtrAccessChain", 67>;
+def SPV_OC_OpInBoundsPtrAccessChain     : I32EnumAttrCase<"OpInBoundsPtrAccessChain", 70>;
+def SPV_OC_OpDecorate                   : I32EnumAttrCase<"OpDecorate", 71>;
+def SPV_OC_OpMemberDecorate             : I32EnumAttrCase<"OpMemberDecorate", 72>;
+def SPV_OC_OpVectorExtractDynamic       : I32EnumAttrCase<"OpVectorExtractDynamic", 77>;
+def SPV_OC_OpVectorInsertDynamic        : I32EnumAttrCase<"OpVectorInsertDynamic", 78>;
+def SPV_OC_OpVectorShuffle              : I32EnumAttrCase<"OpVectorShuffle", 79>;
+def SPV_OC_OpCompositeConstruct         : I32EnumAttrCase<"OpCompositeConstruct", 80>;
+def SPV_OC_OpCompositeExtract           : I32EnumAttrCase<"OpCompositeExtract", 81>;
+def SPV_OC_OpCompositeInsert            : I32EnumAttrCase<"OpCompositeInsert", 82>;
+def SPV_OC_OpTranspose                  : I32EnumAttrCase<"OpTranspose", 84>;
+def SPV_OC_OpImageDrefGather            : I32EnumAttrCase<"OpImageDrefGather", 97>;
+def SPV_OC_OpImage                      : I32EnumAttrCase<"OpImage", 100>;
+def SPV_OC_OpImageQuerySize             : I32EnumAttrCase<"OpImageQuerySize", 104>;
+def SPV_OC_OpConvertFToU                : I32EnumAttrCase<"OpConvertFToU", 109>;
+def SPV_OC_OpConvertFToS                : I32EnumAttrCase<"OpConvertFToS", 110>;
+def SPV_OC_OpConvertSToF                : I32EnumAttrCase<"OpConvertSToF", 111>;
+def SPV_OC_OpConvertUToF                : I32EnumAttrCase<"OpConvertUToF", 112>;
+def SPV_OC_OpUConvert                   : I32EnumAttrCase<"OpUConvert", 113>;
+def SPV_OC_OpSConvert                   : I32EnumAttrCase<"OpSConvert", 114>;
+def SPV_OC_OpFConvert                   : I32EnumAttrCase<"OpFConvert", 115>;
+def SPV_OC_OpBitcast                    : I32EnumAttrCase<"OpBitcast", 124>;
+def SPV_OC_OpSNegate                    : I32EnumAttrCase<"OpSNegate", 126>;
+def SPV_OC_OpFNegate                    : I32EnumAttrCase<"OpFNegate", 127>;
+def SPV_OC_OpIAdd                       : I32EnumAttrCase<"OpIAdd", 128>;
+def SPV_OC_OpFAdd                       : I32EnumAttrCase<"OpFAdd", 129>;
+def SPV_OC_OpISub                       : I32EnumAttrCase<"OpISub", 130>;
+def SPV_OC_OpFSub                       : I32EnumAttrCase<"OpFSub", 131>;
+def SPV_OC_OpIMul                       : I32EnumAttrCase<"OpIMul", 132>;
+def SPV_OC_OpFMul                       : I32EnumAttrCase<"OpFMul", 133>;
+def SPV_OC_OpUDiv                       : I32EnumAttrCase<"OpUDiv", 134>;
+def SPV_OC_OpSDiv                       : I32EnumAttrCase<"OpSDiv", 135>;
+def SPV_OC_OpFDiv                       : I32EnumAttrCase<"OpFDiv", 136>;
+def SPV_OC_OpUMod                       : I32EnumAttrCase<"OpUMod", 137>;
+def SPV_OC_OpSRem                       : I32EnumAttrCase<"OpSRem", 138>;
+def SPV_OC_OpSMod                       : I32EnumAttrCase<"OpSMod", 139>;
+def SPV_OC_OpFRem                       : I32EnumAttrCase<"OpFRem", 140>;
+def SPV_OC_OpFMod                       : I32EnumAttrCase<"OpFMod", 141>;
+def SPV_OC_OpVectorTimesScalar          : I32EnumAttrCase<"OpVectorTimesScalar", 142>;
+def SPV_OC_OpMatrixTimesScalar          : I32EnumAttrCase<"OpMatrixTimesScalar", 143>;
+def SPV_OC_OpMatrixTimesMatrix          : I32EnumAttrCase<"OpMatrixTimesMatrix", 146>;
+def SPV_OC_OpIAddCarry                  : I32EnumAttrCase<"OpIAddCarry", 149>;
+def SPV_OC_OpISubBorrow                 : I32EnumAttrCase<"OpISubBorrow", 150>;
+def SPV_OC_OpIsNan                      : I32EnumAttrCase<"OpIsNan", 156>;
+def SPV_OC_OpIsInf                      : I32EnumAttrCase<"OpIsInf", 157>;
+def SPV_OC_OpOrdered                    : I32EnumAttrCase<"OpOrdered", 162>;
+def SPV_OC_OpUnordered                  : I32EnumAttrCase<"OpUnordered", 163>;
+def SPV_OC_OpLogicalEqual               : I32EnumAttrCase<"OpLogicalEqual", 164>;
+def SPV_OC_OpLogicalNotEqual            : I32EnumAttrCase<"OpLogicalNotEqual", 165>;
+def SPV_OC_OpLogicalOr                  : I32EnumAttrCase<"OpLogicalOr", 166>;
+def SPV_OC_OpLogicalAnd                 : I32EnumAttrCase<"OpLogicalAnd", 167>;
+def SPV_OC_OpLogicalNot                 : I32EnumAttrCase<"OpLogicalNot", 168>;
+def SPV_OC_OpSelect                     : I32EnumAttrCase<"OpSelect", 169>;
+def SPV_OC_OpIEqual                     : I32EnumAttrCase<"OpIEqual", 170>;
+def SPV_OC_OpINotEqual                  : I32EnumAttrCase<"OpINotEqual", 171>;
+def SPV_OC_OpUGreaterThan               : I32EnumAttrCase<"OpUGreaterThan", 172>;
+def SPV_OC_OpSGreaterThan               : I32EnumAttrCase<"OpSGreaterThan", 173>;
+def SPV_OC_OpUGreaterThanEqual          : I32EnumAttrCase<"OpUGreaterThanEqual", 174>;
+def SPV_OC_OpSGreaterThanEqual          : I32EnumAttrCase<"OpSGreaterThanEqual", 175>;
+def SPV_OC_OpULessThan                  : I32EnumAttrCase<"OpULessThan", 176>;
+def SPV_OC_OpSLessThan                  : I32EnumAttrCase<"OpSLessThan", 177>;
+def SPV_OC_OpULessThanEqual             : I32EnumAttrCase<"OpULessThanEqual", 178>;
+def SPV_OC_OpSLessThanEqual             : I32EnumAttrCase<"OpSLessThanEqual", 179>;
+def SPV_OC_OpFOrdEqual                  : I32EnumAttrCase<"OpFOrdEqual", 180>;
+def SPV_OC_OpFUnordEqual                : I32EnumAttrCase<"OpFUnordEqual", 181>;
+def SPV_OC_OpFOrdNotEqual               : I32EnumAttrCase<"OpFOrdNotEqual", 182>;
+def SPV_OC_OpFUnordNotEqual             : I32EnumAttrCase<"OpFUnordNotEqual", 183>;
+def SPV_OC_OpFOrdLessThan               : I32EnumAttrCase<"OpFOrdLessThan", 184>;
+def SPV_OC_OpFUnordLessThan             : I32EnumAttrCase<"OpFUnordLessThan", 185>;
+def SPV_OC_OpFOrdGreaterThan            : I32EnumAttrCase<"OpFOrdGreaterThan", 186>;
+def SPV_OC_OpFUnordGreaterThan          : I32EnumAttrCase<"OpFUnordGreaterThan", 187>;
+def SPV_OC_OpFOrdLessThanEqual          : I32EnumAttrCase<"OpFOrdLessThanEqual", 188>;
+def SPV_OC_OpFUnordLessThanEqual        : I32EnumAttrCase<"OpFUnordLessThanEqual", 189>;
+def SPV_OC_OpFOrdGreaterThanEqual       : I32EnumAttrCase<"OpFOrdGreaterThanEqual", 190>;
+def SPV_OC_OpFUnordGreaterThanEqual     : I32EnumAttrCase<"OpFUnordGreaterThanEqual", 191>;
+def SPV_OC_OpShiftRightLogical          : I32EnumAttrCase<"OpShiftRightLogical", 194>;
+def SPV_OC_OpShiftRightArithmetic       : I32EnumAttrCase<"OpShiftRightArithmetic", 195>;
+def SPV_OC_OpShiftLeftLogical           : I32EnumAttrCase<"OpShiftLeftLogical", 196>;
+def SPV_OC_OpBitwiseOr                  : I32EnumAttrCase<"OpBitwiseOr", 197>;
+def SPV_OC_OpBitwiseXor                 : I32EnumAttrCase<"OpBitwiseXor", 198>;
+def SPV_OC_OpBitwiseAnd                 : I32EnumAttrCase<"OpBitwiseAnd", 199>;
+def SPV_OC_OpNot                        : I32EnumAttrCase<"OpNot", 200>;
+def SPV_OC_OpBitFieldInsert             : I32EnumAttrCase<"OpBitFieldInsert", 201>;
+def SPV_OC_OpBitFieldSExtract           : I32EnumAttrCase<"OpBitFieldSExtract", 202>;
+def SPV_OC_OpBitFieldUExtract           : I32EnumAttrCase<"OpBitFieldUExtract", 203>;
+def SPV_OC_OpBitReverse                 : I32EnumAttrCase<"OpBitReverse", 204>;
+def SPV_OC_OpBitCount                   : I32EnumAttrCase<"OpBitCount", 205>;
+def SPV_OC_OpControlBarrier             : I32EnumAttrCase<"OpControlBarrier", 224>;
+def SPV_OC_OpMemoryBarrier              : I32EnumAttrCase<"OpMemoryBarrier", 225>;
+def SPV_OC_OpAtomicExchange             : I32EnumAttrCase<"OpAtomicExchange", 229>;
+def SPV_OC_OpAtomicCompareExchange      : I32EnumAttrCase<"OpAtomicCompareExchange", 230>;
+def SPV_OC_OpAtomicCompareExchangeWeak  : I32EnumAttrCase<"OpAtomicCompareExchangeWeak", 231>;
+def SPV_OC_OpAtomicIIncrement           : I32EnumAttrCase<"OpAtomicIIncrement", 232>;
+def SPV_OC_OpAtomicIDecrement           : I32EnumAttrCase<"OpAtomicIDecrement", 233>;
+def SPV_OC_OpAtomicIAdd                 : I32EnumAttrCase<"OpAtomicIAdd", 234>;
+def SPV_OC_OpAtomicISub                 : I32EnumAttrCase<"OpAtomicISub", 235>;
+def SPV_OC_OpAtomicSMin                 : I32EnumAttrCase<"OpAtomicSMin", 236>;
+def SPV_OC_OpAtomicUMin                 : I32EnumAttrCase<"OpAtomicUMin", 237>;
+def SPV_OC_OpAtomicSMax                 : I32EnumAttrCase<"OpAtomicSMax", 238>;
+def SPV_OC_OpAtomicUMax                 : I32EnumAttrCase<"OpAtomicUMax", 239>;
+def SPV_OC_OpAtomicAnd                  : I32EnumAttrCase<"OpAtomicAnd", 240>;
+def SPV_OC_OpAtomicOr                   : I32EnumAttrCase<"OpAtomicOr", 241>;
+def SPV_OC_OpAtomicXor                  : I32EnumAttrCase<"OpAtomicXor", 242>;
+def SPV_OC_OpPhi                        : I32EnumAttrCase<"OpPhi", 245>;
+def SPV_OC_OpLoopMerge                  : I32EnumAttrCase<"OpLoopMerge", 246>;
+def SPV_OC_OpSelectionMerge             : I32EnumAttrCase<"OpSelectionMerge", 247>;
+def SPV_OC_OpLabel                      : I32EnumAttrCase<"OpLabel", 248>;
+def SPV_OC_OpBranch                     : I32EnumAttrCase<"OpBranch", 249>;
+def SPV_OC_OpBranchConditional          : I32EnumAttrCase<"OpBranchConditional", 250>;
+def SPV_OC_OpReturn                     : I32EnumAttrCase<"OpReturn", 253>;
+def SPV_OC_OpReturnValue                : I32EnumAttrCase<"OpReturnValue", 254>;
+def SPV_OC_OpUnreachable                : I32EnumAttrCase<"OpUnreachable", 255>;
+def SPV_OC_OpGroupBroadcast             : I32EnumAttrCase<"OpGroupBroadcast", 263>;
+def SPV_OC_OpNoLine                     : I32EnumAttrCase<"OpNoLine", 317>;
+def SPV_OC_OpModuleProcessed            : I32EnumAttrCase<"OpModuleProcessed", 330>;
+def SPV_OC_OpGroupNonUniformElect       : I32EnumAttrCase<"OpGroupNonUniformElect", 333>;
+def SPV_OC_OpGroupNonUniformBroadcast   : I32EnumAttrCase<"OpGroupNonUniformBroadcast", 337>;
+def SPV_OC_OpGroupNonUniformBallot      : I32EnumAttrCase<"OpGroupNonUniformBallot", 339>;
+def SPV_OC_OpGroupNonUniformShuffle     : I32EnumAttrCase<"OpGroupNonUniformShuffle", 345>;
+def SPV_OC_OpGroupNonUniformShuffleXor  : I32EnumAttrCase<"OpGroupNonUniformShuffleXor", 346>;
+def SPV_OC_OpGroupNonUniformShuffleUp   : I32EnumAttrCase<"OpGroupNonUniformShuffleUp", 347>;
+def SPV_OC_OpGroupNonUniformShuffleDown : I32EnumAttrCase<"OpGroupNonUniformShuffleDown", 348>;
+def SPV_OC_OpGroupNonUniformIAdd        : I32EnumAttrCase<"OpGroupNonUniformIAdd", 349>;
+def SPV_OC_OpGroupNonUniformFAdd        : I32EnumAttrCase<"OpGroupNonUniformFAdd", 350>;
+def SPV_OC_OpGroupNonUniformIMul        : I32EnumAttrCase<"OpGroupNonUniformIMul", 351>;
+def SPV_OC_OpGroupNonUniformFMul        : I32EnumAttrCase<"OpGroupNonUniformFMul", 352>;
+def SPV_OC_OpGroupNonUniformSMin        : I32EnumAttrCase<"OpGroupNonUniformSMin", 353>;
+def SPV_OC_OpGroupNonUniformUMin        : I32EnumAttrCase<"OpGroupNonUniformUMin", 354>;
+def SPV_OC_OpGroupNonUniformFMin        : I32EnumAttrCase<"OpGroupNonUniformFMin", 355>;
+def SPV_OC_OpGroupNonUniformSMax        : I32EnumAttrCase<"OpGroupNonUniformSMax", 356>;
+def SPV_OC_OpGroupNonUniformUMax        : I32EnumAttrCase<"OpGroupNonUniformUMax", 357>;
+def SPV_OC_OpGroupNonUniformFMax        : I32EnumAttrCase<"OpGroupNonUniformFMax", 358>;
+def SPV_OC_OpSubgroupBallotKHR          : I32EnumAttrCase<"OpSubgroupBallotKHR", 4421>;
+def SPV_OC_OpTypeCooperativeMatrixNV    : I32EnumAttrCase<"OpTypeCooperativeMatrixNV", 5358>;
+def SPV_OC_OpCooperativeMatrixLoadNV    : I32EnumAttrCase<"OpCooperativeMatrixLoadNV", 5359>;
+def SPV_OC_OpCooperativeMatrixStoreNV   : I32EnumAttrCase<"OpCooperativeMatrixStoreNV", 5360>;
+def SPV_OC_OpCooperativeMatrixMulAddNV  : I32EnumAttrCase<"OpCooperativeMatrixMulAddNV", 5361>;
+def SPV_OC_OpCooperativeMatrixLengthNV  : I32EnumAttrCase<"OpCooperativeMatrixLengthNV", 5362>;
+def SPV_OC_OpSubgroupBlockReadINTEL     : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>;
+def SPV_OC_OpSubgroupBlockWriteINTEL    : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>;
+def SPV_OC_OpAssumeTrueKHR              : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>;
+def SPV_OC_OpAtomicFAddEXT              : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
+
+def SPV_OC_OpTypeJointMatrixINTEL       : I32EnumAttrCase<"OpTypeJointMatrixINTEL", 6119>;
+def SPV_OC_OpJointMatrixLoadINTEL       : I32EnumAttrCase<"OpJointMatrixLoadINTEL", 6120>;
+def SPV_OC_OpJointMatrixStoreINTEL      : I32EnumAttrCase<"OpJointMatrixStoreINTEL", 6121>;
+def SPV_OC_OpJointMatrixMadINTEL        : I32EnumAttrCase<"OpJointMatrixMadINTEL", 6122>;
 def SPV_OC_OpTypejointMatrixWorkItemLengthINTEL : I32EnumAttrCase<"OpJointMatrixWorkItemLengthINTEL", 6410>;
 
 def SPV_OpcodeAttr :
     SPV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [
       SPV_OC_OpNop, SPV_OC_OpUndef, SPV_OC_OpSourceContinued, SPV_OC_OpSource,
       SPV_OC_OpSourceExtension, SPV_OC_OpName, SPV_OC_OpMemberName, SPV_OC_OpString,
       SPV_OC_OpLine, SPV_OC_OpExtension, SPV_OC_OpExtInstImport, SPV_OC_OpExtInst,
       SPV_OC_OpMemoryModel, SPV_OC_OpEntryPoint, SPV_OC_OpExecutionMode,
SPV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [
       SPV_OC_OpAtomicIDecrement, SPV_OC_OpAtomicIAdd, SPV_OC_OpAtomicISub,
       SPV_OC_OpAtomicSMin, SPV_OC_OpAtomicUMin, SPV_OC_OpAtomicSMax,
       SPV_OC_OpAtomicUMax, SPV_OC_OpAtomicAnd, SPV_OC_OpAtomicOr, SPV_OC_OpAtomicXor,
       SPV_OC_OpPhi, SPV_OC_OpLoopMerge, SPV_OC_OpSelectionMerge, SPV_OC_OpLabel,
       SPV_OC_OpBranch, SPV_OC_OpBranchConditional, SPV_OC_OpReturn,
       SPV_OC_OpReturnValue, SPV_OC_OpUnreachable, SPV_OC_OpGroupBroadcast,
       SPV_OC_OpNoLine, SPV_OC_OpModuleProcessed, SPV_OC_OpGroupNonUniformElect,
       SPV_OC_OpGroupNonUniformBroadcast, SPV_OC_OpGroupNonUniformBallot,
+      SPV_OC_OpGroupNonUniformShuffle, SPV_OC_OpGroupNonUniformShuffleXor,
+      SPV_OC_OpGroupNonUniformShuffleUp, SPV_OC_OpGroupNonUniformShuffleDown,
       SPV_OC_OpGroupNonUniformIAdd, SPV_OC_OpGroupNonUniformFAdd,
       SPV_OC_OpGroupNonUniformIMul, SPV_OC_OpGroupNonUniformFMul,
       SPV_OC_OpGroupNonUniformSMin, SPV_OC_OpGroupNonUniformUMin,
       SPV_OC_OpGroupNonUniformFMin, SPV_OC_OpGroupNonUniformSMax,
       SPV_OC_OpGroupNonUniformUMax, SPV_OC_OpGroupNonUniformFMax,
       SPV_OC_OpSubgroupBallotKHR, SPV_OC_OpTypeCooperativeMatrixNV,
       SPV_OC_OpCooperativeMatrixLoadNV, SPV_OC_OpCooperativeMatrixStoreNV,
       SPV_OC_OpCooperativeMatrixMulAddNV, SPV_OC_OpCooperativeMatrixLengthNV,
       SPV_OC_OpSubgroupBlockReadINTEL, SPV_OC_OpSubgroupBlockWriteINTEL,
       SPV_OC_OpAssumeTrueKHR, SPV_OC_OpAtomicFAddEXT,
+
       SPV_OC_OpTypeJointMatrixINTEL, SPV_OC_OpJointMatrixLoadINTEL,
       SPV_OC_OpJointMatrixStoreINTEL, SPV_OC_OpJointMatrixMadINTEL,
       SPV_OC_OpTypejointMatrixWorkItemLengthINTEL
     ]>;
 
 // End opcode section. Generated from SPIR-V spec; DO NOT MODIFY!
 
 //===----------------------------------------------------------------------===//

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td

let description = [{
 
     <!-- End of AutoGen section -->
 
     ```
     scope ::= `"Workgroup"` | `"Subgroup"`
     integer-float-scalar-vector-type ::= integer-type | float-type |
                                `vector<` integer-literal `x` integer-type `>` |
                                `vector<` integer-literal `x` float-type `>`
-    group-non-uniform-broadcast-op ::= ssa-id `=` 
-              `spv.GroupNonUniformBroadcast` scope ssa_use,
-                ssa_use `:` integer-float-scalar-vector-type `,` integer-type
+    group-non-uniform-broadcast-op ::= ssa-id `=`
+        `spv.GroupNonUniformBroadcast` scope ssa_use, ssa_use
+        `:` integer-float-scalar-vector-type `,` integer-type
     ```mlir
 
     #### Example:
 
     ```
     %scalar_value = ... : f32
     %vector_value = ... : vector<4xf32>
     %id = ... : i32
let availability = [
     MaxVersion<SPV_V_1_6>,
     Extension<[]>,
     Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
+def SPV_GroupNonUniformShuffleOp : SPV_Op<"GroupNonUniformShuffle",
+    [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
+  let summary = [{
+    Result is the Value of the invocation identified by the id Id.
+  }];
+
+  let description = [{
+    Result Type  must be a scalar or vector of floating-point type, integer
+    type, or Boolean type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+     The type of Value must be the same as Result Type.
+
+    Id  must be a scalar of integer type, whose Signedness operand is 0.
+
+    The resulting value is undefined if Id is an inactive invocation, or is
+    greater than or equal to the size of the group.
+
+    <!-- End of AutoGen section -->
+
+    #### Example:
+
+    ```mlir
+    %0 = spv.GroupNonUniformShuffle <Subgroup> %val, %id : f32, i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPV_V_1_3>,
+    MaxVersion<SPV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPV_C_GroupNonUniformShuffle]>
+  ];
+
+  let arguments = (ins
+    SPV_ScopeAttr:$execution_scope,
+    SPV_ScalarOrVector:$value,
+    SPV_Integer:$id
+  );
+
+  let results = (outs
+    SPV_ScalarOrVector:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope operands attr-dict `:` type($value) `,` type($id)
+  }];
+}
+
+// -----
+
+def SPV_GroupNonUniformShuffleDownOp : SPV_Op<"GroupNonUniformShuffleDown",
+    [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
+  let summary = [{
+    Result is the Value of the invocation identified by the current
+    invocation’s id within the group + Delta.
+  }];
+
+  let description = [{
+    Result Type  must be a scalar or vector of floating-point type, integer
+    type, or Boolean type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+     The type of Value must be the same as Result Type.
+
+    Delta  must be a scalar of integer type, whose Signedness operand is 0.
+
+    Delta is treated as unsigned and the resulting value is undefined if
+    Delta is greater than or equal to the size of the group, or if the
+    current invocation’s id within the group + Delta is either an inactive
+    invocation or greater than or equal to the size of the group.
+
+    <!-- End of AutoGen section -->
+
+    #### Example:
+
+    ```mlir
+    %0 = spv.GroupNonUniformShuffleDown <Subgroup> %val, %delta : f32, i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPV_V_1_3>,
+    MaxVersion<SPV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPV_C_GroupNonUniformShuffleRelative]>
+  ];
+
+  let arguments = (ins
+    SPV_ScopeAttr:$execution_scope,
+    SPV_ScalarOrVector:$value,
+    SPV_Integer:$delta
+  );
+
+  let results = (outs
+    SPV_Type:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope operands attr-dict `:` type($value) `,` type($delta)
+  }];
+}
+
+// -----
+
+def SPV_GroupNonUniformShuffleUpOp : SPV_Op<"GroupNonUniformShuffleUp",
+    [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
+  let summary = [{
+    Result is the Value of the invocation identified by the current
+    invocation’s id within the group - Delta.
+  }];
+
+  let description = [{
+    Result Type  must be a scalar or vector of floating-point type, integer
+    type, or Boolean type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+     The type of Value must be the same as Result Type.
+
+    Delta  must be a scalar of integer type, whose Signedness operand is 0.
+
+    Delta is treated as unsigned and the resulting value is undefined if
+    Delta is greater than the current invocation’s id within the group or if
+    the selected lane is inactive.
+
+    <!-- End of AutoGen section -->
+
+    #### Example:
+
+    ```mlir
+    %0 = spv.GroupNonUniformShuffleUp <Subgroup> %val, %delta : f32, i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPV_V_1_3>,
+    MaxVersion<SPV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPV_C_GroupNonUniformShuffleRelative]>
+  ];
+
+  let arguments = (ins
+    SPV_ScopeAttr:$execution_scope,
+    SPV_ScalarOrVector:$value,
+    SPV_Integer:$delta
+  );
+
+  let results = (outs
+    SPV_Type:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope operands attr-dict `:` type($value) `,` type($delta)
+  }];
+}
+
+// -----
+
+def SPV_GroupNonUniformShuffleXorOp : SPV_Op<"GroupNonUniformShuffleXor",
+    [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
+  let summary = [{
+    Result is the Value of the invocation identified by the current
+    invocation’s id within the group xor’ed with Mask.
+  }];
+
+  let description = [{
+    Result Type  must be a scalar or vector of floating-point type, integer
+    type, or Boolean type.
+
+    Execution is a Scope. It must be either Workgroup or Subgroup.
+
+     The type of Value must be the same as Result Type.
+
+    Mask  must be a scalar of integer type, whose Signedness operand is 0.
+
+    The resulting value is undefined if current invocation’s id within the
+    group xor’ed with Mask is an inactive invocation, or is greater than or
+    equal to the size of the group.
+
+    <!-- End of AutoGen section -->
+
+    #### Example:
+
+    ```mlir
+    %0 = spv.GroupNonUniformShuffleXor <Subgroup> %val, %mask : f32, i32
+    ```
+  }];
+
+  let availability = [
+    MinVersion<SPV_V_1_3>,
+    MaxVersion<SPV_V_1_6>,
+    Extension<[]>,
+    Capability<[SPV_C_GroupNonUniformShuffle]>
+  ];
+
+  let arguments = (ins
+    SPV_ScopeAttr:$execution_scope,
+    SPV_ScalarOrVector:$value,
+    SPV_Integer:$mask
+  );
+
+  let results = (outs
+    SPV_Type:$result
+  );
+
+  let assemblyFormat = [{
+    $execution_scope operands attr-dict `:` type($value) `,` type($mask)
+  }];
+}
+
+// -----
+
 def SPV_GroupNonUniformUMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformUMax",
                                     SPV_Integer,
                                     [UnsignedOp]> {
   let summary = [{
     An unsigned integer maximum group operation of all Value operands
     contributed by active invocations in the group.
   }];
 

mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp

if (!idOp || !isa<spirv::ConstantOp,           // for normal constant
                       spirv::ReferenceOfOp>(idOp)) // for spec constant
       return emitOpError("id must be the result of a constant op");
   }
 
   return success();
 }
 
 //===----------------------------------------------------------------------===//
+// spv.GroupNonUniformShuffle*
+//===----------------------------------------------------------------------===//
+
+template <typename OpTy>
+static LogicalResult verifyGroupNonUniformShuffleOp(OpTy op) {
+  spirv::Scope scope = op.execution_scope();
+  if (scope != spirv::Scope::Workgroup && scope != spirv::Scope::Subgroup)
+    return op.emitOpError("execution scope must be 'Workgroup' or 'Subgroup'");
+
+  if (op.getOperands().back().getType().isSignedInteger())
+    return op.emitOpError("second operand must be a singless/unsigned integer");
+
+  return success();
+}
+
+LogicalResult spirv::GroupNonUniformShuffleOp::verify() {
+  return verifyGroupNonUniformShuffleOp(*this);
+}
+LogicalResult spirv::GroupNonUniformShuffleDownOp::verify() {
+  return verifyGroupNonUniformShuffleOp(*this);
+}
+LogicalResult spirv::GroupNonUniformShuffleUpOp::verify() {
+  return verifyGroupNonUniformShuffleOp(*this);
+}
+LogicalResult spirv::GroupNonUniformShuffleXorOp::verify() {
+  return verifyGroupNonUniformShuffleOp(*this);
+}
+
+//===----------------------------------------------------------------------===//
 // spv.SubgroupBlockReadINTEL
 //===----------------------------------------------------------------------===//
 
 ParseResult spirv::SubgroupBlockReadINTELOp::parse(OpAsmParser &parser,
                                                    OperationState &result) {
   // Parse the storage class specification
   spirv::StorageClass storageClass;
   OpAsmParser::UnresolvedOperand ptrInfo;

mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir

func.func @group_non_uniform_broadcast_vector(%value: vector<4xf32>) -> vector<4xf32> {
   %0 = spv.GroupNonUniformBroadcast <Subgroup> %value, %one : vector<4xf32>, i32
   return %0: vector<4xf32>
 }
 
 // -----
 
 func.func @group_non_uniform_broadcast_negative_scope(%value: f32, %localid: i32 ) -> f32 {
   %one = spv.Constant 1 : i32
-  // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}} 
+  // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}}
   %0 = spv.GroupNonUniformBroadcast <Device> %value, %one : f32, i32
   return %0: f32
 }
 
 // -----
 
 func.func @group_non_uniform_broadcast_negative_non_const(%value: f32, %localid: i32) -> f32 {
   // expected-error @+1 {{id must be the result of a constant op}}
func.func @group_non_uniform_smin_reduce(%val: i32) -> i32 {
   // CHECK: %{{.+}} = spv.GroupNonUniformSMin "Workgroup" "Reduce" %{{.+}} : i32
   %0 = spv.GroupNonUniformSMin "Workgroup" "Reduce" %val : i32
   return %0: i32
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
+// spv.GroupNonUniformShuffle
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @group_non_uniform_shuffle1
+func.func @group_non_uniform_shuffle1(%val: f32, %id: i32) -> f32 {
+  // CHECK: %{{.+}} = spv.GroupNonUniformShuffle <Subgroup> %{{.+}}, %{{.+}} : f32, i32
+  %0 = spv.GroupNonUniformShuffle <Subgroup> %val, %id : f32, i32
+  return %0: f32
+}
+
+// CHECK-LABEL: @group_non_uniform_shuffle2
+func.func @group_non_uniform_shuffle2(%val: vector<2xf32>, %id: i32) -> vector<2xf32> {
+  // CHECK: %{{.+}} = spv.GroupNonUniformShuffle <Subgroup> %{{.+}}, %{{.+}} : vector<2xf32>, i32
+  %0 = spv.GroupNonUniformShuffle <Subgroup> %val, %id : vector<2xf32>, i32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+func.func @group_non_uniform_shuffle(%val: vector<2xf32>, %id: i32) -> vector<2xf32> {
+  // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}}
+  %0 = spv.GroupNonUniformShuffle <Device> %val, %id : vector<2xf32>, i32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+func.func @group_non_uniform_shuffle(%val: vector<2xf32>, %id: si32) -> vector<2xf32> {
+  // expected-error @+1 {{second operand must be a singless/unsigned integer}}
+  %0 = spv.GroupNonUniformShuffle <Subgroup> %val, %id : vector<2xf32>, si32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+//===----------------------------------------------------------------------===//
+// spv.GroupNonUniformShuffleXor
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @group_non_uniform_shuffle1
+func.func @group_non_uniform_shuffle1(%val: f32, %id: i32) -> f32 {
+  // CHECK: %{{.+}} = spv.GroupNonUniformShuffleXor <Subgroup> %{{.+}}, %{{.+}} : f32, i32
+  %0 = spv.GroupNonUniformShuffleXor <Subgroup> %val, %id : f32, i32
+  return %0: f32
+}
+
+// CHECK-LABEL: @group_non_uniform_shuffle2
+func.func @group_non_uniform_shuffle2(%val: vector<2xf32>, %id: i32) -> vector<2xf32> {
+  // CHECK: %{{.+}} = spv.GroupNonUniformShuffleXor <Subgroup> %{{.+}}, %{{.+}} : vector<2xf32>, i32
+  %0 = spv.GroupNonUniformShuffleXor <Subgroup> %val, %id : vector<2xf32>, i32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+func.func @group_non_uniform_shuffle(%val: vector<2xf32>, %id: i32) -> vector<2xf32> {
+  // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}}
+  %0 = spv.GroupNonUniformShuffleXor <Device> %val, %id : vector<2xf32>, i32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+func.func @group_non_uniform_shuffle(%val: vector<2xf32>, %id: si32) -> vector<2xf32> {
+  // expected-error @+1 {{second operand must be a singless/unsigned integer}}
+  %0 = spv.GroupNonUniformShuffleXor <Subgroup> %val, %id : vector<2xf32>, si32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+//===----------------------------------------------------------------------===//
+// spv.GroupNonUniformShuffleUp
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @group_non_uniform_shuffle1
+func.func @group_non_uniform_shuffle1(%val: f32, %id: i32) -> f32 {
+  // CHECK: %{{.+}} = spv.GroupNonUniformShuffleUp <Subgroup> %{{.+}}, %{{.+}} : f32, i32
+  %0 = spv.GroupNonUniformShuffleUp <Subgroup> %val, %id : f32, i32
+  return %0: f32
+}
+
+// CHECK-LABEL: @group_non_uniform_shuffle2
+func.func @group_non_uniform_shuffle2(%val: vector<2xf32>, %id: i32) -> vector<2xf32> {
+  // CHECK: %{{.+}} = spv.GroupNonUniformShuffleUp <Subgroup> %{{.+}}, %{{.+}} : vector<2xf32>, i32
+  %0 = spv.GroupNonUniformShuffleUp <Subgroup> %val, %id : vector<2xf32>, i32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+func.func @group_non_uniform_shuffle(%val: vector<2xf32>, %id: i32) -> vector<2xf32> {
+  // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}}
+  %0 = spv.GroupNonUniformShuffleUp <Device> %val, %id : vector<2xf32>, i32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+func.func @group_non_uniform_shuffle(%val: vector<2xf32>, %id: si32) -> vector<2xf32> {
+  // expected-error @+1 {{second operand must be a singless/unsigned integer}}
+  %0 = spv.GroupNonUniformShuffleUp <Subgroup> %val, %id : vector<2xf32>, si32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+//===----------------------------------------------------------------------===//
+// spv.GroupNonUniformShuffleDown
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @group_non_uniform_shuffle1
+func.func @group_non_uniform_shuffle1(%val: f32, %id: i32) -> f32 {
+  // CHECK: %{{.+}} = spv.GroupNonUniformShuffleDown <Subgroup> %{{.+}}, %{{.+}} : f32, i32
+  %0 = spv.GroupNonUniformShuffleDown <Subgroup> %val, %id : f32, i32
+  return %0: f32
+}
+
+// CHECK-LABEL: @group_non_uniform_shuffle2
+func.func @group_non_uniform_shuffle2(%val: vector<2xf32>, %id: i32) -> vector<2xf32> {
+  // CHECK: %{{.+}} = spv.GroupNonUniformShuffleDown <Subgroup> %{{.+}}, %{{.+}} : vector<2xf32>, i32
+  %0 = spv.GroupNonUniformShuffleDown <Subgroup> %val, %id : vector<2xf32>, i32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+func.func @group_non_uniform_shuffle(%val: vector<2xf32>, %id: i32) -> vector<2xf32> {
+  // expected-error @+1 {{execution scope must be 'Workgroup' or 'Subgroup'}}
+  %0 = spv.GroupNonUniformShuffleDown <Device> %val, %id : vector<2xf32>, i32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+func.func @group_non_uniform_shuffle(%val: vector<2xf32>, %id: si32) -> vector<2xf32> {
+  // expected-error @+1 {{second operand must be a singless/unsigned integer}}
+  %0 = spv.GroupNonUniformShuffleDown <Subgroup> %val, %id : vector<2xf32>, si32
+  return %0: vector<2xf32>
+}
+
+// -----
+
+//===----------------------------------------------------------------------===//
 // spv.GroupNonUniformUMax
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @group_non_uniform_umax_reduce
 func.func @group_non_uniform_umax_reduce(%val: i32) -> i32 {
   // CHECK: %{{.+}} = spv.GroupNonUniformUMax "Workgroup" "Reduce" %{{.+}} : i32
   %0 = spv.GroupNonUniformUMax "Workgroup" "Reduce" %val : i32
   return %0: i32

mlir/test/Target/SPIRV/non-uniform-ops.mlir

spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
   }
 
   // CHECK-LABEL: @group_non_uniform_umin_reduce
   spv.func @group_non_uniform_umin_reduce(%val: i32) -> i32 "None" {
     // CHECK: %{{.+}} = spv.GroupNonUniformUMin "Workgroup" "Reduce" %{{.+}} : i32
     %0 = spv.GroupNonUniformUMin "Workgroup" "Reduce" %val : i32
     spv.ReturnValue %0: i32
   }
+
+  spv.func @group_non_uniform_shuffle(%val: f32, %id: i32) -> f32 "None" {
+    // CHECK: %{{.+}} = spv.GroupNonUniformShuffle <Subgroup> %{{.+}}, %{{.+}} : f32, i32
+    %0 = spv.GroupNonUniformShuffle <Subgroup> %val, %id : f32, i32
+    spv.ReturnValue %0: f32
+  }
+
+  spv.func @group_non_uniform_shuffle_up(%val: f32, %id: i32) -> f32 "None" {
+    // CHECK: %{{.+}} = spv.GroupNonUniformShuffleUp <Subgroup> %{{.+}}, %{{.+}} : f32, i32
+    %0 = spv.GroupNonUniformShuffleUp <Subgroup> %val, %id : f32, i32
+    spv.ReturnValue %0: f32
+  }
+
+  spv.func @group_non_uniform_shuffle_down(%val: f32, %id: i32) -> f32 "None" {
+    // CHECK: %{{.+}} = spv.GroupNonUniformShuffleDown <Subgroup> %{{.+}}, %{{.+}} : f32, i32
+    %0 = spv.GroupNonUniformShuffleDown <Subgroup> %val, %id : f32, i32
+    spv.ReturnValue %0: f32
+  }
+
+  spv.func @group_non_uniform_shuffle_xor(%val: f32, %id: i32) -> f32 "None" {
+    // CHECK: %{{.+}} = spv.GroupNonUniformShuffleXor <Subgroup> %{{.+}}, %{{.+}} : f32, i32
+    %0 = spv.GroupNonUniformShuffleXor <Subgroup> %val, %id : f32, i32
+    spv.ReturnValue %0: f32
+  }
 }