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Differential D133021

[AMDGPU][CodeGen] Pre-commit a test on (base | offset) SMEM loads for D132552.
ClosedPublic

Authored by kosarev on Aug 31 2022, 7:30 AM.

Details

Reviewers
foad
arsenm
rampitec
Commits
rG1f550d86b236: [AMDGPU][CodeGen] Pre-commit a test on (base | offset) SMEM loads for D132552.

Diff Detail

Event Timeline

kosarev created this revision.Aug 31 2022, 7:30 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 31 2022, 7:30 AM
Herald added subscribers: kerbowa, t-tye, tpr and 4 others. · View Herald Transcript
kosarev requested review of this revision.Aug 31 2022, 7:30 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 31 2022, 7:30 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B184361: Diff 456955.Aug 31 2022, 7:31 AM
kosarev added a parent revision: D132552: [AMDGPU][CodeGen] Support (base | offset) SMEM loads..Aug 31 2022, 7:35 AM
kosarev edited parent revisions, added: D130263: [AMDGPU][CodeGen] Support (soffset + offset) s_buffer_load's.; removed: D132552: [AMDGPU][CodeGen] Support (base | offset) SMEM loads..
kosarev added a child revision: D132552: [AMDGPU][CodeGen] Support (base | offset) SMEM loads..
kosarev mentioned this in D132552: [AMDGPU][CodeGen] Support (base | offset) SMEM loads..Aug 31 2022, 7:38 AM
kosarev added reviewers: foad, arsenm, rampitec.Aug 31 2022, 7:39 AM
foad accepted this revision.Aug 31 2022, 10:09 AM

Looks obviously fine. (You don't really need review for this kind of thing, especially if a reviewer requested it.)

This revision is now accepted and ready to land.Aug 31 2022, 10:09 AM
kosarev added a comment.Sep 1 2022, 1:56 AM

I'd prefer to land this after D130263 as D132552 depends on it anyway.

This revision was landed with ongoing or failed builds.Sep 5 2022, 5:21 AM
Closed by commit rG1f550d86b236: [AMDGPU][CodeGen] Pre-commit a test on (base | offset) SMEM loads for D132552. (authored by kosarev). · Explain Why
This revision was automatically updated to reflect the committed changes.
kosarev added a commit: rG1f550d86b236: [AMDGPU][CodeGen] Pre-commit a test on (base | offset) SMEM loads for D132552..

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
28 lines

Diff 457952

llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
; GISEL: S_BUFFER_LOAD_DWORD_SGPR_IMM %[[BASE]], %[[OFFSET]], 77, ; GISEL: S_BUFFER_LOAD_DWORD_SGPR_IMM %[[BASE]], %[[OFFSET]], 77,
define amdgpu_cs void @test_buffer_load_sgpr_plus_imm_offset(<4 x i32> inreg %base, i32 inreg %i, i32 addrspace(1)* inreg %out) { define amdgpu_cs void @test_buffer_load_sgpr_plus_imm_offset(<4 x i32> inreg %base, i32 inreg %i, i32 addrspace(1)* inreg %out) {
%off = add nuw nsw i32 %i, 77 %off = add nuw nsw i32 %i, 77
%v = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %base, i32 %off, i32 0) %v = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %base, i32 %off, i32 0)
store i32 %v, i32 addrspace(1)* %out, align 4 store i32 %v, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; TODO: Select S_BUFFER_LOAD_DWORD_SGPR_IMM here.
; GCN-LABEL: name: test_buffer_load_sgpr_or_imm_offset
; SDAG-DAG: %[[BASE0:.*]]:sgpr_32 = COPY $sgpr0
; SDAG-DAG: %[[BASE1:.*]]:sgpr_32 = COPY $sgpr1
; SDAG-DAG: %[[BASE2:.*]]:sgpr_32 = COPY $sgpr2
; SDAG-DAG: %[[BASE3:.*]]:sgpr_32 = COPY $sgpr3
; SDAG-DAG: %[[INDEX:.*]]:sgpr_32 = COPY $sgpr4
; SDAG-DAG: %[[SHIFT:.*]]:sreg_32 = S_LSHL_B32 %[[INDEX]],
; SDAG-DAG: %[[OR:.*]]:sreg_32 = S_OR_B32 killed %[[SHIFT]],
; SDAG-DAG: %[[BASE:.*]]:sgpr_128 = REG_SEQUENCE %[[BASE0]], %subreg.sub0, %[[BASE1]], %subreg.sub1, %[[BASE2]], %subreg.sub2, %[[BASE3]], %subreg.sub3
; SDAG: S_BUFFER_LOAD_DWORD_SGPR killed %[[BASE]], killed %[[OR]], 0
; GISEL-DAG: %[[BASE0:.*]]:sreg_32 = COPY $sgpr0
; GISEL-DAG: %[[BASE1:.*]]:sreg_32 = COPY $sgpr1
; GISEL-DAG: %[[BASE2:.*]]:sreg_32 = COPY $sgpr2
; GISEL-DAG: %[[BASE3:.*]]:sreg_32 = COPY $sgpr3
; GISEL-DAG: %[[INDEX:.*]]:sreg_32 = COPY $sgpr4
; GISEL-DAG: %[[SHIFT:.*]]:sreg_32 = S_LSHL_B32 %[[INDEX]],
; GISEL-DAG: %[[OR:.*]]:sreg_32 = S_OR_B32 %[[SHIFT]],
; GISEL-DAG: %[[BASE:.*]]:sgpr_128 = REG_SEQUENCE %[[BASE0]], %subreg.sub0, %[[BASE1]], %subreg.sub1, %[[BASE2]], %subreg.sub2, %[[BASE3]], %subreg.sub3
; GISEL: S_BUFFER_LOAD_DWORD_SGPR_IMM %[[BASE]], %[[OR]], 0,
define amdgpu_cs void @test_buffer_load_sgpr_or_imm_offset(<4 x i32> inreg %base, i32 inreg %i, i32 addrspace(1)* inreg %out) {
%shift = shl i32 %i, 7
%off = or i32 %shift, 5
%v = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %base, i32 %off, i32 0)
store i32 %v, i32 addrspace(1)* %out, align 4
ret void
}
declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32 immarg) #1 declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32 immarg) #1
declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) nounwind readnone willreturn declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) nounwind readnone willreturn
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare i32 @llvm.amdgcn.reloc.constant(metadata) #3 declare i32 @llvm.amdgcn.reloc.constant(metadata) #3
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
Show All 29 Lines